Design, Fabrication, and Evaluation of 2 and 3-Bit GaAs MESFET Analog-to-Digital Converter IC's

The analog-to-digital converter (A/D) is a critical component of a signal processing system. GHz-rate A/D's will be required in many future systems. While Si bipolar based A/D's can easily meet 4-6-bit resolution requirements, excessive power dissipation (1 W per bit) limits their operation to 100-400-MHz sampling rates. Recently, GaAs MES-FET's have demonstrated high frequency operation with relatively low power dissipation. This paper describes the design of 2- and 3-bit A/D's using GaAs MESFET's. Monolithic integrated A/D circuits were fabricated and successfully operated at gigahertz sampling rates. This sampling rate is the highest reported for any AD technology at room temperature. The power dissipation is 150-200 mW per bit. With further improvements in comparator sensitivity, the design can be extended to 4-bit A/D for GHz rate operation.     

四位GaAs超高速D/A转换电路的研究

本文简要介绍了目前国际上GaAs超高速D/A转换器的研制情况。在详细分析了几种常用类型D/A转换电路工作原理的基础上,结合现有GaAs VHSIC的制作工艺条件,设计并制作了一种4位单片集成GaAs MESFET D/A转换电路。测试结果表明,该电路分辨率为4位,转换速率办1Gs/s,建立时间小于1.0ns,微分线性误差小于±1/2LSB,功耗约为20mW。     

An optimized bit cell design for a pipelined current-mode algorithmic A/D converter

The design of a current-mode algorithmic bit cell for use in a pipelined A/D converter is presented. Design issues such as power supply rejection, charge-injection effects, the op-amp's gain/bandwidth tradeoff and the circuit's stability are considered. The circuit was implemented using a 1.2-µm CMOS process and required an area of 0.066 mm². The bit cell features a 10-bit resolution at an 83-kHz sampling rate and a 1.6-mW power dissipation.     

A GaAs phase digitizing and summing system for microwave signalstorage

The analysis, design, and development of a microwave signal storage prototype system using phase-quantization sampling are described. A GaAs 4-bit D/A converter has been demonstrated in a 3-bit DRFM (digital RF memory) prototype system with digital Si emitter-coupled logic (ECL) and RF microwave components at a sample rate of 200 MHz and exhibiting typically a -17-dBc harmonic suppression. A monolithic GaAs A/D and D/A converter has been demonstrated within an RF signal acquisition system. Performance data on the monolithic sampler reveal that the 3-bit quantization system exhibits signal reconstruction with harmonic suppression exceeding 25 dB across an IF bandwidth of greater than 900 MHz     

10 GB/s bit-synchronizer circuit with automatic timing alignment byclock phase shifting using quantum-well AlGaAs/GaAs/AlGaAs

A bit-synchronizer circuit is presented which operated up to a bit rate of Gb/s. The circuit comprises two master-slave flip -flops for data sampling, two EXCLUSIVE-OR gates for clock phase adjustment, an active signal splitter, and an EXCLUSIVE-OR gate for data transition detection. The gain of the EXCLUSIVE-OR phase comparator circuit is measured to be 302 mV/rad for a 1010-bit sequence. The margins for monotonous phase comparison are ±54° relative to the `in bit cell center' position of the sampling clock edge. The circuit is fabricated by using an enhancement/depletion 0.3 μm recessed-gate AlGaAs/GaAs/AlGaAs quantum-well FET process. The chip has a power dissipation of 230 mW at a supply voltage of 1.90 V     

A 40-GHz-bandwidth, 4-bit, time-interleaved A/D converter using photoconductive sampling

GaAs photoconductive switches have been integrated with two parallel 4-bit CMOS analog-to-digital (A/D) converter channels to demonstrate the time-interleaved sampling of wideband signals. The picosecond sampling aperture provided by low-temperature-grown-GaAs metal-semiconductor-metal switches, in combination with low-jitter short-pulse lasers, enables the optically-triggered sampling of electrical signals with tens of gigahertz bandwidth at low to medium resolution. A pair of parallel sampling paths, one for sampling and the second for feedthrough cancellation, generate a differential held signal that is quantized by a low-input capacitance, high-speed flash A/D converter. Dynamic offset averaging is employed to improve converter linearity. An experimental time-interleaved two-channel A/D converter provides about 3.5 effective bits of resolution for inputs up to 40 GHz when tested at an optically-triggered sampling rate of 160 MHz. The sampling rate was limited by the available optical source. Each A/D converter channel operates up to a 640-MHz conversion rate, dissipates 70 mW of power, and occupies an area of 150 /spl mu/m /spl times/ 450 /spl mu/m in a 2.5-V, 0.25-/spl mu/m CMOS technology.     

Design of GaAs 1k bit static RAM

A 1 k bit GaAs static RAM with E/D DCFL was designed and successfully fabricated by SAINT. A bit line pull-up was introduced to the design to make higher operation speed by 25 percent and reduce cell array power consumption by 50 percent. The RAM circuit was optimized in the points of a speed, a power, and an operating margin. A minimum address access time of 1.5 ns was measured for a total power dissipation of 369 mW. This performance is the best achieved so far, for practical application in cache or buffer memories.     

一种折叠内插式高速模数转换器的设计

描述了一种8bit,125MS/s采样率的折叠内插式ADC采用折叠内插结构设计。系统采用全并行结构的粗量化器实现高3位的量化编码,细量化部分采用折叠内插结构实现低5位的量化编码。电路设计中涉及分布式采样保持电路、折叠内插电路并在文章最后提出一种粗量化修正电路设计。通过HSPICE仿真测试,在采样频率为125MHz下对100M以内的输入频率测试,ADC信噪比达到40.0dB以上,功耗仅为170mW。     

High-performance low-power CMOS memories using silicon-on-sapphire technology

Complementary MOS silicon-on-sapphire inverters fabricated using silicon-gate technology and 5-/spl mu/m channel-length devices has achieved nanosecond propagation delays and picojoule dynamic power-x delay products. In addition to high switching speed and low dynamic power, inverters with low leakage currents and therefore low quiescent power have been obtained. Two complex CMOS/SOS memories that realize the performance attributes of the individual inverters have been fabricated. An aluminium-gate 256-bit fully decoded static random-access memory features a typical access time of 50 ns at 10 V with a power dissipation of 0.4 /spl mu/W/bit (quiescent) and 10 /spl mu/W/bit (dynamic). The access time at 5 V is typically 95 ns. A silicon-gate 256-bit dynamic shift register features operation at clock signals of 200 MHz at 10 V and 75 MHz at 5 V. The dynamic power dissipation at 50 MHz and 5 V is typically 90 /spl mu/W/bit.     

A 4160-bit C4D serial memory

A 4160-bit serial memory chip has been designed, fabricated, and tested using as the basic memory cell the conductively connected charge-coupled device (CCD) or C4D. The chip includes an inverting regenerator every 65 bits and a reading tap every 130 bits. Also on-chip is a recirculating amplifier which senses the charge packet as it reaches the end of the register and feeds it back to the input. This means that once data has been written onto the chip, it will be retained as long as the regenerator supply and the two clocks are on. The chip has two multiplexed halves to obtain a data rate of twice the clock frequency. The active area of the chip is 12 mm/SUP 2/ or 2900 /spl mu/m/SUP 2/ per bit. Operation was obtained for arbitrary data streams at clock rates of 1 kHz to 1.6 MHz (3.2 MHz data rate). Power dissipation varies linearly with frequency and is 16 /spl mu/W per bit at the highest frequency. Maximum read latency is 80 /spl mu/s at this frequency. This performance demonstrates the feasibility of the C4D as a component for a medium speed large-scale memory.     

GaAs low-power integrated circuits for a high-speed digital signalprocessor

A high-speed 4-bit ALU, 4×4-bit multiplier, and 8×8-bit multiplier/accumulator have been implemented in low-power GaAs enhanced/depletion E/D direct-coupled FET logic (DCFL). Circuits are fabricated with a high-yield titanium tungsten nitride self-aligned gate MESFET process. The 4-bit ALU performs at up to 1.2 GHz with only 131-mW power dissipation. The multiplication time for the 4×4-bit array multiplier is 940 ps, which is the fastest multiplication time reported for any semiconductor technology. The 8×8-bit two's complement multiplier/accumulator uses 4278 FETs (1317 logic gates) and exhibits a multiplication time of 3.17 ns. the fastest yet reported for a multiplier of this type. Yield on the best wafer for the 4×4-bit and 8×8-bit circuits is 94 and 43%, respectively. A digital arithmetic subsystem has been demonstrated, consisting of the 8×8-bit multiplier/accumulator, two of the 4-bit ALUs, three logical multiplexers, and a logical demultiplexer. The subsystem performs arithmetic and logic functions required in signal processing at clock rates as high as 325 MHz     

A gallium arsenide SDFL gate array with on-chip RAM

A GaAs gate array has been fabricated featuring 432 SDFL cells, 32 interface I/O buffer cells, and four 4 × 4 bit static RAM's. Each Schottky diode field-effect transistor logic (SDFL) cell can be programmed with 3 options as an unbuffered or buffered NOR gate, or as a dual OR/NAND gate. The interface I/O cell can be programmed for ECL, TTL, CMOS, and SDFL logic families. Each 16 bit RAM is fully decoded using depletion mode MESFET's with SDFL circuit approach. The chip size is 147 mils × 185 mils, and the total power dissipation of the whole chip is less than 3 W. Testing of the cell array has given yields of 70 percent for the 101-stage ring oscillators and about 90 percent for the I/O buffers, memory cells, and 25-stage ring oscillators in a wafer. The best speed performance of the unbuffered SDFL gate is 150 ps for fan-out and fan-in of 1 and the load of 100 µm of interconnect. The average power of the SDFL gate is 1.5 mW. The results demonstrated the feasibility of the GaAs SDFL for fast gate array and memory applications.     

Analysis and application of a novel model for estimating powerdissipation of optical interconnections as a function of transmissionbit error rate

This paper proposes a novel model for estimating power dissipation of optical/electrical interconnections as a function of transmission bit error rate. This model is applied to a simplified optoelectronic transmitter and receiver configuration in which a photodetector is directly connected to the decision circuit. It is analytically verified that this configuration can achieve error-free operation with low power under practical operating conditions. A comparison between optical and electrical interconnections based on this simplified configuration is performed. This result shows the interconnection length and bit rate at which optical interconnection is superior in terms of power dissipation to electrical interconnection, Only optical interconnections achieve error-free operation with 40 mW power dissipation at a transmission bit rate of 10 Gb/s and an interconnection length over 7 m     

2位GaAs超高速模-数转换电路的设计与制作

模数(A-D)转换电路是信号处理系统中的一种关键性元件。本文结合现有GaAs起高速集成电路工艺,提出了一种2位GaAs A-D转换电路的设计方法,并制作出了单片形式的2位GaAs A/D转换电路。实验结果表明,该电路能正常工作在1Gs/s的转换速率下。它的转换时间小于1.0ns,电路功耗不高于340mW。这说明它在速度和功耗方面已展现出比Si双极电路更为广阔的发展前景。     

A Low Power, Scalable, DAC Architecture for Liquid Crystal Display Drivers

The proliferation of portable electronic products such as cellular telephones and personal digital assistants has created a high demand for small format liquid crystal displays (LCD) with increasing bit resolution. The electronic drivers for these display applications must adhere to stringent power and area budgets. This paper describes a low-power, area efficient, scalable, digital-analog conversion (DAC) integrated circuit architecture optimized for driving small format LCDs. A 12 channel, 9-bit DAC driver based on this architecture, implemented in 0.5 $mu$ m CMOS technology and suitable for 1/4 VGA resolution displays, exhibited a 2 MSPS conversion rate, 252 $muhbox{W}$ power dissipation per channel using a 5 V supply, and a per DAC die area of 0.042 $hbox{mm}^{2}$. This performance sets a new standard for DAC display drivers in joules per bit areal density at less than 0.58 pJ per bit per $hbox{mm}^{2}$ .      

A monolithic video A/D converter

The design and measured performance of a fully parallel monolithic 8-bit A/D converter is reported. The required comparators and combining logic were designed and fabricated with a standard high-performance triple-diffused technology. A bipolar comparator circuit giving good performance with high input impedance is described. Circuit operation is reported at sample rates up to 30 megasamples per second (MS/s), with analog input signal power at frequencies up to 6 MHz. Full 8-bit linearity was achieved. An SNR of 42-44 dB was observed at input signal frequencies up to 5.3 MHz.     

Low-power CMOS fully-folding ADC with a mixed-averaging distributed T/H circuit

This paper describes an 8-bit 125 Mhzlow-powerCMOS fully-foldinganalog-to-digital converter(ADC).A novel mixed-averaging distributed T/H circuit is proposed to improve the accuracy. Folding circuits are not only used in the fine converter but also in the coarse one and in the bit synchronization block to reduce the number of comparators for low power. This ADC is implemented in 0.5μm CMOS technology and occupies a die area of 2 × 1.5 mm~2. The measured differential nonlinearity and integral nonlinearity are 0.6 LSB/-0.8 LSB and 0.9 LSB/-1.2 LSB, respectively. The ADC exhibits 44.3 dB of signal-to-noise plus distortion ratio and 53.5 dB of spurious-free dynamic range for 1 MHz input sine-wave. The power dissipation is 138 mW at a sampling rate of 125 MHz at a 5 V supply.     

A current-mode bit-block circuit applicable to low-voltage, low-power pipeline video-speed A/D converters

This paper describes a study to determine if a current-mode circuit is useful as an analog circuit technique for realizing submicron mixed analog-and-digital MOS LSIs. To examine this, we designed and circuit simulated a new current-mode ADC bit-block for a 3 V, 10-bit level, 20 MHz ADC with a pipeline architecture and with full current-mode approach. A new precision current-mode sample-and-hold circuit which enables operation of a bit block at a clock speed of 20 MHz was developed. Current mismatches caused by the poor output impedance of a device were also decreased by adopting a cascode configuration throughout the design. Operation with a 3 V power supply and a 20 MHz clock speed in a 3-bit A/D configuration was verified through circuit simulation using standard CMOS 0.6 m device parameters. Gain error, mismatch of current, and linearity of the bit block with changing threshold voltage of a device were carefully examined. The bit block has a gain error of 0.2% (10-bit level), a linearity error of less than 0.1% (more than 10-bit level), and a current mismatch of DAC current sources in a bit cell of 0.2 to 0.4% (more than 8-bit level) with a 3 V power supply and 20 MHz clock speed. An 8-to 9-bit video-speed pipeline ADC can be realized without calibration. This confirms that the current-mode approach is effective.     

Pipelined GaAs carry lookahead adder

Based on the recently introduced GaAs pseudo-dynamic latched logic, the authors present a new type of carry lookahead adder (CLA) which combines the benefits of 0.6 μm E/D MESFET technology with the above mentioned class of logic. Consideration is given to power dissipation, taking into account that for high levels of integration, techniques to reduce the power budget are essential. As a result. The design of a four bit pipelined GaAs CLA operating at 800 MHz and exhibiting less than 1.8 mW of power dissipation is presented