A Low Power, Scalable, DAC Architecture for Liquid Crystal Display Drivers

The proliferation of portable electronic products such as cellular telephones and personal digital assistants has created a high demand for small format liquid crystal displays (LCD) with increasing bit resolution. The electronic drivers for these display applications must adhere to stringent power and area budgets. This paper describes a low-power, area efficient, scalable, digital-analog conversion (DAC) integrated circuit architecture optimized for driving small format LCDs. A 12 channel, 9-bit DAC driver based on this architecture, implemented in 0.5 $mu$ m CMOS technology and suitable for 1/4 VGA resolution displays, exhibited a 2 MSPS conversion rate, 252 $muhbox{W}$ power dissipation per channel using a 5 V supply, and a per DAC die area of 0.042 $hbox{mm}^{2}$. This performance sets a new standard for DAC display drivers in joules per bit areal density at less than 0.58 pJ per bit per $hbox{mm}^{2}$ .      

Design and Analysis of a 0.8–77.5-GHz Ultra-Broadband Distributed Drain Mixer Using 0.13-$mu$m CMOS Technology

A compact and broadband 0.8–77.5-GHz passive distributed drain mixer using standard 0.13-$mu$ m CMOS technology is presented in this paper. To extend the operation bandwidth, a uniform distributed topology is utilized for wideband matching. This paper also analyzes the device size and number of stages for the bandwidth of the CMOS distributed drain mixer. To optimize the conversion gain performance of the CMOS drain mixer, a gate bias optimization method is proposed and successfully implemented in the mixer design. This mixer consumes zero dc power and exhibits a measured conversion loss of ${hbox{5.5}} pm {hbox{1}}$ dB from 0.8 to 77.5 GHz with a compact size of 0.67$,times,$ 0.58 mm$^{2}$ . The output 1-dB compression point is ${-}{hbox{8.5}}$ dBm at 20 GHz. To best of our knowledge, this monolithic microwave integrated circuit has the widest operation bandwidth among CMOS wideband mixers to date with good conversion efficiency and zero dc power consumption.      

A CMOS Backgate-Coupled QVCO Based on Back-to-Back Series Varactor Configuration for Minimal AM-to-PM Noise Conversion

A 3.3 GHz CMOS quadrature voltage-controlled oscillator (QVCO) with very low phase noise is presented. The back-to-back series varactor configuration is employed in the LC tank for minimizing the AM-to-PM noise conversion. The backgate coupling for quadrature phase inter-locking further eliminates the noise contribution from coupling transistors and also reduces power consumption. The implemented QVCO in 0.18 $mu{rm m}$ CMOS technology achieved very low phase noise of ${- 133}~{rm dBc}/{rm Hz}$ at 1 MHz offset, where the total power consumption is 4.4 mW from a 1.0 V supply. The chip has a very high FOM of ${- 196.6}~{rm dBc}/{rm Hz}$.      

A Wideband PLL-Based G/FSK Transmitter in 0.18 $mu$m CMOS

A wideband phase-locked loop (PLL)-based G/FSK transmitter (TX) architecture is presented in this paper. In the proposed TX, the G/FSK data is applied outside the loop; hence, the data rate is not constrained by the PLL bandwidth. In addition, the PLL remains locked all the time, preventing the carrier frequency from drifting. In this architecture, the G/FSK modulation signal is generated from a proposed Sigma-Delta modulated Phase Rotator $(SigmaDelta{hbox{-PR}})$. By properly combining the multi-phase signals from the PLL output, the $SigmaDelta{hbox{-PR}}$ effectively operates as a fractional frequency divider, which can synthesize modulation signals with fine-resolution frequencies. The proposed $SigmaDelta{hbox{-PR}}$ adopts the input signal as the phase transition trigger, facilitating a glitch-free operation. The impact of the $SigmaDelta{hbox{-PR}}$ on the TX output noise is also analyzed in this paper. The proposed TX with the $SigmaDelta{hbox{-PR}}$ is digitally programmable and can generate various G/FSK signals for different applications. Fabricated in a 0.18 $muhbox{m}$ CMOS technology, the proposed TX draws 6.3 mA from a 1.4 V supply, and delivers an output power of $-$11 dBm. With a maximum data rate of 6 Mb/s, the TX achieves an energy efficiency of 1.5 nJ/bit.      

Super-Regenerative Architecture for UWB Pulse Detection: From Theory to RF Front-End Design

This paper presents an optimization of the super-regenerative architecture for impulse-based ultrawideband (UWB) technology dedicated to low-data-rate applications. The receiver belongs to the noncoherent category but enables nanosecond resolution for efficient location and tracking applications. Relying on analytical developments, this paper demonstrates how the super-regenerative architecture can suit the UWB context. Such a receiver enables a high RF gain and pulse-matched filter effect with tied power consumption to be achieved, thanks to the suitable control of the inherent unstable behavior. Bit-error-rate simulations based on this architecture are conducted and show a required $Eb/n_{0}$ of 12.5 dB at $10^{-4}$ in the additive white Gaussian noise channel. RF impairment impacts are evaluated and demonstrate good tolerance to the oscillator central frequency accordance and synchronization issue. Specifications of the circuit and controlled signal are drawn up. To validate this concept, the design of the RF front is performed in the CMOS 0.13-${rm mu}hbox{m}$ technology. It includes an LNA, a transconductance stage, and the detector formed by a fully integrated $LC$ -NMOS oscillator. This circuit consumes less than 10 mA for an RF gain above 50 dB and a 1-GHz-wide input signal bandwidth. The measured sensitivity is $-99 hbox{dBm}$ at $10^{-3}$ for a 1-Mb/s pulse rate for binary modulation.      

Low-Power Memory-Reduced Traceback MAP Decoding for Double-Binary Convolutional Turbo Decoder

Iterative decoding of convolutional turbo code (CTC) has a large memory power consumption. To reduce the power consumption of the state metrics cache (SMC), low-power memory-reduced traceback maximum a posteriori algorithm (MAP) decoding is proposed. Instead of storing all state metrics, the traceback MAP decoding reduces the size of the SMC by accessing difference metrics. The proposed traceback computation requires no complicated reversion checker, path selection, and reversion flag cache. For double-binary (DB) MAP decoding, radix-2 $,times,$2 and radix-4 traceback structures are introduced to provide a tradeoff between power consumption and operating frequency. These two traceback structures achieve an around 20% power reduction of the SMC, and around 7% power reduction of the DB MAP decoders. In addition, a high-throughput 12-mode WiMAX CTC decoder applying the proposed radix-2$,times,$2 traceback structure is implemented by using a 0.13-$mu$m CMOS process in a core area of 7.16 mm$^{2}$. Based on postlayout simulation results, the proposed decoder achieves a maximum throughput rate of 115.4 Mbps and an energy efficiency of 0.43 nJ/bit per iteration.      

A 9-pJ/Pulse 1.42-Vpp OOK CMOS UWB Pulse Generator for the 3.1–10.6-GHz FCC Band

This paper presents the design of a fully integrated ultra-wideband (UWB) pulse generator for the Federal Communications Commission (FCC) 3.1–10.6-GHz band. This generator is reserved for medium rate applications and achieves pulses for an on–off keying (OOK) modulation, pulse position modulation, or pulse interval modulation. This UWB transmitter is based on the impulse response filter method, which uses an edge combiner in order to excite an integrated bandpass filter. The circuit has been integrated in an ST-Microelectronics CMOS 0.13-$mu{hbox{m}}$ technology with 1.2-V supply voltage and the die size is 0.54 ${hbox{mm}}^{2}$. The pulse generator power consumption is 9 pJ per pulse and achieves a peak to peak magnitude of 1.42 V. The pulse is FCC compliant and the generator can be used with a rate up to 38 ${hbox{Mbs}}^{-1}$ with an OOK modulation. Based on the FCC power spectral density limitation, a sizing method is also presented.      

Novel Design of a 2.5-GHz Fully Integrated CMOS Butler Matrix for Smart-Antenna Systems

This paper presents a novel design of monolithic 2.5-GHz 4 $,times,$4 Butler matrix in 0.18- $mu$m CMOS technology. To achieve a full integration of smart antenna system monolithically, the proposed Butler matrix is designed with the phase-compensated transformer-based quadrature couplers and reflection-type phase shifters. The measurements show an accurate phase distribution of ${hbox{45}}{pm}{hbox{3}}^{circ}, ~{hbox{135}} pm {hbox{4}}^{circ}, ~ -{hbox{45}} pm {hbox{3}}^{circ}, ~{hbox{and}}~ -{hbox{135}} pm {hbox{4}}^{circ}$ with amplitude imbalance less than 1.5 dB. The antenna beamforming capability is also demonstrated by integrating the Butler matrix with a 1$,times,$ 4 monopole antenna array. The generated beams are pointing to $-{hbox{45}}^{circ}, ~ -{hbox{15}}^{circ}$ , 15$^{circ}$, and 45$^{circ}$, respectively, with less than 1$^{circ}$ error, which agree very well with the predictions. This Butler matrix consumes no dc power and only occupies the chip area of 1.36 $,times,$1.47 mm$^{2}$ . To our knowledge, this is the first demonstration of the single-chip Butler matrix in CMOS technology.      

A Highly Efficient Cipher Processor for Dual-Field Elliptic Curve Cryptography

This brief presents a high-throughput dual-field elliptic-curve-cryptography (ECC) processor that features all ECC functions with the programmable field and curve parameters over both the prime and binary fields. The proposed architecture is parallel and scalable. Using 0.13-$muhbox{m}$ CMOS technology, the core size of the processor is 1.44 $hbox{mm}^{2}$ . The measured results show that our ECC processor can perform one 160-bit point scalar multiplication with coordinate conversion over the prime field in 608 $muhbox{s}$ at 121 MHz with only 70.0 mW and the binary field in 372 $muhbox{s}$ at 146 MHz with 82.1 mW. The ECC processor chip outperforms other ECC hardware designs in terms of functionality, scalability, performance, cost effectiveness, and power consumption. In addition, the system analysis shows that our design is very efficient, compared with the software implementation for realistic security applications.      

A Low Phase-Noise QVCO With Integrated Back-Gate Coupling and Source Resistive Degeneration Technique

A 0.18 $mu$ m CMOS quadrature voltage-controlled oscillator with an extremely-low phase noise is presented. The excellent phase noise performance is accomplished by integration of the back-gate quadrature phase coupling and source resistive degeneration techniques into a complementary oscillator topology. The measured phase noise is as low as ${-}133$ dBc/Hz at 1 MHz offset from 3.01 GHz. The output phase imbalance is less than 1$^{circ}$ . The output power is $-1.25{pm} 0.5$ dBm and harmonic suppression is greater than 30.8 dBc. The oscillator core consumes 5.38 mA from a 1.5 V power supply. This QVCO achieves the highest figure-of-merit of ${-}193.5$ dBc/Hz.      

A 0.7 V Single-Supply SRAM With 0.495 $mu$m$^{2}$ Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme

We proposed a novel SRAM architecture with a high-density cell in low-supply-voltage operation. A self-write-back sense amplifier realizes cell failure rate improvement by more than two orders of magnitude at 0.6 V. A cascaded bit line scheme saves additional process cost for hierarchical bit line layer. A test chip with 256 kb SRAM utilizing 0.495 $mu$ m$^{2}$ cell in 65 nm CMOS technology demonstrated 0.7 V single-supply operation.      

A 0.13 $mu$ m CMOS Quad-Band GSM/GPRS/EDGE RF Transceiver Using a Low-Noise Fractional-N Frequency Synthesizer and Direct-Conversion Architecture

This paper presents a single-chip CMOS quad-band (850/900/1800/1900 MHz) RF transceiver for GSM/GPRS/EDGE applications which adopts a direct-conversion receiver, a direct-conversion transmitter and a fractional-N frequency synthesizer with a built-in DCXO. In the GSM mode, the transmitter delivers 4 dBm of output power with 1$^{circ}$ RMS phase error and the measured phase noise is ${-}$164.5 dBc/Hz at 20 MHz offset from a 914.8$~$MHz carrier. In the EDGE mode, the TX RMS EVM is 2.4% with a 0.5 $~$dB gain step for the overall 36 dB dynamic range. The RX NF and IIP3 are 2.7 dB/ ${-}$12 dBm for the low bands (850/900 MHz) and 3 dB/${-}$ 11 dBm for the high bands (1800/1900 MHz). This transceiver is implemented in 0.13 $mu$m CMOS technology and occupies 10.5 mm$^{2}$ . The device consumes 118 mA and 84 mA in TX and RX modes from 2.8 V, respectively and is housed in a 5$,times,$ 5 mm$^{2}$ 40-pin QFN package.      

A 12-bit 3.125 MHz Bandwidth 0–3 MASH Delta-Sigma Modulator

We demonstrate a 12-bit 0–3 MASH delta-sigma modulator with a 3.125 MHz bandwidth in a 0.18 $muhbox{m}$ CMOS technology. The modulator has an oversampling ratio of 8 (clock frequency of 50 MHz) and achieves a peak SNDR of 73.9 dB (77.2 $~$dB peak SNR) and consumes 24 mW from a 1.8 V supply. For comparison purposes, the modulator can be re-configured as a single-loop topology where a peak SNDR of 64.5 dB (66.3 dB peak SNR) is obtained with 22 mW power consumption. The energy required per conversion step for the 0–3 MASH architecture (0.95 pJ/step) is less than half of that required by the feedback topology (2.57 pJ/step).      

180$^{circ}$ and 90$^{circ}$ Phase Shifting Networks With an Octave Bandwidth and Small Phase Errors

A new phase shifting network for both 180 $^{circ}$ and 90 $^{circ}$ phase shift with small phase errors over an octave bandwidth is presented. The theoretical bandwidth is 67% for the 180$^{circ}$ phase bit and 86% for the 90$^{circ}$ phase bit when phase errors are $pm 2^{circ}$. The proposed topology consists of a bandpass filter (BPF) branch, consisting of a LC resonator and two shunt quarter-wavelength transmission lines (TLs), and a reference TL. A theoretical analysis is provided and scalable parameters are listed for both phase bits. To test the theory, phase shifting networks from 1 GHz to 3 GHz were designed. The measured phase errors of the 180$^{circ}$ and the 90$^{circ}$ phase bit are $pm 3.5^{circ}$ and $pm 2.5^{circ}$ over a bandwidth of 73% and 102% while the return losses are better than 18 dB and 12 dB, respectively.      

A 2.7 mW, 90.3 dB DR Continuous-Time Quadrature Bandpass Sigma-Delta Modulator for GSM/EDGE Low-IF Receiver in 0.25 $mu$m CMOS

Quadrature bandpass $SigmaDelta$ modulators based on polyphase filters are suited for analog-to-digital conversion in GSM/EDGE low-IF receivers. This paper presents a continuous-time quadrature bandpass sigma-delta $(SigmaDelta)$ modulator with a chain of integrators with weighted capacitive feedforward summation (CICFF) topology—which is a desirable solution for implementation in low power applications. A new compensation scheme for the polyphase filter is proposed. The summation of feedforward signals is implemented by weighted capacitors, without the necessity of any additional active components. The effectiveness of the proposed architecture is proved on a test chip which was designed in a standard 0.25 $muhbox{m}$ CMOS technology. The designed $SigmaDelta$ modulator has a power consumption of 2.7 mW at 1.8 V supply voltage, a dynamic range of 90.3 dB and a peak SNDR of 86.8 dB. The chip area is $0.5times 1.4 {hbox{mm}}^{2}$ including pads.      

A V-Band CMOS VCO With an Admittance-Transforming Cross-Coupled Pair

A novel circuit topology suitable for the implementation of CMOS voltage-controlled oscillators (VCOs) at millimeter-wave frequencies is presented in this paper. By employing transmission line segments to transform the admittance of the additional cross-coupled pair, the proposed LC-tank VCO can sustain fundamental oscillation at a frequency close to the $f _{max}$ of the transistors. Using a standard 0.18 $muhbox{m}$ CMOS process, a V-band VCO is realized for demonstration. The fabricated circuit exhibits a frequency tuning range of 670 MHz in the vicinity of 63 GHz. The measured output power and phase noise at 1 MHz offset are $-hbox{15~dBm}$ and $-hbox{89~dBc}/hbox{Hz}$ , respectively. Operated at a 1.8 $~$V supply voltage, the VCO core and the output buffer consume a total DC current of 55 mA.      

An 8.1 mW, 82 dB Delta-Sigma ADC With 1.9 MHz BW and $-$98 dB THD

A switched-capacitor low-distortion 15-level delta-sigma ADC is described. It achieves third-order noise shaping with only two integrators by using quantization noise coupling. Realized in a 0.18 $mu{hbox{m}}$ CMOS technology, it provides 81 dB SNDR, 82 dB dynamic range, and $-$98 dB THD in a signal bandwidth of 1.9 MHz. It dissipates 8.1 mW with a 1.5 $~$V power supply (analog power 4.4 mW, digital power 3.7$~$ mW). Its figure-of-merit is 0.25 pJ/conversion-step, which is among the best reported for discrete-time delta-sigma ADCs in wideband applications.      

A 107-pJ/bit 100-kb/s 0.18- $muhbox{m}$ Capacitive-Coupling Transceiver With Data Edge Signaling and DC Power-Free Pulse Detector for Printable Communication Sheet

A novel communication system which simultaneously achieves the mobility of wireless communication and the low-power performance of wireline communication is developed with a printable sheet. By combining meter-scale wireline communication and micrometer-scale wireless capacitive-coupling communication, the proposed communication system enables multiple electronic objects scattered over tables, walls, and ceilings to communicate contactlessly with each other by establishing communication paths without cumbersome physical connections. The transceiver developed for the 20 cm$times$ 20 cm communication sheet features a data-edge-signaling transmitter and a dc power-free pulse detector, thereby achieving the lowest energy of 107 pJ/bit at 100 kb/s in wireless communications at a distance of 60 cm in 0.18-$muhbox{m}$ CMOS.      

Compact $S$ -/$Ka$-Band CMOS Quadrature Hybrids With High Phase Balance Based on Multilayer Transformer Over-Coupling Technique

This paper presents compact CMOS quadrature hybrids by using the transformer over-coupling technique to eliminate significant phase error in the presence of low-$Q$ CMOS components. The technique includes the inductive and capacitive couplings, where the former is realized by employing a tightly inductive-coupled transformer and the latter by an additional capacitor across the transformer winding. Their phase balance effects are investigated and the design methodology is presented. The measurement results show that the designed 24-GHz CMOS quadrature hybrid has excellent phase balance within ${pm}{hbox{0.6}}^{circ}$ and amplitude balance less than ${pm} {hbox{0.3}}$ dB over a 16% fractional bandwidth with extremely compact size of 0.05 mm$^{2}$. For the 2.4-GHz hybrid monolithic microwave integrated circuit, it has measured phase balance of ${pm}{hbox{0.8}}^{circ}$ and amplitude balance of ${pm} {hbox{0.3}}$ dB over a 10% fractional bandwidth with a chip area of 0.1 mm$^{2}$ .      

A Floating-Gate-Based Programmable CMOS Reference

We describe a compact programmable CMOS reference, where the reference is determined by the charge difference between two floating-gate transistors, thereby making the reference insensitive to temperature and other environmental effects. Using floating-gate transistors adds programmability making a wide range of reference voltages possible with negligible long-term drift. A prototype circuit has been implemented in a 0.35-$mu{hbox {m}}$ CMOS process, and reference voltages ranging from 50 mV to 0.6 V have been achieved. We demonstrate a voltage reference programming accuracy of $pm40 muhbox{V}$ . Experimental results indicate a temperature sensitivity of approximately 53 $muhbox{V}/^{circ}hbox{C}$ for a nominal reference voltage of 0.4 V over a temperature range of $-60 ^{circ}hbox{C}$–$140 ^{circ}hbox{C}$.