A new technique in LDMOS transistors to improve the breakdown voltage and the lattice temperature

A new technique for high breakdown voltage of the LDMOS device is proposed in this paper. The main idea in the proposed technique is to insert the P⁺ silicon windows in the buried oxide at the interface of the n-drift to improve the breakdown voltage, electric field and maximum lattice temperature. The proposed structure is called as P⁺ window LDMOS (PW-LDMOS). It is shown by extending the depletion region between the P⁺ windows and the n-drift region, the breakdown voltage of PW-LDMOS increases to 405 V from 84 V of the conventional LDMOS on 1 µm silicon layer and 2 µm buried oxide layer. Also, effective values of doping, length, and depth of P⁺ window are investigated in the breakdown voltage. Moreover, a self-heating-effect is alleviated by the silicon windows in comparison with the conventional LDMOS. All the achieved results have been extracted by two-dimensional and two-carriers simulator ATLAS.     

LDMOS漂移区结构优化的模拟

RESURF LDM O S很难兼顾击穿电压和导通电阻对结构的要求。文中采用了D oub le RESURF(双重降低表面电场)新结构,使漂移区更易耗尽。从理论和模拟上验证了D oub le RESURF在漂移区浓度不变时对击穿电压的提高作用以及在保持击穿电压不变的情况下减小导通电阻的效果。同时,在LDM O S结构中加入D oub leRESURF结构也降低了工艺上对精度的要求。为新结构和新工艺的开发研制作前期设计和评估。     

一种LDMOS高压运算放大器的设计与实现

使用专门设计的LDMOS高压器件,实现了一个具有高压驱动能力(±150 V)和大增益(>80 dB)的CMOS运算放大器。模拟结果显示,N沟道和P沟道LDMOS晶体管的最大击穿电压都超过了320 V,高压隔离超过300 V,从而可以确保其高压放大功能。该运算放大器适用于数字通信,如程控交换机中的高压驱动电路的单片集成。     

A novel high voltage lateral double diffused metal oxide semiconductor (LDMOS) device with a U-shaped buried oxide feature

A novel U-shape buried oxide lateral double diffused metal oxide semiconductor (LDMOS) is reported in this paper. The proposed structure features ionized charges in both sides of dielectric between source and gate region to enhance the breakdown voltage. The dielectric between drain and drift region affects on the breakdown voltage by adding a new peak in the electric field profile. Two dimensional simulation with a commercial software tool predicts significantly improved performance of the proposed device as compared to conventional LDMOS structures.     

Pulsed voltage driven organic field-effect transistors for high stability transient current measurements

In this article, we propose the usage of gate voltage pulses of alternating polarity, to effectively suppress the hysteresis in organic field effect transistors (OFETs). The hysteretic behaviour of poly(3-hexylthiophene-2,5-diyl) (P3HT) based OFETs is systematically investigated by using continuous and pulsed sweep voltage mode. On the basis of the experimental results, both time settings and mode of gate bias voltage influence the carrier transport in the semiconductor channel. Hysteresis-free transfer characteristic curves are obtained by applying diametrically opposed gate pulses of a few milliseconds in duration. Stable on-current transient measurements are also achieved by implementing the pulse mode, thus allowing on-line gas sensing measurements to be successfully performed. Finally, the response of the sensor upon exposure to different concentrations of analyte vapours is found to be in good agreement with the Langmuir adsorption isotherm model.     

三端自由高压LDMOS器件设计

应用RESURF原理，设计了三端自由的高压LDMOS器件。采用虚拟制造技术，分析比较了多种结构，对器件结构进行了优化。设计了与常规CMOS兼容的高压器件结构的制造方法和工艺。采用虚拟制造，得到NMOS和PMOS虚拟器件，击穿电压分别为350V和320V。     

高压平台上的脉冲电流测量

为了对高压平台上的脉冲电流信号进行测量,设计并制作了一个自积分式Rogowski线圈并通过光电转换,光纤传输等技术,将测量到的信号传输到低压端对信号进行监测。在对该测量系统进行标定时,脉冲信号源产生高压脉冲信号,然后使用示波器进行测量,得到一条测量电流和脉冲电压的关系曲线,其线性度良好,因此该装置能够用于高压脉冲电流的测量。     

Design and optimization of high voltage LDMOS transistors on 0.18 μm SOI CMOS technology

In this paper, we have studied the effect of systematic downscaling of MOS channel length of the performance of the hybrid GaN MOS-HEMT with numerical simulations. The improvement in on-state conduction, together with concomitant short channel effects, including drain induced barrier lowering (DIBL) is quantitatively evaluated. A specific on-resistance of 2.1 mΩ cm² has been projected for a MOS channel length of 0.38 μm. We also have assessed the impact of high-k gate dielectrics, such as Al₂O₃. In addition, we have found that adding a thin GaN cap layer on top of AlGaN barrier can help reducing short channel effects.     

飞机高压直流电源系统的设计与仿真

提出了一种新颖的适用于飞机的高压直流电源系统,该系统由永磁同步发电机、PWM整流器以及控制器组成,具有结构简单、可靠性高等优点,不仅可以保证输入电流为标准正弦波,而且在飞机转速发生变化或者负载发生改变的情况下,依然可以输出稳定高压直流。然后对该系统进行了仿真,仿真结果与理论分析一致。     

600 V高低压兼容BCD工艺及驱动电路设计

基于高压功率集成电路的关键参数性能要求和现有工艺条件,在国内3μmCMOS工艺基础上,开发出8～9μm薄外延上的600VLDMOS器件及高低压兼容BCD工艺,并设计出几款600V高压半桥栅驱动电路。该工艺在标准3μm工艺基础上增加N埋层、P埋层及P-top层,P埋层和P阱对通隔离,形成各自独立的N-外延岛。实验测试结果表明:LDMOS管耐压达680V以上,低压NMOS、PMOS及NPN器件绝对耐压达36V以上,稳压二极管稳压值为5.3V。按该工艺进行设计流片的电路整体参数性能满足应用要求,浮动偏置电压达780V以上。     

ESD应力下LDMOS器件软失效的分析及优化

分析了发生软失效的两种原因:电场诱导和热诱导。针对一种采用0.35μm BCD工艺的LDMOS器件,讨论了改变器件漂移区长度对软泄漏电流的影响。最终通过对漂移区长度以及源端和衬底接触间距的优化,消除了器件原先存在的软泄漏电流现象,并且没有过分增大器件的触发电压。     

RF LDMOS功率器件研制

基于ISE TCAD模拟软件对RF LDMOS器件的工艺流程和器件结构进行了优化设计,采用带栅极金属总线的版图结构降低栅电阻,同时简化了LDMOS器件的封装设计.通过实际流片和测试分析,重点讨论了漂移区注入剂量和漂移区长度对LDMOS器件的转移特性、击穿特性、截止频率及最大振荡频率的影响.测试结果表明该器件的阈值电压为1.8 V,击穿电压可达70 V,截止频率和最大振荡频率分别为9 GHz和12.6 GHz,并可提供0.7 W/mm的输出功率密度.     

补偿法测量电压和电流的研究

电压、电流的测量是工程实践中最基本的测量内容之一,由于电压表、电流表的内阻是客观存在的,必然给测量带来误差。为了减小甚至消除这种误差,可以改进测量方法,补偿测量法就是其中重要的一种。文中对有源二端网络中开路电压和短路电流测量的几种补偿测量方法进行了研究和比较,并通过实验进行了验证,实验结果与理论计算相吻合。     

单芯片大功率RFLDMOS晶体管设计与实验

传统射频LDMOS晶体管的源区采用重掺杂p+sinker结构,该结构会占据较大的芯片面积。文中采用槽型sinker结构,可将源区sinker面积减少1/3以上。通过流片实验,得到饱和电流为170 mA/mm、击穿电压120 V、截止频率和最大振荡频率分别为5.5 GHz和10 GHz的RF LDMOS器件。在50 V工作电压、1 090 MHz频点下栅宽345 mm单芯片器件的最大输出功率362 W,功率增益15.6 dB,漏极效率38.1%。     

Flexible air-stable three-dimensional polymer field-effect transistors with high output current density

Flexible air-stable short-channel polymer organic field-effect transistor (OFET) arrays with high saturated output current density are demonstrated by utilizing a novel solution-processed naphthobisthiadiazole (NTz) based donor–acceptor semiconducting polymer (PNTz4T) and designing a three-dimensional vertical channel structure with an extremely large ratio of channel width to channel length. The saturated mean field-effect mobility of 0.16 cm²/V s of the short-channel polymer devices remains over one month resulting in air-stable OFET arrays with high on/off ratio over 10⁶ and powerful current–density exceeding 0.3 A/cm² under low operation voltage, both of which meet the requirements for such applications as driving organic light-emitting diodes in active-matrix displays.     

用掺氧多晶硅钝化技术制造高可靠高压晶体管

论述了 SIPOS钝化的原理、生产 SIPOS晶体管的工艺步骤 ,以及在制造过程中易出现的问题和解决方法     

几种典型的电流源结构和高精度基准电流源的设计

本文介绍并分析了几种典型的电流源结构,并设计了一种具有良好稳定性和高精度的CMOS基准电流源.在高精度的基准电流源电路中使用了带隙电路,使电路获得一个不受电源电压、温度和工艺参数影响的基准电压,然后通过电压-电流转换电路获得稳定的基准电流.HSPICE的仿真结果表明:当温度从-55℃到125℃变化时,电流输出仅变化了0.004.     

高压LDMOS场极板的分析与设计

场板是高压LDMOS中普遍使用的一种结终端技术,对单阶梯LDMOS场板的长度、其下方氧化层厚度以及场氧侵蚀厚度等参数进行了模拟和分析,在此基础上设计了一种新型体硅双阶梯场板LDMOS,并对其具体参数进行了细致的模拟和分析.模拟结果表明,双阶梯场板LDMOS的击穿电压比单阶梯场板LDMOS提高了15.3%,导通电阻降低了17.1%,电流驱动能力也提高了8.5%.     

利用激光互感器测量高压输电线的电流

随着输电电压的不断提高．输电线路上测量电压、电流的互感器的绝缘费用不断提高,采用激光互感器进行测量可大大节约该项费用。本文较系统地介绍了一种利用激光互感器测量高压线大电流的系统,分析了该系统的工作原理和设计方法,并分析了测量误差。     

Device preparation and characterization of drain current transients in static induction micro transistors

Static induction transistors (SITs) based on copper phthalocyanine (CuPc) were prepared and the dependence of static and transient characteristics on the edge features of the patterned Al gate electrode was studied. Devices having Al gate electrodes deposited with and without a gap between a shadow mask and the substrate were prepared. Devices prepared in the presence of the gap produces a thin transparent edge for the Al gate electrode which enhances the modulation of the drain current by the gate voltage. However, a repetitive slow transient of the drain current was observed for the devices using gap. This transient is considered to be due to the charge carrier trapping at Al dots in the active channel region.