A new technique in LDMOS transistors to improve the breakdown voltage and the lattice temperature

A new technique for high breakdown voltage of the LDMOS device is proposed in this paper. The main idea in the proposed technique is to insert the P⁺ silicon windows in the buried oxide at the interface of the n-drift to improve the breakdown voltage, electric field and maximum lattice temperature. The proposed structure is called as P⁺ window LDMOS (PW-LDMOS). It is shown by extending the depletion region between the P⁺ windows and the n-drift region, the breakdown voltage of PW-LDMOS increases to 405 V from 84 V of the conventional LDMOS on 1 µm silicon layer and 2 µm buried oxide layer. Also, effective values of doping, length, and depth of P⁺ window are investigated in the breakdown voltage. Moreover, a self-heating-effect is alleviated by the silicon windows in comparison with the conventional LDMOS. All the achieved results have been extracted by two-dimensional and two-carriers simulator ATLAS.     

一种新型高压Triple RESURF SOI LDMOS

提出了一种新型Triple RESURF SOI LDMOS结构,该结构有一个Ｐ型埋层。首先,耗尽层能够在Ｐ型埋层的上下同时扩展与Triple RESURF机理相同,使得漂移区浓度提高,导通电阻降低。其次,当漂移区浓度较高时,Ｐ型埋层起到了降低体内电场的作用,并能够提高漏端纵向电场使得其电场分布更加均匀从而耐压增加。Triple RESURF结构在SOI LDMOS中首次提出。在６微米厚的SOI层以及２微米厚的埋氧层中获得了耐压300V的Triple RESURF SOI LDMOS,其导通电阻从Double RESURF SOI LDMOS的17.2mΩ.cm2降低到13.8mΩ.cm2。当外延层厚度增加时, Triple RESURF结构的效果更加明显,在相同耐压下,相对于Double RESURF,该结构能够在400V和550V的SOI LDMOS中分别降低29%和38%的导通电阻。     

A new high voltage SOI LDMOS with triple RESURF structure

A novel triple RESURF（T-resurf） SOI LDMOS structure is proposed.This structure has a P-type buried layer.Firstly,the depletion layer can extend on both sides of the P-buried layer,serving as a triple RESURF and leading to a high drift doping and a low on-resistance.Secondly,at a high doping concentration of the drift region, the P-layer can reduce high bulk electric field in the drift region and enhance the vertical electric field at the drain side,which results in uniform bulk electric field distributions and an enhanced BV.The proposed structure is used in SOI devices for the first time.The T-resurf SOI LDMOS with BV = 315 V is obtained by simulation on a 6μm-thick SOI layer over a 2μm-thick buried oxide layer,and its R_sp is reduced from 16.5 to 13.8 mΩ·cm² in comparison with the double RESURF（D-resurf） SOI LDMOS.When the thickness of the SOI layer increases, T-resurf SOI LDMOS displays a more obvious effect on the enhancement of BV²/R_on.It reduces R_sp by 25%in 400 V SOI LDMOS and by 38%in 550 V SOI LDMOS compared with the D-resurf structure.     

具有增强介质层电场的SJ-LDMOS

横向超结功率器件遭受衬底辅助耗尽效应,这破坏了超结的电荷平衡,降低了器件的耐压。本文研究了一种基于增强介质层电场的解决方法,以提高横向超结器件（SJ-LDMOS）的耐压。通过高密度的界面电荷增强埋氧层（BOX）的电场从而提高埋氧层的耐压,这可以削弱纵向电场对超结的影响,消除衬底辅助耗尽效应,促进超结电荷平衡。为了获得理想的线性电场增强效果,一种具有槽形埋氧层的超结器件（TBOX SJ-LDMOS）被提出。槽形埋氧层能根据纵向电场的大小自适应地收集空穴,在埋氧层表面形成近似线性的电荷分布,这促进了超结的电荷平衡,提高了SJ-LDMOS器件的耐压,并使其接近理想超结的耐压值。     

Super junction LDMOS with enhanced dielectric layer electric field for high breakdown voltage

The lateral super junction(SJ) power devices suffer the substrate-assisted depletion(SAD) effect,which breaks the charge balance of SJ resulting in the low breakdown voltage(BV).A solution based on enhancing the electric field of the dielectric buried layer is investigated for improving the BV of super junction LDMOSFET (SJ-LDMOS).High density interface charges enhance the electric field in the buried oxide(BOX) layer to increase the block voltage of BOX,which suppresses the SAD effect to achieve the charge balance of SJ.In order to obtain the linear enhancement of electric field,SOI SJ-LDMOS with trenched BOX is presented.Because the trenched BOX self-adaptively collects holes according to the variable electric field strength,the approximate linear charge distribution is formed on the surface of the BOX to enhance the electric field according to the need.As a result,the charge balance between N and P pillars of SJ is achieved,which improves the BV of SJ-LDMOS to close that of the idea SJ structure.     

LDMOS漂移区结构优化的模拟

RESURF LDM O S很难兼顾击穿电压和导通电阻对结构的要求。文中采用了D oub le RESURF(双重降低表面电场)新结构,使漂移区更易耗尽。从理论和模拟上验证了D oub le RESURF在漂移区浓度不变时对击穿电压的提高作用以及在保持击穿电压不变的情况下减小导通电阻的效果。同时,在LDM O S结构中加入D oub leRESURF结构也降低了工艺上对精度的要求。为新结构和新工艺的开发研制作前期设计和评估。     

一种LDMOS高压运算放大器的设计与实现

使用专门设计的LDMOS高压器件,实现了一个具有高压驱动能力(±150 V)和大增益(>80 dB)的CMOS运算放大器。模拟结果显示,N沟道和P沟道LDMOS晶体管的最大击穿电压都超过了320 V,高压隔离超过300 V,从而可以确保其高压放大功能。该运算放大器适用于数字通信,如程控交换机中的高压驱动电路的单片集成。     

Pulsed voltage driven organic field-effect transistors for high stability transient current measurements

In this article, we propose the usage of gate voltage pulses of alternating polarity, to effectively suppress the hysteresis in organic field effect transistors (OFETs). The hysteretic behaviour of poly(3-hexylthiophene-2,5-diyl) (P3HT) based OFETs is systematically investigated by using continuous and pulsed sweep voltage mode. On the basis of the experimental results, both time settings and mode of gate bias voltage influence the carrier transport in the semiconductor channel. Hysteresis-free transfer characteristic curves are obtained by applying diametrically opposed gate pulses of a few milliseconds in duration. Stable on-current transient measurements are also achieved by implementing the pulse mode, thus allowing on-line gas sensing measurements to be successfully performed. Finally, the response of the sensor upon exposure to different concentrations of analyte vapours is found to be in good agreement with the Langmuir adsorption isotherm model.     

A novel high voltage lateral double diffused metal oxide semiconductor (LDMOS) device with a U-shaped buried oxide feature

A novel U-shape buried oxide lateral double diffused metal oxide semiconductor (LDMOS) is reported in this paper. The proposed structure features ionized charges in both sides of dielectric between source and gate region to enhance the breakdown voltage. The dielectric between drain and drift region affects on the breakdown voltage by adding a new peak in the electric field profile. Two dimensional simulation with a commercial software tool predicts significantly improved performance of the proposed device as compared to conventional LDMOS structures.     

Improvements on high voltage performance of power static induction transistors

A novel structure for designing and fabricating a power static induction transistor (SIT) with excellent high breakdown voltage performance is presented. The active region of the device is designed to be surrounded by a deep trench to cut off the various probable parasitical effects that may degrade the device performance, and to avoid the parallel-current effect in particular. Three ring-shape junctions (RSJ) are arranged around the gate junction to reduce the electric field intensity. It is important to achieve maximum gate-source breakdown voltage BVGS, gate-drain breakdown voltage BVGD and blocking voltage for high power application. A number of technological methods to increase BVgd and BVGs are presented. The BVGS of the power SIT has been increased to 110 V from a previous value of 50-60 V, and the performance of the power SIT has been greatly improved. The optimal distance between two adjacent ring-shape junctions and the trench depth for the maximum B VGS of the structure are also presented.     

电力静电感应晶体管大电压特性的改善

A novel structure for designing and fabricating a power static induction transistor（SIT）with excellent high breakdown voltage performance is presented.The active region of the device is designed to be surrounded by a deep trench to cut off the various probable parasitical effects that may degrade the device performance,and to avoid the parallel-current effect in particular.Three ring-shape junctions（RSJ）are arranged around the gate junction to reduce the electric field intensity.It is important to achieve maximum gate–source breakdown voltage BVGS, gate–drain breakdown voltage BVGD and blocking voltage for high power application.A number of technological methods to increase BVGD and BVGS are presented.The BVGS of the power SIT has been increased to 110 V from a previous value of 50–60 V,and the performance of the power SIT has been greatly improved.The optimal distance between two adjacent ring-shape junctions and the trench depth for the maximum BVGS of the structure are also presented.     

一种RESURF效应增强的高压低阻槽型SOI LDMOS

本文提出一种RESURF效应增强（Enhanced RESURF Effect）的高压低阻SOI LDMOS（ER-LDMOS）新结构,并研究其工作机理。ER-LDMOS的主要特征是：漂移区中具有氧化物槽;氧化物槽靠近体区一侧具有P条;氧化物槽下方的N型漂移区中具有埋P层。首先,从体区延伸到氧化物槽底部的P条,不仅起到纵向结终端扩展的作用,而且具有纵向RESURF效果,此二者都优化体内电场分布且提高漂移区掺杂浓度;其次,埋P层在漂移区中形成triple RESURF效果,能够进一步优化体内电场并降低导通电阻;第三,漂移区中的氧化物槽沿纵向折叠漂移区,减小了器件元胞尺寸,进一步降低比导通电阻;第四,P条、埋P层、氧化物槽和埋氧层对N型漂移区形成多维耗尽作用,实现增强的RESURF效应,可达到提高漂移区掺杂浓度与优化电场分布的目的,从而降低导通电阻且提高器件耐压。仿真结果表明,在相同的器件尺寸参数下,与常规槽型SOI LDMOS相比,ER-LDMOS击穿电压提高67%,比导通电阻降低91%。     

Scalable general high voltage MOSFET model including quasi-saturation and self-heating effects

In this work, we present for the first time, a highly scalable general high voltage MOSFET model, which can be used for any high voltage MOSFET with extended drift region. This model includes physical effects like the quasi-saturation, impact-ionization and self-heating, and a new general model for drift resistance. The model is validated on the measured characteristics of two widely used high voltage devices in the industry i.e. LDMOS and VDMOS devices, and implemented on commercial circuit simulators like SABER (Synopsys), ELDO (Mentor Graphics), Spectre (Cadence) and UltraSim (Cadence). The accuracy of the model is better than 10% for DC I–V and g–V characteristics and shows good behavior for all capacitances which are unique for these devices showing peaks and shift of peaks with bias variation. The model also exhibits excellent scalability with transistor width, drift length, number of fingers and temperature.     

三端自由高压LDMOS器件设计

应用RESURF原理，设计了三端自由的高压LDMOS器件。采用虚拟制造技术，分析比较了多种结构，对器件结构进行了优化。设计了与常规CMOS兼容的高压器件结构的制造方法和工艺。采用虚拟制造，得到NMOS和PMOS虚拟器件，击穿电压分别为350V和320V。     

浮空层结构的分析

分析了REBULF LDMOS的实验结果，由击穿电压的测试结果验证了模拟仿真中发现的漏电流增加源于n+浮空层的作用，但暴露于表面的n+p结的漏电流使击穿电压降低. 为了解决这个问题，文中分析了具有部分n+浮空层的REBULF LDMOS结构，此结构不但具有降低体内电场的REBULF效应，而且终止于源端体内的n+p结解决了文献［10］中的大漏电流问题. 分析结果表明，击穿电压较一般RESURF LDMOS结构提高60%以上.     

高压平台上的脉冲电流测量

为了对高压平台上的脉冲电流信号进行测量,设计并制作了一个自积分式Rogowski线圈并通过光电转换,光纤传输等技术,将测量到的信号传输到低压端对信号进行监测。在对该测量系统进行标定时,脉冲信号源产生高压脉冲信号,然后使用示波器进行测量,得到一条测量电流和脉冲电压的关系曲线,其线性度良好,因此该装置能够用于高压脉冲电流的测量。     

Creation of a new high voltage device with capable of enhancing driving current and breakdown voltage

This work reports a novel SOI MESFET including silicon N-type and P-type wells inside the drift and buried oxide regions. The drift-diffusion equations along with the main physical models such as impact ionization, Shockley-Read-Hall and self-heating effect are carefully solved inside the structures. Modification of the potential profile occurs in the channel region and results in decrease in peak electric field. Output power density is successfully boosted owing to improved driving current and breakdown voltage, simultaneously. In addition, self-heating effect is alleviated in the proposed structure due to decreased effective thermal resistance of the channel region. Comprehensive DC and AC performance comparisons show that the proposed device promises a more reliable candidate than the conventional SOI structure for high voltage applications.     

Design and optimization of high voltage LDMOS transistors on 0.18 μm SOI CMOS technology

In this paper, we have studied the effect of systematic downscaling of MOS channel length of the performance of the hybrid GaN MOS-HEMT with numerical simulations. The improvement in on-state conduction, together with concomitant short channel effects, including drain induced barrier lowering (DIBL) is quantitatively evaluated. A specific on-resistance of 2.1 mΩ cm² has been projected for a MOS channel length of 0.38 μm. We also have assessed the impact of high-k gate dielectrics, such as Al₂O₃. In addition, we have found that adding a thin GaN cap layer on top of AlGaN barrier can help reducing short channel effects.     

飞机高压直流电源系统的设计与仿真

提出了一种新颖的适用于飞机的高压直流电源系统,该系统由永磁同步发电机、PWM整流器以及控制器组成,具有结构简单、可靠性高等优点,不仅可以保证输入电流为标准正弦波,而且在飞机转速发生变化或者负载发生改变的情况下,依然可以输出稳定高压直流。然后对该系统进行了仿真,仿真结果与理论分析一致。     

600 V高低压兼容BCD工艺及驱动电路设计

基于高压功率集成电路的关键参数性能要求和现有工艺条件,在国内3μmCMOS工艺基础上,开发出8～9μm薄外延上的600VLDMOS器件及高低压兼容BCD工艺,并设计出几款600V高压半桥栅驱动电路。该工艺在标准3μm工艺基础上增加N埋层、P埋层及P-top层,P埋层和P阱对通隔离,形成各自独立的N-外延岛。实验测试结果表明:LDMOS管耐压达680V以上,低压NMOS、PMOS及NPN器件绝对耐压达36V以上,稳压二极管稳压值为5.3V。按该工艺进行设计流片的电路整体参数性能满足应用要求,浮动偏置电压达780V以上。