未来通信处理器将使DSP和RISC组合在一起

未来通信处理器将使ＤＳＰ和ＲＩＳＣ组合在一起未来嵌入式通信处理要求采用混合体系结构的单一处理器，把当今的ＲＩＳＣ和ＤＳＰ机器的最特性组合在一起１９９６年技术预测Ｈｉｔａｃｈｉ　Ａｍｅｒｉｃａ公司Ｄａｎ　Ｍａｎｓｕｒ集成还是不集成？如果您在谈论数字信号...     

微处理器再上一层楼 闪存入驻单片机和DSP

ＰｅｎｔｉｕｍＩＩ处理器采用ＤＩＢ结构，总线带宽大幅度提高；新ＲＩＳＣ型处理器，符合民用产品智能化要求，但系统级集成问题还有待解决；单片微型机开始内置闪速存储器；ＤＳＰ广泛用于移动电话机、硬盘机和调制解调器；采用ＤＳＰ和闪速存储器的调制解调器，便于通...     

元器件快讯

新型ＤＳＰ芯片ＴＭＳ３２０Ｃ５４７０／５４７１德州仪器（ＴＩ）公司最近又推出两款新型ＤＳＰ芯片ＴＭＳ３２０Ｃ５４７０和ＴＭＳ３２０Ｃ５４７１ ,通过这两款集成高效可编程ＴＭＳ３２０ＤＳＰ和ＲＩＳＣ处理器可支持嵌入式操作系统 ,并可在功耗降低约３０%的同时使成本和尺寸再缩减４０ %。这两款器件将可编程ＴＭＳ３２０Ｃ５０００ＤＳＰ与ＡＲＭ７Ｔｈｕｍｂ精简指令集（ＲＩＳＣ）处理器结合在一起 ,因而可支持那些已被广泛应用的嵌入式操作系统。同时可加快实时应用产品的上市时间 ,其中包括文本语音转换、无线数据、语音识别…     

体积小功耗低的RISC处理器

体积小功耗低的ＲＩＳＣ处理器日本ＮＥＣ公司研制出的３２ｂｉｔＲＩＳＣ处理器，在一块７．２ｍｍ×７．４ｍｍ的芯片上集成有２４万个器件，据称。在同类产品中封装最小。功耗和工作电压最低。新处理器型号为ＰＤ７０７３１Ｖ８０５，静态设计应用０．８μｍ铝双层布线...     

国外消息

国外消息▲东芝的ＭＰＥＧ┐２解码ＩＣ东芝的美洲电子元件公司推出了用于机顶盒与ＤＶＤ的解码系统ＩＣ。ＴＣ８１２２０Ｆ是满足该公司要求的完整的解码系统，将用于交互电视，是工业界最高水平的单片集成电路。其功能包括东芝的Ｒ３９００ＭＩＰＳＲＩＳＣ处理器芯片核...     

TI DSP的软件设计方法

查询号：１３１数字信号处理器（ＤＳＰ）是一种可编程的高性能处理器,近年来发展很快,它不仅适用于数字信号处理,而且在图像处理、语音处理、通信等领域都得到了广泛的应用。德州仪器公司（ＴＩ）是当今世界ＤＳＰ（ＤＳＰ）芯片的主要供应商之一,其ＤＳＰ芯片可分为两类：一类是定点ＤＳＰ,包括Ｃ１Ｘ,Ｃ２Ｘ,Ｃ２ＸＸ,Ｃ５Ｘ,Ｃ５４Ｘ,Ｃ６２Ｘ等;另一类是浮点ＤＳＰ,包括Ｃ３Ｘ,Ｃ４Ｘ,Ｃ６７Ｘ等。ＴＭＳ３２０Ｃ３０是ＴＩ公司的一种浮点ＤＳＰ,我们用它进行了图像压缩软件的开发。基于我们的工作经验,在本文中评价了…     

3G手机芯片级体系结构的展望(下)

开放式多媒体应用平台（ＯＭＡＰ） 是专门为支持２．５Ｇ和 ３Ｇ应用需求而设计的应用处理器体系结构。此平 台的设计方案基于以下两个基本假设： １在 ２．ＳＧ和 ３Ｇ产品中，应用将主要面向各种媒体，为了满足其对性能和功率效率的要求，我们必须采用包含ＤＳＰ和 ＭＣＵ在内的多处理器平台。ＯＭＡＰ是专为优化多媒体应用性能而设计的，它可以提升任何支持语音、音频、图像或视频信号处理的应用的性 能。 ２应用环境是动态的，因此，您可以不断地将新的应用软件下载至 ＲＩＳＣ和 ＤＳＰ芯片 中。 图２显示了ＯＭＡＰ的结构框图。图中…     

多媒体数字信号处理器TMS320C80

多媒体数字信号处理器ＴＭＳ３２０Ｃ８０２０００８３上海技术物理研究所肖儿良卢子峰吴常泳１ＴＭＳ３２０Ｃ８０概述ＴＭＳ３２０系列数字信号处理器（ＤＳＰ）是美国著名半导体公司ＴＩ的产品，是单片机数字信号处理器的先驱。自１９８２年成功地推出第一代ＤＳＰ产品...     

可满足不同设计要求的混合式CPU／DSP处理器

众所周知，ＣＤ光盘机，蜂窝电话、磁盘驱动器、ＧＰＳ接收机和网络基础设施等都有赖于　数字信号处理器（ＤＳＰ），而其中的大多数产品同时需要一个独立的微处理器（或微控制器）。经济上的压力迫使厂家降低造价、尺寸和功耗，但遗憾的是大多数微处理器并不是理想的ＤＳＰ，而大多数ＤＳＰ则只是平庸的微处理器。标准的ＣＰＵ设计在ＦＩＲ滤波器、ＦＦＴ、卷积和其它一些任务上不如ＤＳＰ。反之，大多数ＤＳＰ在中断处理、决策树、位处理或逻辑操作方面不如标准ＣＰＵ。总之，这两个家族沿自己的道路成长并发展成为完全不同的编程工具。典…     

HP发布PA-RISC处理器未来之路

ＨＰ公司最新宣布推出其第三代的６４位ＰＡ－８５００处理器。这一处理器具有出色的性能与优异的扩展性，并且集成了容量为１．５ＭＢ的片内高速缓冲存储器。该处理器将主要应用于ＨＰ的企业级工作站与服务器产品之中。以此为契机，ＨＰ向外界公布了其高性能６４位ＰＡ－ＲＩＳＣ处理器的未来发展规划。这一发展规划支持ＨＰ继续为其企业客户提供出色的性能改进，同时能够确保ＰＡ－ＲＩＳＣ系列处理器在下一世纪中的领先地位。新的ＰＡ－８５００处理器尤其适用于需要对多项操作进行并发加速的应用场合，例如，数据密集型的Ｉｎｔｅｒｎｅ…     

A Retargetable Compilation Methodology for Embedded Digital Signal Processors Using a Machine-Dependent Code Optimization Library

We address the problem of code generation for embedded DSP systems. Such systems devote a limited quantity of silicon to program memory, so the embedded software must be sufficiently dense. Additionally, this software must be written so as to meet various high-performance constraints. Unfortunately, current compiler technology is unable to generate dense, high-performance code for DSPs, due to the fact that it does not provide adequate support for the specialized architectural features of DSPs via machine-dependent code optimizations. Thus, designers often program the embedded software in assembly, a very time-consuming task. In order to increase productivity, compilers must be developed that are capable of generating high-quality code for DSPs. The compilation process must also be made retargetable, so that a variety of DSPs may be efficiently evaluated for potential use in an embedded system. We present a retargetable compilation methodology that enables high-quality code to be generated for a wide range of DSPs. Previous work in retargetable DSP compilation has focused on complete automation, and this desire for automation has limited the number of machine-dependent optimizations that can be supported. In our efforts, we have given code quality higher priority over complete automation. We demonstrate how by using a library of machine-dependent optimization routines accessible via a programming interface, it is possible to support a wide range of machine-dependent optimizations, albeit at some cost to automation. Experimental results demonstrate the effectiveness of our methodology, which has been used to build good-quality compilers for three fixed-point DSPs. This revised version was published online in July 2006 with corrections to the Cover Date.     

单片可编程DSP及其在高速控制中的应用

数字信号处理器是一种面向信号处理和计算密集型任务的单片微机。本文以ＴＭＳ３２０系列ＤＳＰ为例，对ＤＳＰ和一般微控制器的性能进行了比较，讨论了单片ＤＳＰ用于高速实时控制的结构特点，最后给出了ＤＳＰ在计算机控制中的应用实例。     

Paged Absolute Addressing Mode Optimizations for Embedded Digital Signal Processors Using Post-pass Data-flow Analysis

We address the problem of code generation for embedded DSP systems. In such systems, it is typical for one or more digital signal processors (DSPs), program memory, and custom circuitry to be integrated onto a single IC. Consequently, the amount of silicon area that is dedicated to program memory is limited, so the embedded software must be sufficiently dense. Additionally, this software must be written so as to meet various high-performance constraints, which may include hard real-time constraints. Unfortunately, existing compiler technology is unable to generate dense, high-performance code for DSPs since it does not provide adequate support for the specialized architectural features of DSPs. These specialized features not only allow for the fast execution of common DSP operations, but they also allow for the generation of dense assembly code that specifies these operations. Thus, system designers often hand-program the embedded software in assembly, which is a very time-consuming task. In this paper, we focus on providing compiler support for one particular specialized architectural feature, namely the paged absolute addressing mode – this feature is found in two commercial DSPs, the Texas Instruments' TMS320C25 and TMS320C50 fixed-point DSPs; however, it may also be featured in application-specific processors (ASIPs). We present some machine-dependent code optimizations that improve code density by exploiting this architectural feature. Experimental results demonstrate that for a set of typical DSP benchmarks, some of our optimizations reduce overall code size and data memory consumption by an average of 5.0% and 16.0%, respectively. Our experimental vehicle throughout this research is the TMS320C25.     

Multimedia processors

This paper describes large-scale-integration programmable processors designed for multimedia processing such as real-time compression and decompression of audio and video as well as the generation of computer graphics. As the target of these processors is to handle audio and video in real time, the processing capability must be increased tenfold compared to that of conventional microprocessors, which were designed to handle mainly texts, figures, tables, and photographs. To clarify the advantages of a high-speed multimedia processing capability, we define these chips as multimedia processors. General-purpose microprocessors for workstations and personal computers (PCs) use special built-in hardware for multimedia processing, so the multimedia processors described include these modified general-purpose microprocessors. After reviewing the history of programmable processors, we classify multimedia processors into five categories depending on their basic architecture. The categories are reduced instruction set computer (RISC) microprocessors for workstations, complex instruction set computer microprocessors for PCs, embedded RISCs, low-power digital signal processors (DSPs), which are mainly used for mobile communications devices, and media processors that support PCs for multimedia applications. These five classes are then grouped into two: microprocessors with a multimedia instruction set and highly parallel DSPs. An architectural comparison between these two groups on the basis of Moving Picture Experts Group decoding applications is made, and the advantages and disadvantages of each class are clarified. Future processors, including “system on a chip,” and their applications are also discussed     

现代通信中的DSP：面临的挑战及未来发展趋势

本文介绍了ＤＳＰ（数字信号处理器）在通信领域的应用现状和新动向，同时指出了ＤＳＰ为适应现代通信技术发展的需要所面临的挑战，最后对新一代ＤＳＰ的特点和未来趋势作了总结归纳。     

高性能16位定点DSP的Datapath设计及FPGA验证

随着数字化产品的不断普及，以高速、实时为特点的数字信号处理器(Digital Signal Processors，DSPs)越来越多地应用到国防和消费等各个领域。文章介绍了一款嵌入式高性能16位定点DSPs的Datapath(数据通路)设计，以Datapath中各功能单元为线索，叙述其电路实现及FPGA验证。     

基于TMS320C6000 DSP的FIFO—网络数据传输

随着网络技术的飞速发展,越来越多的嵌入式信号采集系统通过以太网来传输数据.而FIFO作为高速信号处理系统中常用的数据通道,也大量的用于嵌入式系统中.本文实现了一个基于TMS320C6000系列DSP的嵌入式信号处理--网络传输方案,在采集A/D数据并进行高速信号处理的同时,还通过FIFO以及DSP的网络接口,实现了高速的嵌入式数据通路,最终将结果传入计算机进行保存、显示和处理.文中给出了硬件框图和软件流程.同时针对在系统开发过程中遇到的一些问题,进行了较详细的分析讨论,提出了解决办法.     

计算高度密集型应用在异构多核DSP上的运行方法研究

研究实现了计算高度密集型应用在异构多核DSP上运行的方法.即利用存储在RISC核外设总线上的FLASH中的应用程序,通过异构多核DSP目标板加电,自动加载到RISC核RAM执行,该应用程序将计算高度密集型应用的DSP程序加载到DSPs核上,并利用RISC核向DSPs核点火执行.主要介绍了异构多核DSP中的RISC核和DSP核的复位、启动方法,DSP核的多种冗余降级工作模式,详细分析了RISC核控制DSP核的原理及操作方法.提出的运行方法完整有效,为相关的研究人员打下了良好的基础.     

On Enhancing SIMD-controlled DSPs for Performing Recursive Filtering

Many digital signal processors (DSPs) and also microprocessors are employing the single-instruction multiple-data (SIMD) paradigm for controlling their data paths. Although the SIMD paradigm can provide high computational power and efficiency, not all applications can profit from this feature. One important application, particularly in audio processing, of DSPs are recursive (IIR) filters. Due to their data-dependencies they can not exploit the capabilities of SIMD-controlled DSPs as non-recursive (FIR) filters can. This paper shows, how the SIMD control scheme can be enhanced to accommodate recursive filters without introducing much hardware overhead. Three methods for calculating recursive filters on SIMD-controlled DSPs and their requirements for control and data transfer are presented. They can be applied to direct-form as well as cascade-form realizations. The performance and hardware requirements of these methods are evaluated to determine the most efficient solution in terms of the AT-product. An erratum to this article is available at .     

基于TMS320C6x.系列DSP/BIOS平台的实时电视跟踪系统设计

为解决实时目标识别和跟踪的硬件平台设计问题,本文以两片高性能DSP为核心处理器,设计了基于双DSP的实时图像处理系统.常见的目标跟踪系统算法包括重心跟踪法、相关跟踪法和边缘跟踪,在实时跟踪过程中,根据需要进行各个算法间的切换,为了提高实时电视跟踪系统设计的开发效率及实时跟踪性能,可以在双DSP平台上,在利用TMS320C6x内部自带的实时操作系统DSP/BIOS以及API函数,编写高效的多任务跟踪程序,缩短开发周期.试验证明,基于DSP/BIOS的实时跟踪系统设计可以很好的达到设计要求,不但增强了程序的可维护性,而且程序模块化,可移植性好.