MALU—单指令周期可实现乘法的ALU

ＭＡＬＵ—单指令周期可实现乘法的ＡＬＵ李永明，陈弘毅，于政，褚彤，边昆（清华大学微电子研究所，北京１０００８４）一、引言算术逻辑单元（ＡＬＵ）是微处理器（ＭＰＵ）和微型控制器（ＭＣＵ）的关键部件．常规的ＡＬＵ只含有加法，利用多次相加及移位操作来实现乘...     

对GAL器件输出逻辑宏单元使用的探讨

探讨了通用阵列逻辑（ＧＡＬ）器件输出逻辑宏单元（ＯＬＭＣ）的配置和工作原理，还探讨了在编写源件时可能出现的错误及其原因，进而给出了输出逻辑宏单元的使用和管脚设定的规则。     

Lattice pLSI系列器件与AMD MACH系列器件的比较

本文对Ｌａｔｔｉｃｅ公司ｐＬＳＩ／ｉｓｐＬＳＩ １０００系列高密度可编程逻辑器件和ＡＭＤ公司ＭＡＣＨ１００／２００系列ＰＡＬ器件作了简要的比较。Ｌａｔｔｉｃｅ公司和ＡＭＤ公司都是可编程逻辑器件的重要生产厂家，本文对Ｌａｔｔｉｃｅ的代表产品ｐＬＳＩ／ｉｓｐＬＳＩ１０００系列高密度可编程逻辑器件和ＡＭＤ公司的代表产品ＭＡＣＨ１００／２００系列，ＰＡＬ在以下几个方面进行了比较：（１）逻辑块的尺寸；（２）     

一种用GAL实现的m序列发生器

通用可重编程逻辑阵列（ＧＡＬ）是１９８５年问世的新器件，它具有可靠性高、保密性强、可电擦写、可重复编程以及输出逻辑结构可组态等特点，它可替代ＴＴＬ／７４ＨＣ组合逻辑电路、低密度门阵列及其它可编程逻辑芯片。通常一只ＧＡＬ芯片可替代４￣１２个中小规模集成芯片，这可使系统体积减小，成本降低，同时提高了系统的可靠性与稳定性。本文将介绍ＧＡＬ芯片在扩频通信中的应用，并详细介绍用一片ＧＡＬ１６Ｖ８芯片实现的七     

基于HDL的PLA辅助分析

本文提出了一种用硬件描述语言（ＨＤＬ）来辅助分析ＰＬＡ的方法，并详细地介绍了可编程逻辑阵列（ＰＬＡ）的模块描述，阵列数据获取方法及模拟和测试语言（ＳＴＬ）激励文件的生成过程，最后，本文给出了一个较完整的自动分析程序流程图。     

可编程的系统芯片FPSLIC

美国ＡＴＭＥＬ公司最近推出首创的可编程的系统芯片ＦＰＳＬＩＣ,此种ＦＰＳＬＩＣ家族系列被命名为ＡＴ９４Ｋ××系列。 作为现场可编程系统级ＩＣ电路,ＦＰＳＬＩＣ电路集成了高性能的用于数据路径逻辑的ＡＴ４０Ｋ的现场可编程门阵列（ＦＰＧＡ）,且每个现场可编程门阵列都带有４～１８ｋ ＡＴ４０Ｋ的静态记忆存储器（ＳＲＡＭ）;１个高性能的用于控制逻辑的带有硬件乘法加速器的３０＋ＭＩＰＳ的ＡＶＲ牌的精简指令集计算机（ＲＩＳＣ）;１个３２ｋＢ的可选结构静态记忆存储器（ＳＲＡＭ）;２个外部用户端口,１个１６位和２个…     

ADSL调制／解调中FFT设计及实现

阐述了ＡＤＳＬ（非对称数字用户线）的调制／解调技术，并给出一种用可擦可编程逻辑器件来实现其中ＦＦＴ（快速傅立叶变换）的具体方案。     

FLEX8000器件在彩灯控制系统中的应用

文章介绍了在节日彩灯课题中应用Ａｌｔｅｒａ公司的可编程逻辑器件（ＦＬＥＸ８０００系列）进行电子自动化设计的过程。     

可编程阵列逻辑器件在通信系统中的应用

近年来,可编程逻辑器件（ＰＬＤ）已广泛应用于计算机系统、数据处理、接口技术和工业控制等领域中,文中阐述了可编程阵列逻辑（ＰＡＬ）器件在差分四相多相键控（ＤＱＰＳＫ）发送端中的应用,结果表明,与中小规模集成电路设计方法相比,彩可阵列逻辑器件的设计方法不仅体积小、功耗低、可靠性高,而且安装、调试过程更为简便。     

No．7信令中继线无法删除的处理

Ｎｏ．７信令中继线无法删除的处理陈雅聪田波块的逻辑地址（ＬＣＥ）即第二组数据中２４６０，２５００，１６２０，１７４０，１８Ｃ０所对应的物理地址（ＮＡ）。〉：ＣＥＩＤＳＬ，２４６０→ＮＡ＝Ｈ８００２，对应ＴＣＥＳＥＱＮＢＲ＝１１〉：ＣＥＩＤＳＬ，２５...     

基于不相交乘积项的逻辑探测和拆分算法

 针对以往逻辑探测算法存在的不足,提出了一种基于不相交乘积项的逻辑探测和拆分算法.该算法通过将逻辑函数的乘积项转化为不相交乘积项,并结合不相交乘积项之间海明距关系将不相交乘积项拆分成互不相交的二部分,使之分别适合RM逻辑综合和布尔逻辑综合.通过对拆分结果分析,本文进一步提出了一种新的逻辑探测方法.实验结果表明,本文的判别结果能对电路综合过程中的逻辑选择提供一个良好的指导作用.     

混合RM-DRM逻辑及其在可逆电路综合中的应用

为获得布尔函数的紧凑逻辑表示,进而改善综合所得电路的质量,提出一种混合Reed-Muller和对偶Reed-Muller(RM-DRM)逻辑模型。基于海明距离对立方体集合进行划分来构建函数的混合RM-DRM逻辑表示,并利用对偶原理借助EXORCISM-4工具对混合RM-DRM逻辑进行化简。最后将混合RM-DRM逻辑作为结构表示模型应用于可逆电路综合。实验结果表明,与采用RM逻辑作为表示模型相比,混合RM-DRM逻辑模型的采用可以降低某些函数综合所得可逆电路的量子成本,并且能够降低RevLib库中的134个函数综合所得可逆电路的平均量子成本。     

Efficient reversible NOR gates and their mapping in optical computing domain

Reversible logic is a computing paradigm in which there is a one to one mapping between the input and the output vectors. Reversible logic gates are implemented in an optical domain as it provides high speed and low energy computations. In the existing literature there are two types of optical mapping of reversible logic gates: (i) based on a semiconductor optical amplifier (SOA) using a Mach–Zehnder interferometer (MZI) switch; (ii) based on linear optical quantum computation (LOQC) using linear optical quantum logic gates. In reversible computing, the NAND logic based reversible gates and design methodologies based on them are widely popular. The NOR logic based reversible gates and design methodologies based on them are still unexplored. In this work, we propose two NOR logic based n-input and n-output reversible gates one of which can be efficiently mapped in optical computing using the Mach–Zehnder interferometer (MZI) while the other one can be mapped efficiently in optical computing using the linear optical quantum gates. The proposed reversible NOR gates work as a corresponding NOR counterpart of NAND logic based Toffoli gates. The proposed optical reversible NOR logic gates can implement the reversible boolean logic functions with a reduced number of linear optical quantum logic gates or reduced optical cost and propagation delay compared to their implementation using existing optical reversible NAND gates. It is illustrated that an optical reversible gate library having both optical Toffoli gate and the proposed optical reversible NOR gate is superior compared to the library containing only the optical Toffoli gate: (i) in terms of number of linear optical quantum gates when implemented using linear optical quantum computing (LOQC), (ii) in terms of optical cost and delay when implemented using the Mach–Zehnder interferometer.     

Coordinate logic filters and their applications in image processing and pattern recognition

In this paper we present a number of image processing applications using coordinate logic filters, which execute coordinate logic operations among the pixels of the image. These filters are very efficient in various 1D, 2D, or higher-dimensional digital signal processing applications, such as noise removal, magnification, opening, closing, skeletonization, and coding, as well as in edge detection, feature extraction, and fractal modeling. In this paper we present some typical image processing applications using coordinate logic filters. The key issue in the coordinate logic analysis of images is the method of fast successive filtering and managing of the residues. The desired processing is achieved by executing only direct logic operations among the pixels of the given image. Coordinate logic filters can be easily and quickly implemented using logic circuits or cellular automata; this is their primary advantage.     

Generation and evaluation of current and logic tests for switch-level sequential circuits

This article presents an approach to developing high quality tests for switch-level circuits using both current and logic test generation algorithms. Faults that are aborted or undetectable by logic tests may be detected by current tests, or vice versa. An efficient switch level test generation algorithm for generating current and logic tests is introduced. Clear definitions for analyzing the effectiveness of the joint test generation approach are derived. Experimental results are presented for demonstrating high coverage of stuck-at, stuck-on, and stuck-open faults for switch level circuits when both current and logic tests are used.This is expanded version of the work originally presented at the 1991 International Test Conference.     

A Wired-AND Current-Mode Logic Circuit Technique in CMOS for Low-Voltage, High-Speed and Mixed-Signal VLSIC

A wired-AND current-mode logic (WCML) circuit techniquein CMOS technology for low-voltage and high-speed VLSI circuitsis proposed, and a WCML cell library is developed using standard0.8 micron CMOS process. The proposed WCML technique appliesthe analog circuit design methodologies to the digital circuitdesign. The input and output logic signals are represented bycurrent quantities. The supply current of the logic circuitis adjustable for the required logic speed and the switchingnoise level. The noise is reduced on the power supply lines andin the substrate by the current-steering technique and by thesmooth swing of the reduced node potentials. Precise analogcircuits and fast digital circuits can be integrated on the samesilicon substrate by using the low noise property of the WCML.It is shown by the simulations that at low supply voltages, theWCML is faster and generates less switching noise when comparedto the static-CMOS logic. At high speeds, the power dissipationof the WCML is less than that of the static-CMOS logic.     

新型电光逻辑门的设计及计算机图形光谱

光逻辑门是未来全光网络中光信息处理的核心元件,它可以实现高速光包交换,全光地址识别,数据编码,奇偶校验,信号再生等功能。采用微环谐振器设计了一种新型的电光逻辑门,结构通过三个非对称微环组成,分析耦合区的传输矩阵方程得出加载电压信号的变化能够实现微环折射率的变化,利用光强的逻辑开关特性可以实现光门逻辑。计算机仿真验证了工作波长1 600 nm时,实现的高电平50.7 V定义为逻辑1,低电平0 V定义为逻辑0,通过光强变化得出了6位逻辑运算;整个系统的响应时间理论上得到了1.8 ps,运算速率可达近200 Gbit/s。逻辑的双稳态分析中得出:微环发生最大谐振值时对应的控制波长等于微环未发生形变前的谐振波长和偏移量之和;调制可以通过微环谐振波长实现控制。这一研究对于未来全光通信的实现具有一定的意义。     

Probabilistic analysis of dynamic and temporal fault trees using accurate stochastic logic gates

This paper presents accurate models for the analysis of fault trees based on stochastic logic. To produce the models, probabilistic analysis of static, dynamic and temporal gates is carried out and the probability models are converted to their equivalent stochastic logic gates. A hardware template is also designed for each stochastic logic gate. In the proposed method, users provide fault rates of basic events and immediately evaluate system reliability. Experimental results show that the proposed method is more accurate than previous methods using the proposed stochastic logic gates for dynamic and temporal fault trees. The formula was validated using the Markov model for exponential failure distribution events. The proposed model is applicable for both exponential and non-exponential distributions.     

A modeling and analysis methodology for modular logic controllersof machining systems using Petri net formalism

Logic controllers for machining systems typically have three control modes: auto, hand and manual. In this paper, a unified formal representation of logic controllers with three control modes is provided using Petri nets (PNs). A modular logic controller structure is introduced and formalized for high-volume transfer lines. The modular logic controller consists of one control module for the mode decision and other control modules for station logic controllers. Each station control module is represented by connecting together operation modules, which are designed with respect to the fault recovery processes of operations; their connection algorithm is also provided. In our formal representation, each control module is represented by a live, safe and reversible PN. A condition for the modular logic controller to generate a correct control logic is provided: the operation causality condition. Using the modular structure of a logic controller, the control logic can be easily reconfigured and automatic code generation is possible     

网络支付协议的形式化安全需求及验证逻辑

从整个网络支付协议的安全角度出发，提出网络支付协议的多层安全需求模型，包括以认证和密钥分配为基础的基层需求、网络支付协议固有的中层需求(包括保密性、原子性、公平性、完整性、匿名性、不可否认性、可追究性等)、以及面向具体应用的高层需求。基于一阶逻辑和时序逻辑，提出一种适合描述网络支付协议的形式化安全需求的逻辑，描述了该逻辑的语法结构和推理规则，并用该安全需求逻辑对网络支付协议的多层安全需求进行了形式化描述。最后，以SET协议为例进行需求验证。