A learning approach of wafer temperature control in a rapid thermalprocessing system

This paper presents a learning approach for wafer temperature control in a rapid thermal processing system (RTP). RTP is very important for semiconductor processing system and requires an accurate trajectory following. Numerous studies have addressed this problem and most research on this problem requires exact knowledge of the system dynamics. The various approaches do not guarantee the desired performance in practical applications when there exist some modeling errors between the model and the actual system. In this paper, iterative learning control scheme is applied to RTP without exact information on the dynamics. The learning gain of the iterative learning law is estimated by neural networks instead of a mathematical model. In addition, the control information obtained by the iterative learning controller (ILC) is accumulated in the feedforward neuro controller (FNC) for generalization to various reference profiles. Through numerical simulations, it is demonstrated that the proposed method can achieve an accurate output tracking even without an exact RTP model. The output errors decrease rapidly through iterations when using the learning gain estimated and the FNC yields a reduced initial error, and so requires small iterations     

Control of MMST RTP: repeatability, uniformity, and integration forflexible manufacturing [ICs]

A real-time multivariable strategy is used to control the uniformity and repeatability of wafer temperature in rapid thermal processing (RTP) semiconductor device manufacturing equipment. This strategy is based on a physical model of the process where the model parameters are estimated using an experimental design procedure. The internal model control (IMC) law design methodology is used to automatically compute the lamp powers to a multizone array of concentric heating zones to achieve wafer temperature uniformity. Control actions are made in response to real-time feedback information provided by temperature sensing, via pyrometry, at multiple points across the wafer. Several modules, including model-scheduling and antiovershoot, are coordinated with IMC to achieve temperature control specifications. The control strategy, originally developed for prototype equipment at Stanford University, is analyzed via the customization, integration, and performance on eight RTP reactors at Texas Instruments conducting thirteen different thermal fabrication operations of two sub-half-micron CMOS process technologies used in the the Microelectronics Manufacturing Science and Technology (MMST) program     

A novel technique for RTP annealing of compound semiconductors

We introduce for the first time a novel rapid thermal processing (RTP) unit called Zapper™, which has recently been developed by MHI Inc. and the University of Florida, for high temperature thermal processing of semiconductors. This Zapper™ unit is capable of reaching much highertemperatures (>1500°C) than conventional tungsten–halogen lamp RTP equipment and achievinghigh ramp-up and ramp-down rates. We have conducted implant activation annealing studies ofSi⁺-implanted GaN thin films (with and without an AlN encapsulation layer) using the Zapper™ unit at temperatures up to 1500°C. The electrical property measurements of such annealed samples have led to the conclusion that high annealing temperatures and AlN encapsulation are needed for the optimum activation efficiency of Si⁺ implants in GaN. It has clearly been demonstrated that the Zapper™ unit has tremendous potential for RTP annealing of semiconductor materials, especially for wide band-gap (WBG) compound semiconductors that require very high processing temperatures.     

Polymer Optical Interconnects—A Scalable Large-Area Panel Processing Approach

A flexible approach to producing optical interconnects on 609.6$ast ,$609.6 mm large-area panels is demonstrated. Stepwise projection patterning from 101.6$ast ,$101.6 mm masks has generated optical waveguide patterns over the whole panel using large-area projection lithography equipment. The waveguide routing design allows optical waveguides on different 101.6$ast ,$101.6 mm tiles to be interconnected. Four different waveguide connecting geometries in the border region between tiles have been fabricated and tested. Multimode waveguides from inorganic-organic hybrid polymers (ORMOCER) (cross section:$le hbox 50~muhbox mast hbox 10~muhbox m$) with refractive index step between core and cladding$Delta n=hbox 0.01$were produced. The index step was adjusted by mixing two diffrent ORMOCER systems. The materials show good adhesion to numerous substrates, such as glass and silicon. Application concepts such as flexible manufacturing of optoelectrical hybrid backplanes with two-dimensional interconnect, a three-dimensional optical interconnect with optical vias, and a hybrid backplane with the optical interconnect in a strip-format on a separate plane right above the electrical plane are proposed. Promising new technologies are presented along with preliminary demonstrativ viability.     

Fast Simulation of steady-state temperature distributions in electronic components using multidimensional model reduction

In this paper, a model reduction technique is applied to the thermal modeling of electronic components and devices with complex geometries. The reduced-order model is capable of predicting a complete detailed three-dimensional temperature distribution in the original model. The small size and the simplicity of the reduced model allows for the very quick simulation of the device under a wide range of input parameters, such as different boundary conditions and power distributions. Use of the reduced-order model in a thermal design cycle can have a significant effect on both prediction accuracy and simulation efficiency. In the paper, the usefulness of this technique is demonstrated through examples from different electronic devices and packages. Accuracy of the reduced-order model is validated by comparison with the solution to a detailed numerical model.     

Impact of Design on High-Frequency Performance of Advanced MIM Capacitors Using Si $_{3}$N $_{4}$ Dielectric Layers

High-frequency characterizations of ultra thin 32 nm PECVD Si$_{3}$N $_{4}$ dielectric in an advanced metal–insulator–metal (MIM) capacitors are presented, with focus on the impact of design on the performance of MIM capacitors. Frequency dependent capacitance has been extracted over a wide range of frequency bandwidth. An equivalent model circuit of capacitors including four parameters was developed to explain this behavior. The results have been compared with the values obtained from a 3-D electromagnetic modeling. A specific chart has been introduced to predict the electrical performance of new MIM capacitor designs.      

$hbox{TiN/ZrO}_{2}$/Ti/Al Metal–Insulator–Metal Capacitors With Subnanometer CET Using ALD-Deposited $hbox{ZrO}_{2}$ for DRAM Applications

We provide the first report of the structural and electrical properties of $hbox{TiN/ZrO}_{2}$/Ti/Al metal–insulator–metal capacitor structures, where the $hbox{ZrO}_{2}$ thin film (7–8 nm) is deposited by ALD using the new zirconium precursor ZrD-04, also known as Bis(methylcyclopentadienyl) methoxymethyl. Measured capacitance–voltage ($C$– $V$) and current–voltage ( $I$–$V$) characteristics are reported for premetallization rapid thermal annealing (RTP) in $hbox{N}_{2}$ for 60 s at 400 $^{circ}hbox{C}$, 500 $^{circ}hbox{C}$, or 600 $^{ circ}hbox{C}$. For the RTP at 400 $^{circ}hbox{C}$ , we find very low leakage current densities on the order of nanoamperes per square centimeter at a gate voltage of 1 V and low capacitance equivalent thickness values of $sim$ 0.9 nm at a gate voltage of 0 V. The dielectric constant of $ hbox{ZrO}_{2}$ is 31 $pm$ 2 after RTP treatment at 400 $^{circ}hbox{C}$.      

430-V 12.4-$hboxmOmegacdot hboxcm^2$Normally off 4H-SiC Lateral JFET

This letter reports the experimental demonstration of the first 4H-SiC normally off high-voltage lateral junction field-effect transistor. The design and fabrication of such a device have been investigated. The fabricated device has a vertical channel length of 1.8$muhboxm$created by tilted aluminum implantation on the sidewalls of deep trenches and a lateral drift-region length of 5$muhboxm$. Normally off operation$(V_ GS=hbox0 V)$with a blocking voltage$V_ br$of 430 V has been achieved with a specific on-resistance$R_ onhbox- sp$of 12.4$hboxmOmega cdot hboxcm^2$, which is the lowest specific on-resistance for 4H-SiC lateral power switches reported to date, resulting in a$V_ br^2/R_ onhbox- sp$value of 15$hboxMW/cm^2$. This is among the best$V_ br^2/R_ onhbox- sp$figure-of-merit reported to date for 4H-SiC lateral high-voltage devices.     

Experimental application of a quadratic optimal iterative learning control method for control of wafer temperature uniformity in rapid thermal processing

A quadratic-optimal iterative learning control (ILC) method has been designed and implemented on an experimental rapid thermal processing system used for fabricating 8-in silicon wafers. The controller was designed to control the wafer temperatures at three separate locations by manipulating the power inputs to three groups of tungsten-halogen lamps. The controller design was done based on a time-varying linear state-space model, which was identified using experimental input-output data obtained at two different temperatures. When initialized with the input profiles produced by multiloop PI controllers, the ILC controller was seen to be capable of improving the control performance significantly with repeating runs. In a series of experiments with wafers on which thermocouples are glued, the ILC controller, over the course of ten runs, gradually steered the wafer temperatures very close to the respective reference trajectories despite significant disturbances and model errors.     

Activation annealing of Si-implanted GaN up to 1500°C using a novel RTP technique

A novel rapid thermal processing (RTP) unit called Zapper™ has recently been developed by MHI Inc. and the University of Florida for high temperature thermal processing of semiconductors. This Zapper™ unit is capable of reaching much higher temperatures (>1500°C) than conventional tungsten-halogen lamp RTP equipment and achieving high ramp-up and ramp-down rates. Implant activation annealing studies of Si⁺-implanted GaN thin films (with and without an AlN encapsulation layer) have been conducted using the Zapper™ unit at temperatures up to 1500°C. The measurements of electrical properties of such annealed samples have led to the conclusion that high annealing temperatures and AlN encapsulation are needed for the optimum activation efficiency of Si⁺ implants in GaN. It has clearly been demonstrated that the Zapper™ unit has tremendous potential for RTP annealing of semiconductor materials, especially for wide bandgap compound semiconductors that require very high processing temperatures.     

Reduced-order modeling for hyperthermia control

This paper analyzes the feasibility of using reduced-order modeling techniques in the design of multiple-input, multiple-output (MIMO) hyperthermia temperature controllers. State space thermal models are created based upon a finite difference expansion of the bioheat transfer equation model of a scanned focused ultrasound system (SFUS). These thermal state space models are reduced using the balanced realization technique, and an order reduction criterion is tabulated. Results show that a drastic reduction in model dimension can be achieved using the balanced realization. The reduced-order model is then used to design a reduced-order optimal servomechanism controller for a two-scan input, two thermocouple output tissue model. In addition, a full-order optimal servomechanism controller is designed for comparison and validation purposes. These two controllers are applied to a variety of perturbed tissue thermal models to test the robust nature of the reduced-order controller. A comparison of the two controllers validates the use of open-loop balanced reduced-order models in the design of MIMO hyperthermia controllers.     

Modeling and Design for a Novel Adaptive Voltage Positioning (AVP) Scheme for Multiphase VRMs

Adaptive voltage positioning (AVP) has been used in multiphase voltage regulator module (VRM) applications. A novel scheme, called AVP $+$, is analyzed in this paper. Small signal model is used to look into the control performance issues such as output impedance and stability. The model has been verified in the experiments and simulations. Compared to a conventional AVP schemes, the present scheme provides better stability margin and output-impedance performance. This is especially true for the prevailing trend of using ceramic output capacitors and high switching frequency. The focus of the present paper is the small-signal modeling for control loop design using the AVP$+$ scheme which was never analyzed before. And the comparisons were made between AVP$+$ and AVP$-$ on the stability and output impedance performance.      

On the Design of Undersampling Continuous-Time Bandpass Delta–Sigma Modulators for Gigahertz Frequency A/D Conversion

This paper describes issues and tradeoffs related to the design of undersampling delta–sigma modulators $(DeltaSigma {rm Ms})$ for wireless receivers. It proposes a new bandpass undersampling $DeltaSigma {rm M}$ architecture dedicated to multigigahertz frequencies. This paper is based on up-sampling in the feedback path to remove the analog mixer usually found in the modulator. Design equations are discussed for an optimum operating point when the input signal is at 1.8 GHz. The related design model can be applied to many communication standards. The underlying proposed architecture can receive high-frequency carriers modulated with signals of bandwidth as large as 5 MHz. In the proposed design, it converts the signal into digital data with a spurious-free dynamic range of 46 dB at a sampling frequency of 810.1 MHz. Design simulation, characterization, and implementation of the proposed modulator are done using a 0.13- ${rm mu}hbox{m}$ CMOS technology.      

VoIP设备设计中RTP协议的实现

详细介绍了RTP/RTCP协议(Real-time Transport Protocol & Real-time Transport Control Protocol)的原理及帧结构,重点介绍了时间戳的使用方法和注意事项,提出了基于RTP/RTCP协议的VoIP话音传输技术解决方案,设计了基于多JitterBuffer机制的RTP/RTCP协议栈,配套设计了协议栈与SIP协议和DSP驱动的接口软件,实现了实时的多通道会议模式的VOIP话音通信功能,现已形成成熟的技术,产品也已量产。实践证明,本设计具有一定的独特性,性能上也优于其他同类产品。     

Thin-gate SiO2 films formed by in situ multiple rapidthermal processing

A reliable method of forming very thin SiO₂ films (<10 nm) has been developed by rapid thermal processing (RTP) in which in situ multiple RTP sequences have been employed. Sub-10-nm-thick SiO₂ films formed by single-step RTP oxidation (RTO) are superior to conventional furnace-grown SiO₂ on the SiO₂ /Si interface characteristics, dielectric strength, and time-dependent dielectric-breakdown (TDDB) characteristics. It has been confirmed that the reliability of SiO₂ film can be improved by pre-oxidation RTP cleaning (RTC) operated at 700-900°C for 20-60 s in a 1%HCl/Ar or H₂ ambient. The authors discuss the dielectric reliability of the SiO₂ films formed by single-step RTO in comparison with conventional furnace-grown SiO₂ films. The effects and optimum conditions of RTC prior to RTO on the TDDB characteristics are demonstrated. The dielectric properties of nitrided SiO₂ films formed via the N₂O-oxynitridation process are described     

Temperature control in a rapid thermal processor

Temperature control problems in a rapid thermal processor (RTP) are addressed by using a conventional proportional-integral-derivative (PID) controller and an autoadaptive algorithm. So far, temperature control in most RTP systems has usually been accomplished by using PID controllers. In RTP systems using only classical control schemes, the setting of the control module is a long and complicated task, which often provides optimum results within a limited temperature range. It is shown that adaptive control is less affected by process dynamics     

Enhancement-Mode$hboxSi_3hboxN_4hbox/AlGaN/GaN$MISHFETs

Enhancement-mode$hboxSi_3hboxN_4/hboxAlGaN/GaN$metal–insulator–semiconductor HFETs (MISHFETs) with a 1-$muhboxm$gate footprint are demonstrated by combining$hboxCF_4$plasma treatment technique and a two-step$hboxSi_3hboxN_4$deposition process. The threshold voltage has been shifted from$-$4 [for depletion-mode HFET] to 2 V using the techniques. A 15-nm$hboxSi_3hboxN_4$layer is inserted under the metal gate to provide additional isolation between the gate Schottky contact and AlGaN surface, which can lead to reduced gate leakage current and higher gate turn-on voltage. The two-step$hboxSi_3hboxN_4$deposition process is developed to reduce the gate coupling capacitances in the source and drain access region, while assuring the plasma-treated gate region being fully covered by the gate electrode. The forward turn-on gate bias of the MISHFETs is as large as 7 V, at which a maximum current density of 420 mA/mm is obtained. The small-signal RF measurements show that the current gain cutoff frequency$(f_T)$and power gain cutoff frequency$(f_max)$are 13.3 and 23.3 GHz, respectively.     

An effective IPv4–IPv6 translation mechanism for SIP applications in next generation networks

In a next generation network, the IPv6‐enabled IP multimedia subsystem (IMS) network may connect to an IPv4 network. When an IPv4/IPv6 dual‐stack user equipment (UE) initiates a call by sending an IPv6 SIP INVITE message to an IPv4‐only user agent (UA), the call cannot be established correctly. To resolve this problem, the IMS‐application layer gateway solution, the redirect solution, and the interactive connectivity establishment solution have been proposed. In this paper, we propose an effective solution where only the IPv6 INVITE message is translated into an IPv4 INVITE message. Upon receipt of the IPv4 200 OK message replied from the IPv4‐only UA, the dual‐stack UE learns that the correspondent UA supports IPv4‐only and utilizes IPv4 instead of IPv6 to send the subsequent SIP messages and real‐time transport protocol (RTP) packets. The proposed solution is compared with the existing solutions in terms of network node modification, call setup complexity, and RTP transmission latency. Our study indicates that the proposed solution outperforms the other three solutions in the call setup and the RTP transmission. Copyright © 2009 John Wiley & Sons, Ltd.     

An Experimental and Numerical Investigation Into Multilayer Probe Card Layout Design

This paper conducts experimental and numerical investigations into the microforce probing technique used to test the functionality of IC devices. The study commences by considering the case of a single tungsten needle probe and examines the relationship between the contact force and the scrub mark size on aluminum pads at various levels of overdrive and shooting angle. Subsequently, a three-dimensional computational model is developed to facilitate the design of an optimum multilayer needle card layout. The simulation results obtained for the profile and size of the scrub marks on the upper surface of the aluminum pads of an IC device are found to be in good agreement with the experimental observations. The validated model is then applied to analyze the effects of the tip length and beam length on the scrub mark profile and the stress distribution contours within the needle during a wafer level test. The results predicted by the finite-element model (FEM) for the scrub mark length under various beam lengths are used to specify a suitable design for a multilayer needle layout. Taking the case of DDR2 SDRAM of an aluminum pad of dimensions 70$mu$m$,times,$70$mu$m (length by width), the numerical results enable appropriate values to be assigned to the shooting angles, beam lengths, and tip lengths of the individual needles within a four-layer probe card.     

Model identification in rapid thermal processing systems

Of the various techniques for controlling the temperature in rapid thermal processing (RTP), model-based control has the greatest potential for attaining the best performance, when the model is accurate. Some system identification methods are introduced to help obtain more accurate models from measured input-output data. For the first identification method, techniques for estimating the parameters (time constant and gain) of a particular physics-based model are presented. For the other, it is shown how to use the input-output measurements to obtain a black-box (autoregressive exogenous) model of the RTP system, which turns out to have better predictive capability. For each problem, the theoretical derivation of the identification technique and assumptions on which it is based are summarized, and experimental results based on data collected from an RTP system are described. Studying the DC response using the identified model led to a reconfiguration of the chamber geometry of the existing RTP system to more effectively distribute the light energy from the lamps