A simple model for threshold voltage of surrounding-gate MOSFET's

We propose a threshold voltage model for surrounding-gate MOSFETs. The model treats the ends and the double-gate regions of the channel as separate devices operating in parallel. The threshold voltage for the full device is obtained as the perimeter-weighted sum of the threshold voltages of the two parts enabling simple analytic threshold models to be used. Short channel effects and drain-induced barrier lowering are also modeled in this manner     

Reduction of threshold voltage sensitivity in SOI MOSFET's

The threshold voltage sensitivity, of fully depleted SOI MOSFET's to variations in SOI silicon film thickness was examined through both simulation and device experiments. The concept of designing the channel V_th implant to achieve a constant dose within the film, rather than a constant doping concentration, was studied for a given range of film thicknesses. Minimizing the variation in retained dose reduced the threshold voltage sensitivity to film thickness for the range of t_si examined. One-dimensional process simulations were performed to determine the optimal channel implant condition that would reduce the variation in retained dose using realistic process parameters for both NMOS and PMOS device processes. SOI NMOS transistors were fabricated. The experimental results confirmed the simulation findings and achieved a reduced threshold voltage sensitivity     

Calculation of threshold voltage in nonuniformly doped MOSFET's

A simple algorithm is presented that is based on a semi-empirical modification of a closed form expression for the inversion charge, to allow the calculation of the so-called extrapolated threshold voltage versus source-substrate bias in nonuniformly doped MOSFET's. This algorithm is suitable for incorporation into process simulation computer programs like SUPREM. It is demonstrated, by comparison to exact calculations and to measurements, that the algorithm gives accurate values of extrapolated threshold voltage even for cases where junctions are present in the MOSFET substrate under the gate.     

A new analysis of the threshold voltage for non-uniform ion-implant MOSFET's

An analysis for the threshold voltage of MOSFET's with a Gaussian ion-implant profile is presented. Two parameters xpand xb, which characterize the peak location and the spread of a Gaussian profile, can be arbitrarily adjusted such that even a deeply ion-implanted device can be simulated. The theory predicts a good agreement with available experimental data collected from transistors with a wide range of process parameters and also confirms the so-called anomalous short-channel effect recently observed by Nishida and Onodera [3].     

A two-dimensional analytical threshold voltage model for MOSFET's with arbitrarily doped substrates

A threshold voltage model is presented which is valid for short- and long-channel MOSFET's with a nonuniform substrate doping profile. The model is based upon an approximate two-dimensional analytical solution of Poisson's equation for a MOSFET of arbitrary substrate doping profile which takes into account the effect of curved junctions of finite depth. The analytical model is compared to MINIMOS simulations showing that it can accurately predict short-channel threshold voltage falloff and threshold voltages in this vicinity without the use of fitting parameters.     

An anomalous increase of threshold voltages with shortening the channel lengths for deeply boron-implanted N-channel MOSFET's

In relatively heavily and deeply boron-implanted n-channel MOSFET's, we found the anomalous phenomenon that the threshold voltage increases with decreasing channel length over a wide range of channel lengths. This is quite contrary to the well-known short-channel effect associated with the dependence of the threshold voltage on the channel length. It is difficult to explain this phenomenon directly by any simplified models that have been presented to date. In this brief, we present mainly the detailed experimental results of such an anomalous short-channel effect.     

Thermal-oxide gate GaAs MOSFET's

The first thermal-oxide gate GaAs MOSFET of the deep-depletion mode is reported. The gate oxide, which has been grown by the new GaAs oxidation technique in the As2O3vapor, is so chemically stable that it can be subjected to the fabrication process. Measurement of some dc characteristics of the device fabricated has shown a strikingly suppressed hysteresis.     

Modeling of threshold voltage of a quadruple gate transistor

In this paper, a three dimensional analytical solution of electrostatic potential is presented for undoped (or lightly doped) quadruple gate MOSFET by solving 3-D Poisson's equation. It is shown that the threshold voltage predicted by the analytical solution is in close agreement with TCAD 3-D numerical simulation results. For numerical simulation, self-consistent Schrodinger-Poisson equations, calibrated by 2D non equilibrium green function simulation, are used. This analytical model not only provides useful physics insight of effects of gate length and body width on the threshold voltage, but also serves as a basis for compact modeling of quadruple gate MOSFETs.     

Nondestructive determination of MOSFET gate breakdown voltage

A method is presented which allows the gate breakdown of a MOSFET to be nondestructively determined. The method applies a linear ramp voltage across the gate, allowing the leakage component to be easily separated from the capacitive currents. In this manner, the leakage component can be measured before it becomes large enough to cause a destructive dielectric breakdown in the gate oxide.     

Ultrathin oxide-nitride gate dielectric MOSFET's

The first ultrathin oxide-nitride (O-N) gate dielectrics with oxide equivalent thickness of less than 2 nm have been deposited and characterized in n-MOSFET's. The O-N gates, deposited by remote plasma-enhanced CVD, demonstrate reduced gate leakage when compared with oxides of equivalent thickness while retaining comparable drive currents     

Buried channel MOSFET's with gate lengths from 2.5 µm to 700 Å

High resolution electron beam lithography has been used to fabricate ion implanted buried channel MOSFET's with gate lengths ranging from 0.4 µm to 700 Å. Similar devices were also fabricated on the same chip using optical lithography with gate lengths of 2.5 µm. These devices include some with the smallest lithographically defined gates ever made in silicon; similar devices should help define the limits to miniaturization in semiconducting devices.     

多层浮栅FET pH传感单元阈值电压敏感模型分析和讨论

Research into new pH sensors fabricated by the standard CMOS process is currently a hot topic. The new pH sensing multi-floating gate field effect transistor is found to have a very large threshold voltage, which is different from the normal ion-sensitive field effect transistor. After analyzing all the interface layers of the structure, a new sensitive model based on the Gauss theorem and the charge neutrality principle is created in this paper. According to the model, the charge trapped on the multi-floating gate during the process and the thickness of the sensitive layer are the main causes of the large threshold voltage. From this model, it is also found that removing the charge on the multi-floating gate is an effective way to decrease the threshold voltage. The test results for three different standard pH buffer solutions show the correctness of the model and point the way to solve the large threshold problem.     

Analytical model for threshold voltage of double gate bilayer graphene field effect transistors

A new model for threshold voltage of double-gate Bilayer Graphene Field Effect Transistors (BLG-FETs) is presented in this paper. The modeling starts with deriving surface potential and the threshold voltage was modeled by calculating the minimum surface potential along the channel. The effect of quantum capacitance was taken into account in the potential distribution model. For the purpose of verification, FlexPDE 3D Poisson solver was employed. Comparison of theoretical and simulation results shows a good agreement. Using the proposed model, the effect of several structural parameters i.e. oxide thickness, quantum capacitance, drain voltage, channel length and doping concentration on the threshold voltage and surface potential was comprehensively studied.     

Matching degradation of threshold voltage and gate voltage of NMOSFET after Hot Carrier Injection stress

Device degradation modelling is more and more important for reliable circuit design. On MOSFET, the threshold voltage drift in time can lead to circuit performance degradation. In this study, V_T shift due to Hot Carrier Injection stress is accelerated on small width devices. V_T matching is also degraded during stress as a function of V_T deterioration. This width dependence allows explaining gate voltage matching behavior in the sub-threshold area used in low power analog applications.     

A voltage tunable threshold logic gate based on multiquantum-wellheterojunction bipolar transistor for multifunction logic

The properties of a heterojunction bipolar transistor with a multiquantum-well collector region for its application as a voltage tunable logic element are examined. The quantum confined Stark effect gives rise to a strong negative differential resistance in the photocurrent-voltage characteristic of the device, which allows the device to be switched optically and/or electronically. This permits the realization of a circuit where the NAND, INVERSE CARRY, and NOR logic functions can be implemented by simply changing the biasing     

A semi-empirical analytic model for threshold voltage instability in MOSFETs with high-k gate stacks

n the threshold voltage and the induced trap density. The obtained model is also verified by extensive experimental data of trapping and de-trapping stress from different high-k gate configurations.     

高K栅堆叠结构MOSFET器件阈值电压不稳定度的半经验解析模型

A semi-empirical analytic model for the threshold voltage instability of MOSFET is derived from the Shockley-Read-Hall (SRH) statistics in this paper to account for the transient charging effects in a MOSFET high-k gate stack. Starting from the single energy level and single trap assumption, an analytical expression of the filled trap density in terms of the dynamic time is derived from the SRH statistics. The semi-empirical analytic model of the threshold voltage instability is developed based on the MOSFET device physics between the threshold voltage and the induced trap density. The obtained model is also verified by the extensive experimental data of the trapping and de-trapping stress from the different high k gate configuration.     

Analytical model for threshold voltage shift due to impuritypenetration through a thin gate oxide

We derived an analytical model for the threshold voltage shift due to impurity penetration through gate oxide and evaluated the thermal budget for pMOS devices with a thin gate oxide. The threshold voltage shift decreases as the channel doping concentration increases, but the decrease is quite small. The allowable surface concentration of the penetrated impurity increases as the gate oxide thickness decreases if the allowable threshold voltage shift is constant. Therefore, the allowable diffusion length normalized by the gate oxide thickness d_ox increases with decreasing d_ox