基于Verilog-A的Sigma Delta系统行为级建模

介绍Verilog-A设计语言的特点,基于Sigma Delta系统介绍分级设计思想.分析开关电容型Sigma Delta调制器的非理想特性,主要包括时钟抖动、开关热噪声、运放增益、摆率等.在建立各自噪声模型的基础上,基于Verilog-A对二阶Sigma Delta系统行为级完整建模,通过仿真结果的比对,验证Verilog-A建模,总结其可准确预测指标并在一定程度上有效地削减仿真时间的优点.     

An in-plane high-sensitivity, low-noise micro-g silicon accelerometer with CMOS readout circuitry

A high-sensitivity, low-noise in-plane (lateral) capacitive silicon microaccelerometer utilizing a combined surface and bulk micromachining technology is reported. The accelerometer utilizes a 0.5-mm-thick, 2.4/spl times/1.0 mm/sup 2/ proof-mass and high aspect-ratio vertical polysilicon sensing electrodes fabricated using a trench refill process. The electrodes are separated from the proof-mass by a 1.1-/spl mu/m sensing gap formed using a sacrificial oxide layer. The measured device sensitivity is 5.6 pF/g. A CMOS readout circuit utilizing a switched-capacitor front-end /spl Sigma/-/spl Delta/ modulator operating at 1 MHz with chopper stabilization and correlated double sampling technique, can resolve a capacitance of 10 aF over a dynamic range of 120 dB in a 1 Hz BW. The measured input referred noise floor of the accelerometer-CMOS interface circuit is 1.6/spl mu/g//spl radic/Hz in atmosphere.     

CMOS图像传感器中分段电容DAC非理想因素研究

CMOS图像传感器信号处理中通常采用分段电容DAC产生斜坡参考电压。研究了分段电容DAC精确的电容失配及寄生与其转换精度的关系式。基于对分段电容DAC工作原理的研究,导出了电容失配及寄生模型;针对其分数桥接电容失配、各二进制电容间的失配及寄生电容问题进行了理论分析;对分段电容DAC进行非理想因素仿真,设计了一个采用分段电容DAC的10位单斜ADC并对其进行测试,仿真和测试结果均验证了理论分析的正确性。上述理论分析结果可作为分段电容DAC的设计指导。     

A fully-digital and ultra-low-power front-end for differential capacitive sensors

In this paper, we present a simple, compact and low-power interface for differential capacitive sensors with a direct digital output. The complete system is composed with a current to voltage converter, an integrator, a comparator and a one-bit digital to analog converter as a feedback. The so-obtained Sigma–Delta modulator is able to deliver directly a bit stream with a ratio of logical ‘1’ directly proportional to the differential capacitance to be measured. A partially integrated prototype has been realized to demonstrate accuracy and non-linearity compatible with a 9-bit sensor.

     

一种用于差分电容检测的电荷Delta-Sigma调制器的研究

研究一种用于差分电容传感器检测的电荷Delta-Sigma调制器结构.在该检测电路中不需要C/V转换电路,待检测的差分电容直接作为调制器环路的输入电容,差分电容的变化量首先被转换为变化的电荷,然后被调制成一位的数字输出信号.文章最后给出了一个二阶的Delta-Sigma调制器的行为级仿真结果.     

基于Simulink的∑△调制器的非理想性建模

基于Simulink的系统级模型有助于分析开关电容ΣΔ调制器的各种非理想特性,包括时钟抖动、MOS开关噪声、运算放大器的输入参考噪声、有限直流增益、压摆率和比较器的迟滞性等。为建立各非理想特性与调制器性能之间的关系,对一个非理想特性的5阶单比特ΣΔ调制器进行系统仿真,定量得出各非理想特性对调制器性能的影响。该非理想性系统模型有助于在系统级有效制定出各子模块的性能参数。     

一种用于ADSL的高精度调制器的建模与仿真

要模数转换问题的研究中,介绍了∑-△调制器的过采样和噪声整形技术,为提高转换精度和速率,提出了一个采用四阶级联结构和∑-△调制技术实现高精度的调制器的行为级模型,根据影响建模的各种非理想因素,对各种实际非理想因素(例如开关热噪声、时钟抖动、运放的有限直流增益等)通过优化系统参数之后,可以得到一个用于ADSL设计中的高精度∑-△调制器行为级模型。并在MATLAB下对其仿真验证,结果表明为实际设计提供了依据。调制器在基带带宽1.5MHz、24倍过采样率条件下,系统的信噪比达到87dB,精确度可达14比特。     

一种Sigma-Delta调制器的电路实现

由于过采样sigma-delta调制器结构简单,并对电路的非理想因素要求不高,它被广泛应用在信号处理中。这里提出了16-bit,1.2-Ms/s调制器的具体实现电路。在Chartered 0.35?m CMOS工艺库下通过了仿真和验证,这个调制器的SNR可以达到93dB,在3.3V电源下功耗为200mW。     

高阶∑△ADC中积分器的设计

基于N阱0.6μm DPDM CMOS工艺,完成了高阶∑△ADC中第一级积分器的设计。分析了开关电容积分器的非理想特性,同时设计了一个对寄生电容不敏感的同相开关电容(SC)积分器,并特别采用旁路电容减小沟道电荷注入引起的谐波失真和噪声。在cadence下的电路仿真表明,积分器具有-104.9dB等效输入噪声;利用MATLAB进行系统仿真,∑△ADC的信号噪声畸变比(SNDR)达到100.5dB,满足系统16bit的要求。     

Multivalent analog functional blocks for Sensor-ASIC circuit design

In Sensor-ASIC circuit design several basic analog functional blocks can be identified, which occur frequently and therefore may be designed for multivalent purposes. This usually refers to structures as time-continuous pre-amplifiers, gain-programmable amplifiers in switched-capacitor (SC) technique, filters in SC technique, current sources, programmable bandgap references, and one time programmable (OTP) registers, which store the data for the adjustment of the analog components. The design and some parametric results of those functional blocks will be presented and described, as well as their application in two different Sensor-ASICs being fabricated in an in-house 5 V 1 μm CMOS process.     

基于CMOS的开关电容DC-DC降压变换器

在标准CMOS工艺的基础上,分析了基本串并电容组合开关电容DC-DC降压变换器的工作原理和集成方法.采用两个单端开关电容变换器反相并联联结,降低了输出电压波纹.利用电路内部节点电压驱动MOS开关管,避免了每个开关管都必须单独驱动.用SPICE软件对电路进行了瞬态分析,给出了分析结果.     

正交调制器的非线性建模及校正

本文通过对正交调制器进行非线性建模和补偿,校正了其线性和非线性失真。实验结果表明,该正交调制器模型和补偿模型可以有效地解决其非理想特性引起的失真问题。     

18位高精度音频Σ-ΔDAC设计

采用基于过采样Σ-ΔDAC调制技术设计的音频D/A转换器,对量化噪声进行有效整形,提高了分辨率和带内信噪比(SNR)。重点对Sigma-delta设计进行了详细分析,给出了有关电路结构和仿真结果。芯片已在TSMC 0.18μm CMOS工艺上流片成功,在工作频率6.144MHz时动态范围达128.6dB,信噪比109.5dB,总谐波失真达-117.2dB。     

A novel broadband MMIC vector modulator for V‐band applications

In this study, a new vector modulator topology is presented. The modulator is composed by two “balanced‐load” biphase modulators. The balanced load is a novel principle allowing a topological simplification of commonly adopted vector modulator schemes: seven couplers are used instead of the 9 ones in traditional reflection‐type modulators, with comparable performance. The measured results of monolithic 45–65 GHz test vehicles of the methodology for both biphase and vector modulators, are presented. © 2009 Wiley Periodicals, Inc. Int J RF and Microwave CAE 2010.     

Parallel implementation of isothermal and isoenergetic Dissipative Particle Dynamics using Shardlow-like splitting algorithms

A parallel implementation of the Shardlow splitting algorithm (SSA) for Dissipative Particle Dynamics (DPD) simulations is presented. The isothermal and isoenergetic SSA implementations are compared to the DPD version of the velocity-Verlet integrator in terms of numerical stability and performance. The integrator stability is assessed by monitoring temperature, pressure and total energy for both the standard and ideal DPD fluid models. The SSA requires special consideration due to its recursive nature resulting in more inter-processor communication as compared to traditional DPD integrators. Nevertheless, this work demonstrates that the SSA exhibits stability over longer time steps that justify its regular use in parallel, multi-core applications. For the computer architecture used in this study, a factor of 10–100 speedup is achieved in the overall time-to-solution for isoenergetic DPD simulations and a 15–34 speedup is achieved for the isothermal DPD simulations.     

Design automation of a lossless multiport network and its application to image filtering

The paper presents expert tools which are elaborated on the basis of synthesis method of lossless nonreciprocal multiport circuits, composed of gyrators and capacitors. The algorithms are written in C++ and the tools compose a user friendly environment for design automation of filters, filter pairs and filter banks. It is possible to design in this environment not only classical structures like Butterworth, Chebyshev, and Cauer (elliptic) filters. The lossless nonreciprocal prototype circuit allows to design more complex filters, including allpass sections necessary to improve filter phase characteristics. However, the most important possibility is to design multiport circuits, especially in the case of not fully determined filter specifications. On each stage of the design process VHDL-AMS is used to describe the circuits. The obtained prototype gyrator-capacitor circuit can be implemented in OTA-C, SC (switched-capacitor) or SI (switched-current) techniques to realize the filter in CMOS technology. In the paper SI technique is used for layout generation of an image filter in order to illustrate the elaborated synthesis algorithms and tools.     

基于滑模控制的Sigma-Delta调制器参数设计和优化

将滑模控制策略引入到Sigma-Delta调制器设计中,用于分析一位比较器环节对Sigma-Delta调制器系统产生的非线性影响。通过将Sigma-Delta调制器中积分器的状态输出作为研究变量,一位比较器环节作为变结构单元对系统工作原理进行重新建模,同时基于滑模变结构控制理论推导出了采用近似线性化方法分析一位比较器非线性特性需满足的基础条件。在保证满足一位比较器环节可近似线性化处理的基础上,采用智能优化算法对Sigma-Delta调制器系统参数进行优化设计,降低了调制器系统参数设计难度,同时进一步提高系统性能。理论分析和仿真结果验证了本文方法的可行性和有效性。     

利于集成且对杂散电容抑制性极佳的开关电容型滤波器

采用单位缓冲器设计对杂散电容不灵敏的开关电容(SC)频率相关负电阻(FDNR)元件,利用该元件对椭圆函数式LC低通滤波器进行SC模拟。为了获得电容最佳值,提出了一种简单的最优化方法;并采用寄生电阻预畸变与SC负电阻相结合的办法,设计的SC滤波器对杂散电容不灵敏,且电路简单。采用分立元件制作了一个五阶椭圆低通SC-FDNR滤波器,实验结果表明该方法实用可行,效果明显。     

一种增益自举运算放大器的分析与优化设计

基于开关电容的流水线ADC设计中,运算放大器的建立时间和精度是关键指标。而增益自举运算放大器的建立时间分析比较复杂。本文通过理论推导和模型简化的方法分析其主运放和辅助运放的单位增益带宽及相位裕度对建立时间的影响。提出了一种P型与N型传输函数相同的辅助运放电路,并以此设计了一个高速、低功耗的自举运算放大器。     

Finite-pulse stability of interconnected systems with complete-reset pulse frequency modulators

An interconnected system of complete-reset pulse frequency modulators (CRPFM's) and linear dynamic subsystems is considered. Upper bounds are determined for the number of pulses emitted by each modulator. Each of these bounds represents a measure of the energy spent by the respective modulator. Finiteness of these bounds for all modulators constitues finite-pulse stability and implies finite energy expanded. Sufficient conditions are established for finite-pulse stability.