用于生物荧光检测的高灵敏CMOS双结深光电传感器设计

基于标准CMOS工艺,可实现单结深光电二极管传感器(p+/n-well、n-well/p-sub和n+/p-sub)和双结深光电二极管传感器(p+/n-well/p-sub)。建立了双结深光电二极管传感器的光电响应数学模型,仿真了四种结构的光敏响应。采用上华0.5μm CMOS工艺实现了p+/nwell和p+/n-well/p-sub两种结构,传感面积为100μm×100μm。p+/n-well型结构在400nm波长,60lux光强下光电流为1.55nA,暗电流为13pA,p+/n-well/p-sub型结构在同等条件下光电流为2.15nA,暗电流为11pA。测试表明,设计的双结深光电传感器具有更高的灵敏度,可用于微弱的生物荧光信号检测。     

双结光电二极管荧光检测单元暗电流优化设计

双结p+/n-well/p-sub光电二极管由于其较高灵敏度、低暗电流而成为荧光检测光电传感单元的最佳选择.文章基于0.5 μm CMOS工艺对双结p+/n-well/p-sub光电二极管进行了版图优化设计,有效减少了硅和二氧化硅界面对光电二极管光吸收区暗电流的影响.流片后测试表明优化后版图面积为100μtm×100 μm,双结p+/n-well/p-sub光电二极管单元的暗电流从11 pA减小到了6.5pA,光电流从2.15 nA稍有减弱到2.05 nA,光暗电流比值提高了60％.优化后的双结p+/n-well/p-sub光电二极管更适用于对微弱的荧光信号检测.     

一维0.18μm CMOS光电二极管量子效率的研究与模拟

为了建立更精确的CMOS光电二极管SPICE模型,使之在像素电路模拟中能够更好地反映实际的光电转换物理现象.使用连续性方程和不同的边界条件对CMOS光电二极管建立了一维物理模型,然后代入普通 CMOS 0.18工艺参数在温度为300 K、反偏电压为2.2 V时,对N-diff/P-epi, N-well/P-epi两种结构的二极管量子效率进行了模拟.其中考虑了表面复合速率、外延层厚度、P 衬底与P外延同质结等因素对模拟结果的影响.在此基础上,还对CMOS光栅二极管的量子效率进行了计算. 模拟结果符合这些器件已知的特性.     

超晶格雪崩光电二极管的结构优化及性能研究

基于碰撞离化理论研究了异质材料超晶格结构对载流子离化率的作用,设计得到In0.53Ga0.47As/In0.52Al0.48As超晶格结构的雪崩光电二极管。通过分析不同结构参数对器件性能的影响,得到了低隧道电流、高倍增因子的超晶格结构雪崩层,根据电场分布方程模拟了器件二维电场分布对电荷层厚度及掺杂的依赖关系,并优化了吸收层的结构参数。对优化得到的器件结构进行仿真并实际制作了探测器件,进行光电特性测试,与同结构普通雪崩光电二极管相比,超晶格雪崩光电二极管具有更强的光电流响应,在12.5~20 V的雪崩倍增区,超晶格雪崩光电二极管在具备高倍增因子的同时具有较低的暗电流,提高了器件的信噪比。     

InGaAs/InP SAGCM-APD的器件模型及其数值模拟

基于泊松方程和载流子连续性方程,导出了InGaAs/InP SAGCM-APD(吸收、渐变、电荷、倍增层分离结构雪崩光电二极管)特性的数学模型,利用数值计算工具对其进行了数值模拟,得到了APD内部电场分布、增益特性、暗电流特性、过剩噪声和增益带宽特性等的数值结果.模拟结果与实际器件特性测量结果相符合,表明运用该模型与数值模拟方法可对不同结构参数的InGaAs/InP SAGCM-APD进行结构设计、工艺改进和特性分析.     

1-3微米光谱区外延HgCdTe/CdTe光电二极管

已经成功地生长出用于1—3微米波段的有不同组分的HgCdTe/CdTe外延层。通过注入硼生长p-型层或两面注入生长p-型和n-型层以形成n~+/p结。在没有增透膜时,短波红外HgCdTe光电二极管的量子效率为55～56％。在室温下,截止波长为1.39微米的二极管,其零偏电阻—面积乘积(R_0A)是4×10~4欧姆-厘米~2。截止波长为2.4微米的光电二极管,在195K下,测量得的R_0A乘积同样是～10~4欧姆一厘米~2。二极管的R_0A乘积与能隙和温度的依赖关系,与受产生—复合模型限制的体晶的结果非常吻合。短波红外二极管的击穿电压可从12伏变到130伏以上,这要看Cd的组分(x)和本底载流子浓度而定。     

高边缘击穿和扩展光谱的圆形单光子雪崩二极管

介绍了一种0. 18μm互补金属氧化物半导体(CMOS)技术的新型宽光谱荧光相关谱探测器,其为高边缘击穿、扩展光谱和低暗计数率的圆形单光子雪崩二极管(SPAD).该器件由p+/deep n-well结,p-well保护环和多晶硅保护环组成.通过Silvaco TCAD 3D器件仿真,直径为10μm的圆形p+/deep n-well SPAD器件具有较高边缘击穿特性.此外,p+/deep n-well结SPAD比p+/n-well结SPAD具有更长的波长响应和扩展光谱响应范围.该器件在0. 5 V过量偏压下,可在490～775 nm波长范围内实现超过40%的光子探测率.该圆形p+/deep n-well SPAD器件在25℃时具有较好雪崩击穿为15. 14 V,具有较低暗计数率为638 Hz.     

高边缘击穿和扩展光谱的圆形单光子雪崩二极管（英文）

介绍了一种0. 18μm互补金属氧化物半导体(CMOS)技术的新型宽光谱荧光相关谱探测器,其为高边缘击穿、扩展光谱和低暗计数率的圆形单光子雪崩二极管(SPAD).该器件由p+/deep n-well结,p-well保护环和多晶硅保护环组成.通过Silvaco TCAD 3D器件仿真,直径为10μm的圆形p+/deep n-well SPAD器件具有较高边缘击穿特性.此外,p+/deep n-well结SPAD比p+/n-well结SPAD具有更长的波长响应和扩展光谱响应范围.该器件在0. 5 V过量偏压下,可在490～775 nm波长范围内实现超过40%的光子探测率.该圆形p+/deep n-well SPAD器件在25℃时具有较好雪崩击穿为15. 14 V,具有较低暗计数率为638 Hz.     

可应用于光互连的新型高带宽、高灵敏度差分光接收机的概念提出与设计

提出了一种可应用于高速光通信和光互连的新型高带宽、高灵敏度差分光接收机.其中,高带宽和高灵敏度分别通过输入负载平衡的全差分跨阻前置放大器和将入射光信号转换成一对差分光生电流信号的两个光电探测器来实现.与常用光接收机相比,这种新型光接收机无任何附加成本.设计了一种相应的、与0.35μm标准CMOS工艺完全兼容的光电集成接收机.其中,光电探测器采用面积为60μm×30μm、结电容为1.483pF的插指型p+/n-well/p-substrate光电二极管.仿真结果表明:该光电集成接收机的带宽为1.37GHz;跨阻增益为81.9dBΩ;面积为0.198mm2;数据传输率至少可达2Gb/s;对于215-1位的输入伪随机码序列(PRBS),在误码率为10-12条件下,灵敏度至少可达-13dBm.     

新型敏紫硅光伏二极管

本文从分析普通N~+/P(或P~+/N)结硅光伏二极管的短波响应限制机理出发,介绍一种用于提高短波量子效率的新结构敏紫硅光伏二极管——氧化层电荷感应高低结(以下缩写为OCI-HLJ)硅光伏二极管.实验结果表明,OCI-HLJ结构,可以明显地增强硅光伏二极管在蓝紫和紫外方面的光量子效率.在波长为365nm时,OCI-HLJ硅光伏二极管的光谱响应度达0.23μA/μW,在253nm的紫外光处,仍具有很高的光谱灵敏度.OCI-HLJ结构,是制作敏紫硅光电器件的一种切实可行的新型结构.     

Extended One-Dimensional Analysis to Effectively Derive Quantum Efficiency of Various CMOS Photodiodes

This paper proposes an extended 1-D analysis to derive quantum efficiency of various commonly used CMOS photodiodes. The theoretical model of the CMOS photodiode with the n-/p-epitaxial/p + substrate (n-/p-epi/p + sub) structure is established from steady-state continuity equations, where most existing boundary conditions are applied. In particular, the minority carrier and current densities are continuous across the interface between two layers with the same dopant type. Models of the other commonly used CMOS photodiodes are also examined. Three CMOS photodiodes with n-/p-substrate (n-/p-sub), p⁺/n-/p-substrate (p⁺/n-/p-sub), and n-/p-epi/p + sub structures are fabricated and characterized to validate the proposed model. Additionally, the surface recombination velocity is adequately determined by fitting the simulated quantum efficiency to the measured value. The simulated quantum efficiency of the proposed model for these three photodiodes is quite consistent with the measured values, revealing the feasibility and effectiveness of the proposed model in characterizing various CMOS photodiodes.     

Towards a SPR-based biosensing platform incorporating a CMOS active column sensor

A biosensing platform based on surface plasmon resonance and incorporating a CMOS imager is being developed. This work comprises three different tasks towards this goal: a numerical analysis to determine the optimal plasmon resonance conditions, a numerical analysis to select the best CMOS photodiode and the architecture proposal of a CMOS imager. A simulation with COMSOL of a Kretschmann configuration using CMOS/post-CMOS compatible materials, a silicon dioxide prism and a gold–water interface, showed an optimal metal thickness of 50 nm and the associated incidence resonance angle of 68.46°. Then, a simulation with Silvaco ATLAS of two different CMOS photodiodes, a n-diff/p-sub and a n-well/p-sub, showed that the latter has a maximum quantum efficiency of 82 % and a photcurrent of 85 nA at 633 nm. This photodiode was selected as the photosensing element in a 20 × 20 μm² pixel with a 61 % fill factor. A 32 × 32-pixel CMOS active column sensor (ACS) with fixed pattern noise (FPN) reduction was proposed. It includes non-correlated double sampling and double delta sampling schemes for noise handling. The reduction of the output’s variance was demonstrated through Monte Carlo analysis. An experimental optical setup was used to characterize the performance of the imager, obtaining a conversion gain of 7.3 μV/e^? and a photodiode capacitance of 22 fF, showing good agreement with the values obtained with electrical simulation of 5.2 μV/e^? and 31 fF. The measured full-well saturation was of 118.8 × 10³ e^? or 2.4 V. Finally, pixel-FPN and column-FPN of 0.09 and 0.06 % respectively were obtained. The low FPN levels demonstrate the benefits of the ACS and noise reduction circuits implemented. This work provide valuable information for the upcoming implementation of an integrated SPR-biosensing platform incorporating a CMOS-ACS.     

Leakage current modeling of test structures for characterization of dark current in CMOS image sensors

In this paper, we present an extensive study of leakage current mechanisms in diodes to model the dark current of various pixel architectures for active pixel CMOS image sensors. Dedicated test structures made in 0.35-/spl mu/m CMOS have been investigated to determine the various contributions to the leakage current. Three pixel variants with different photodiodes-n/sup +//pwell, n/sup +//nwell/p-substrate and p/sup +//nwell/p-substrate-are described. We found that the main part of the total dark current comes from the depletion of the photodiode edge at the surface. Furthermore, the source of the reset transistor contributes significantly to the total leakage current of a pixel. From the investigation of reverse current-voltage (I-V) characteristics, temperature dependencies of leakage current, and device simulations we found that for a wide depletion, such as n-well/p-well, thermal Shockley-Read-Hall generation is the main leakage mechanism, while for a junction with higher dopant concentrations, such as n/sup +//p-well or p/sup +//n-well, tunneling and impact ionization are the dominant mechanisms.     

基于标准CMOS工艺的光敏传感单元结构的研究

基于0.6μm标准N阱CM O S工艺,研究了光敏管的结深及其侧墙结构对有源感光单元的感光面积百分比、光电响应信号幅值、感光灵敏度以及感光动态范围等参数的影响。研究了包括传统N+/P衬底的光敏管结构,以及网格状N+/P衬底,N阱/P衬底,网格状N阱/P衬底,P+/N阱/P衬底的光敏管结构。测试结果表明,不同深结深的光敏管结构,可以将器件感光灵敏度提高8~16.5 dB;网格状光敏管结构可以增加光敏管的侧墙面积,改善器件感光灵敏度;非网格状光敏管结构具有较低的暗电流和较大的感光动态范围,其中P+/N阱/P衬底光敏管结构的传感单元在变频两次扫描的工作方式下的感光动态范围可达139.8 dB。     

Transport model in n++-poly/SiOx/SiO2/p-sub MOS capacitors for low-voltage nonvolatile memoryapplications

The origin of enhanced injection in n⁺⁺-poly/SiO_x /SiO₂/p-sub MOS capacitors under accumulation is investigated. Starting from experimental evidences as the structural homogeneity of the off-stochiometric oxide and the temperature dependence of current in n⁺⁺-poly/SiO_x/p-sub capacitors, we developed a new transport model. In this picture, transport consists on the Poole-Frenkel and multistep tunneling of the SiO_x barrier and the Fowler-Nordheim (FN) tunnel of the SiO ₂ barrier, the latter definitely limiting the current flowing through the MOS. The model explains how the presence of two barriers and an accelerating electric field in the SiO_x gives rise to the injection enhancement, respect to the case of a single conventional n ⁺⁺-poly/SiO₂ barrier. In fact, after the trap-assisted tunnel of the first barrier, the electron arrives at the SiO_x/SiO₂ interface with an excess energy furnished by the electric field. There, it sees an FN barrier lower than in the conventional case. Experiment and model calculations are in excellent agreement     

Process and device performance of 1 /spl mu/m channel n-well CMOS technology

The process and device performance of 1 /spl mu/m-channel n-well CMOS have been characterized in terms of substrate resistivities of 40 and 10 /spl Omega/-cm, substrate materials with and without an epitaxial layer, n-well surface concentrations ranging from 5/spl times/10/SUP 15/ to 4/spl times/10/SUP 16/ cm/SUP -3/, n-well depths of 3, 4, and 5 /spl mu/m, channel boron implantation doses from 2/spl times/10/SUP 11/ to 1.3/spl times/10/SUP 12/ cm/SUP -2/, and effective channel lengths down to 0.6 /spl mu/m. Based on the experimental results obtained from /spl mu/m-channel n-well CMOS devices, the scaling effects on device and circuit performance of 0.5 /spl mu/m-channel n-well CMOS are discussed and the deep-trench-isolated CMOS structure is demonstrated.     

1.0-/spl mu/m n-Well CMOS/Bipolar Technology

High-performance 1.0-/spl mu/m n-well CMOS/bipolar on-chip technology was developed. For process simplicity, an n-well and a collector of bipolar transistors were formed simultaneously, and base and NMOS channel regions were also made simultaneously resulting in collector-isolated vertical n-p-n bipolar transistor fabrication without any additional process step to CMOS process. On the other hand, 1.0-/spl mu/m CMOS with a new "hot carrier resistant" seIf-defined Polysilicon sidewall spacer (SEPOS) LDD NMOS was developed. It can operate safely under supply voltage over 5 V without performance degradation of CMOS circuits. By evaluating ring oscillators and differential amplifiers constructed by both CMOS and bipolar transistors. it can be concluded that in a digital and in an analog combined system, CMOS has sufficiently high-speed performance for digital parts, while bipolar is superior for analog parts. In addition, bipolar transistors with an n/sup +/-buried layer were also fabricated to reduce collector resistance. Concerning the bipolar input/output buffers, the patterned n/sup +/-buried layer improves the drivability and high-frequency response. As a result, the applications of n-well CMOS/bipolar technology become clear. This technology was successfully applied to a high-speed 64-kbit CMOS static RAM, and improvement in access time was observed.     

Process and Device Performance of Submicrometer-Channel CMOS Devices Using Deep-Trench Isolation and Self-Aligned TiSi/sub 2/ Technologies

According to our scaling study, a deeper n-well allows for a lower n-well surface concentration with improved short-channel effects in submicrometer-channel PMOS-FET's. The deep n-well, however, requires a large space between n- and p-channel devices. This large space limits the integration density in scaled bulk CMOS VLSI's. The deep-trench isolation combined with an epitaxial layer resolves this drawback with significantly improved device-to-device isolation and latchup susceptibility. The 6-/spl mu/m-deep with 2-/spl mu/m-wide deep trench is etched in the epitaxial layer and is refilled with 1500 /spl Aring/ of thermal silicon-dioxide film and 2/spl mu/m of polysilicon film. The sheet resistances of N/sup +/ and P/sup +/ diffusion and N/sup +/ -doped polysilicon layers were reduced to 3 to 4 /spl Omega//spl square/ by using the self-aligned TiSi/sub 2/ layer with an oxide sidewall spacer. As a result of this low sheet resistance, the saturation drain current of submicrometer n- and p-channel MOSFET's was improved approximately 33 to 37 percent compared with conventional MOSFET's without the self-aligned TiSi/sub 2/ layer. The 0.5-/spl mu/m-channel CMOS devices using the deep-trench isolation with an epitaxial layer and the self-aligned TiSi/sub 2/ layer operated at a propagation delay time of 140 ps with a power dissipation of 1.1 mW per inverter and attained a maximum clock frequency of 400 MHz in a static /spl divide/ 4 counter without suffering from Iatchup even at the Iatchup trigger current of 200 mA.     

3-GHz Silicon Photodiodes Integrated in a 0.18-$mu$m CMOS Technology

A new PIN photodiode (PD) structure with deep n-well (DNW) fabricated in an epitaxial substrate complementary metal–oxide–semiconductor (epi-CMOS) process is presented. The DNW buried inside the epitaxial layer intensifies the electric field deep inside the epi-layer significantly, and helps the electrons generated inside the epi-layer to drift faster to the cathode. Therefore, this new structure reduces the carrier transit time and enhances the PD bandwidth. A PD with an area of $70times 70 mu$m $^{2}$ fabricated in a 0.18- $mu$m epi-CMOS achieves 3-dB bandwidth of 3.1 GHz in the small signal and 2.6 GHz in the large signal, both with a 15-V bias voltage and 850-nm optical illumination. The responsivity is measured 0.14 A/W, corresponding to a quantum efficiency of 20%, at low bias. The responsivity increases to 0.4 A/W or 58% quantum efficiency at 16.2-V bias in the avalanche mode.