CCII-Based Grounded to Floating Immittance Converter and a Floating Inductance Simulator

A new circuit employing second-generation current conveyors (CCIIs), and unmatched resistors for converting a grounded immittance to the corresponding floating immittance with either positive or negative adjustable multiplier, is presented. Moreover, the proposed circuit can also realize a synthetic floating inductance employing a grounded capacitor depending on the passive element selection. Simulation results using 0.35 μ m TSMC CMOS technology parameters are given. Erkan Yuce was born in 1969 in Nigde, Turkey. He received the B.Sc. from Middle East Technical University and M.Sc. degrees from Pamukkale University in 1994 and 1998 respectively. He is a Ph.D. student at Bogazici University all in Electrical and Electronics Engineering. He is currently Research Assistant at the Electrical and Electronics Engineering Department of Bogazici University. His current research interests include analog circuits, active filters, synthetic inductors, and current-mode circuits. He is the author or co-author of about 10 papers published in scientific journals or conference proceedings. Oguzhan Cicekoglu was born in 1963 in Istanbul, Turkey. He received the B.Sc. and M.Sc. degrees from Bogazici University and the Ph.D. degree from Istanbul Technical University all in Electrical and Electronics Engineering in 1985, 1988 and 1996 respectively. He served as lecturer at the School of Advanced Vocational Studies Electronics Prog. of Bogazici University where he held various administrative positions between 1993 and 1999, and as part time lecturer at various institutions. He was with Biomedical Engineering Institute between 1999 and 2001. He is currently Associate Professor at the Electrical and Electronics Engineering Department of Bogazici University. His current research interests include analog circuits, active filters, analog signal processing applications and current-mode circuits. He is the author or co-author of about 150 papers published in scientific journals or conference proceedings. Oguzhan Cicekoglu is a member of the IEEE. Shahram Minaei received his B.Sc. degree in Electrical and Electronics Engineering from Iran University of Science and Technology in 1993. He received his M.Sc. and Ph.D. degrees in Electronics and Communication Engineering from Istanbul Technical University in 1997 and 2001, respectively. He is currently an Associate Professor at the Electronics and Communication Engineering Department of Dogus University in Istanbul, Turkey. He has more than 50 journal or conference papers in scientific review. He served as reviewer for a number of international journals and conferences. His current field of research concerns current-mode circuits and analog signal processing. Shahram Minaei is a member of the IEEE.     

The Effects of Non-Idealities and Current Limitations on the Simulated Inductances Employing Current Conveyors

Active devices such as current conveyors play an essential role on the performance of simulated inductances. The effects of second-generation current conveyor (CCII) non-idealities on the proposed and on the previously published inductances are investigated, in which lossless inductances are realized. CCIIs like all active devices have terminal current limitations that can not be exceeded. Thus, the values of the applied input current sources for the proposed and previously published inductances depending on the passive elements values and applied signal frequency impose restrictions on the input current of the inductor. Erkan Yuce was born in 1969 in Nigde, Turkey. He received the B.Sc. degree from Middle East Technical University and M.Sc. degree from Pamukkale University in 1994 and 1998 respectively, all in Electrical and Electronics Engineering. He is currently Research Assistant and a Ph.D. student at the Electrical and Electronics Engineering Department of Bogazici University. His current research interests include analog circuits, active filters, synthetic inductors, voltage-mode current-mode circuits. He is the author or co-author of about 4 papers published in scientific journals or conference proceedings Oguzhan Cicekogluwas born in 1963 in Istanbul, Turkey. He received the B.Sc. and M.Sc. degrees from Bogazici University and the Ph.D. degree from Istanbul Technical University all in Electrical and Electronics Engineering in 1985, 1988 and 1996 respectively. He served as lecturer at the School of Advanced Vocational Studies Electronics Prog. of Bogazici University where he held various administrative positions between 1993 and 1999, and as part time lecturer at various institutions. He was with Biomedical Engineering Institute between 1999 and 2001. He is currently Associate Professor at the Electrical and Electronics Engineering Department of Bogazici University. His current research interests include analog circuits, active filters, analog signal processing applications and current-mode circuits. He is the author or co-author of about 150 papers published in scientific journals or conference proceedings. Oguzhan Cicekoglu is a member of the IEEE.     

Resource management of IP-enabled DVB-T networks in the context of wireless B3G systems

The wireless beyond 3G systems or the so called Composite Radio Environments (CRE) (or even 4G systems), consist of multiple type radio access technologies, collaborating with each other, providing both diverse access alternatives and QoS improvement, especially as far as concerns protection against traffic congestion and loss of radio coverage situations. The merits deriving from beyond 3G systems interest not only network and service providers but also the mobile users. Additionally, the need of broadband wireless access is directly associated with the intense demand for IP multimedia services (e.g. video streaming or high speed web browsing), mainly inside hot-spot areas. Taking into consideration the above described tendency in the area of wireless network systems, the IP-enabled DVB-T (the terrestrial specification of the Digital Video Broadcasting family) systems appear as an attractive alternative network access in the CRE context. Along this direction, this paper presents the most important aspects of a CRE network management system (NMS), focusing on the component responsible for the DVB-T resource management (RM). Finally, we implement and investigate through simulation a greedy algorithm suitable for DVB-T networks that performs fast resource management and configuration. We also provide some indicative results which prove that the algorithm demonstrates a close to optimal performance at the RM functionality. This work is partially funded by the Commission of the European Communities, under the Fifth Framework Program, within the IST project CREDO (Composite Radio for Enhanced Service Delivery during the Olympics). Dimitris Kouis is currently a research associate at the Electrical Engineers School of the National Technical University of Athens, in Greece. He received his diploma from the Computer Engineering and Informatics department of the Polytechnic School of the University of Patras and a Ph.D. degree in Telecommunications and Computing from the National Technical University of Athens, Greece, in 1999 and 2005 respectively. He has worked in research projects in the context of the IST framework. His research interests include mobile and wireless networking, wireless network resources optimization techniques and large-scale software platforms. He is a member of the Technical Chamber of Greece since 1999. Panagiotis Demestichas received the Diploma and the Ph.D. degrees in Electrical and Computer Engineering from the National Technical University of Athens (NTUA). From September 2002 he is an Assistant Professor at the University of Piraeus, in the department of Technology Education and Digital Systems. From 1993 until August 2002 he has been a senior research engineer with the Telecommunications Laboratory in NTUA. From February 2001 until August 2002 he was a lecturer at NTUA, in the department of Applied Mathematics and Physics, teaching courses on programming languages, data structures, data bases, telecommunications. From September 2000 until August 2002 he taught telecommunication courses, in the department of Electronics of the Technological Education Institute of Piraeus. Most of his current activities focus on the FP6/IST project E2R (End-to-End Reconfigurability). He is also the chairman of Working Group 6 (WG6), titled Reconfigurability, of the Wireless Word Research Forum (WWRF). At the international level he has actively participated in the projects IST MONASIDRE Management of Networks and Services in a Diversified Radio Environment), where he was the project manager, as well as other EU projects under the IST, ACTS, RACE II, EURET, BRITE/EURAM frameworks. His research interests include the design, management and performance evaluation of mobile and broadband networks, service and software engineering, algorithms and complexity theory, and queueing theory. He has authored over 100 publications in these areas in international journals and refereed conferences. He is a member of the IEEE, ACM and the Technical Chamber of Greece. George Koundourakis was born in Alex/polis, Greece, in 1979. He received the degree of Electrical and Computer Engineer from the National Technical University of Athens (NTUA), Greece, in July 2001. He is a Research Associate and PhD candidate at the Telecommunications Laboratory of the Division of Communication, Electronic and Information Engineering at NTUA. He has worked in research projects in the context of the IST framework. He is the author of several scientific papers in the areas of mobile communications. He is a member of the Technical Chamber of Greece. Michael E. Theologou received the degree in Electrical Engineering from Patras University and his Ph.D. degree from the School of Electrical Engineering and Computer Science of the National Technical University of Athens (NTUA). Currently he is a Professor in the School of Electrical Engineering and Computer Science of NTUA. His research interests are in the field of Mobile and Personal communications. He has many publications in the above areas. Dr Theologou is a member of IEEE and the Technical Chamber of Greece.     

Single DDCC Biquads with High Input Impedance and Minimum Number of Passive Elements

Two new configurations for the design of biquad filters with high input impedance are presented. The first configuration can synthesize low-pass and high-pass filter functions according to the passive components used. The second one can synthesize a band-pass filter function. The proposed configurations employ only one differential difference current conveyor (DDCC) as active elements and minimum number of passive elements, namely two resistors and two capacitors. Another filter topology based on DDCC is presented that allows modifying the quality factor without changing its natural frequency. All the filters enjoy low sensitivities. SPICE simulation results are given to confirm the validity of the analysis and to point out the high performance of the filters.Muhammed A. Ibrahim was born in Erbil, Iraq in 1969. He obtained his B.Sc. and M.Sc. degrees from Salahaddin University, Erbil, Iraq and Istanbul Technical University, Istanbul, Turkey in 1990 and 1999, respectively, all in electronics and communication engineering. Between 1992 and 1996 he worked as Research Assistant at Salahaddin University where he was later appointed as Assistant Lecturer in 1999. Since 2000 he has been studying for his Ph.D. degree in Electronics and Communication Engineering Program at Istanbul Technical University. His main research interests are CMOS circuit design, current-mode circuits and analog signal processing applications. He has more than 20 international journal and conference papers in scientific review.H. Hakan Kuntman received his B.Sc., M.Sc. and Ph.D. degrees from Istanbul Technical University in 1974, 1977 and 1982, respectively. In 1974 he joined the Electronics and Communication Engineering Department of Istanbul Technical University. Since 1993 he is a professor of electronics in the same department. His research interest include design of electronic circuits, modeling of electron devices and electronic systems, active filters, design of analog IC topologies. Dr. Kuntman has authored many publications on modelling and simulation of electron devices and electronic circuits for computer-aided design, analog VLSI design and active circuit design. He is the author or the coauthor of 76 journal papers published or accepted for publishing in international journals, 91 conference papers presented or accepted for presentation in international conferences, 99 turkish conference papers presented in national conferences and 10 books related to the above mentioned areas. Furthermore he advised and completed the work of 7 Ph.D. students and 31 M.Sc. students. Currently, he acts as the head of the Electronics and Communication Engineering Department in Istanbul Technical University. Dr. Kuntman is a member of the Chamber of Turkish Electrical Engineers (EMO).Oguzhan Cicekoglu received the B.Sc. and M.Sc. degrees from Bogazici University and the Ph.D. degree from Istanbul Technical University all in Electrical and Electronics Engineering in 1985, 1988 and 1996 respectively. He served as lecturer at the School of Advanced Vocational Studies Electronics Prog. of Bogazici University where he held various administrative positions between 1993 and 1999. He served also as part time lecturer at various institutions. He was with the Biomedical Engineering Institute of the Bogazici University between 1999 and 2001. He is currently Associate Professor at the Electrical and Electronics Engineering Department of the same University.His current research interests include analog circuits, active filters, analog signal processing applications and current-mode circuits. Oguzhan Cicekoglu is the author or co-author of 62 journal papers and about 90 international or local conference papers published or accepted for publishing in journals or conference proceedings.He served as the committee member in various scientific conferences and as reviewer in numerous journals including Analog Integrated Circuits and Signal Processing, IEEE CAS-I, IEEE CAS-II, International Journal of Electronics, Microelectronics Journal, Solid State Electronics and IEE Proceedings Pt.G.Oguzhan Cicekoglu is a member of the IEEE.     

New 1.5-V CMOS second generation current conveyor based on wide range transconductor

This paper presents a novel CMOS low-voltage and low-power positive second-generation current conveyor (CCII+). The proposed CCII+ uses two n-channel differential pairs instead of the complementary differential pairs; i.e. (n-channel and p-channel), to realize the input stage. This solution allows almost a rail-to-rail input and output operation; also it reduces the number of current mirrors needed in the input stage. The CCII+ is operating at supply voltages of ±0.75 V with a total standby current of 133 μA. The application of the proposed CCII+ to realize a MOS-C second order maximally flat low-pass filter is given. PSpice simulation results for the proposed CCII+ and its application are given. Ahmed H. Madian was born in Jeddah, Saudi Arabia in 1975. He received the B.Sc. degree with honors, and the M.Sc. degree in electronics and communications from Cairo University, Cairo, Egypt, in 1997, and 2001 respectively. He is currently a Research Assistant in the Electronics Engineering Department, Micro-Electronics Design Center, Egyptian Atomic Energy Authority, Cairo, Egypt. His research interests are in circuit theory; low-voltage analog CMOS circuit design, current-mode analog signal processing, and mixed/digital applications on filed programmable gate arrays. Soliman A. Mahmoud was born in Cairo, Egypt, in 1971. He received the BSc degree with honors in 1994, the MSc degree in 1996, and the PhD degree in 1999, all from the Electronics and Communications Department, Cairo University, Egypt. He is currently an Associate Professor at the Electrical Engineering Department, Fayoum University, Egypt. He is currently also a visiting Associate Professor at the Electrical and Electronics Engineering Department, German University in Cairo, Egypt. In 2005, He was decorated with the Science Prize in Advanced Engineering Technology from the Academy of Scientific Research and technology. His research and teaching interests are in circuit theory, fully-integrated analog filters, high-frequency transconductance amplifiers, low-voltage analog CMOS circuit design, current-mode analog signal processing, and mixed analog/digital programmable analog blocks. Ahmed M. Soliman was born in Cairo Egypt, on November 22, 1943. He received the B.Sc. degree with honors from Cairo University, Cairo, Egypt, in 1964,the M.S. and Ph.D. degrees from the University of Pittsburgh, Pittsburgh, PA., U.S.A., in 1967 and 1970, respectively, all in Electrical Engineering. He is currently Professor Electronics and Communications Engineering Department, Cairo University, Egypt. From September 1997-September 2003, Dr Soliman served as Professor and Chairman Electronics and Communications Engineering Department, Cairo University, Egypt. From 1985-1987, Dr. Soliman served as Professor and Chairman of the Electrical Engineering Department, United Arab Emirates University, and from 1987-1991 he was the Associate Dean of Engineering at the same University. He has held visiting academic appointments at San Francisco State University, Florida Atlantic University and the American University in Cairo.He was a visiting scholar at Bochum University, Germany (Summer 1985) and with the Technical University of Wien, Austria (Summer 1987). In November 2005, Dr Soliman gave a lecture at Nanyang Technological University, Singapore.Dr Soliman was also invited to visit Taiwan and gave lectures at Chung Yuan Christian University and at National Central University of Taiwan. In 1977, Dr. Soliman was decorated with the First Class Science Medal, from the President of Egypt, for his services to the field of Engineering and Engineering Education. Dr Soliman is a Member of the Editorial Board of the IEE Proceedings Circuits, Devices and Systems. Dr Soliman is a Member of the Editorial Board of Analog Integrated Circuits and Signal Processing. Dr Soliman served as Associate Editor of the IEEE Transactions on Circuits and Systems I (Analog Circuits and Filters) from December 2001 to December 2003 and is Associate Editor of the Journal of Circuits, Systems and Signal Processing from January 2004-Now.     

New Four-Quadrant CMOS Current-Mode and Voltage-Mode Multipliers

In this paper, a four-quadrant current-mode multiplier based on a new squarer cell is proposed. The multiplier has a simple core, wide input current range with low power consumption, and it can easily be converted to a voltage-mode by using a balanced output transconductor (BOTA) [1]. The proposed four-quadrant current-mode and voltage-mode multipliers were confirmed by using PSPICE simulation and found to have good linearity with wide input dynamic range. For the proposed current-mode multiplier, the static power consumption is 0.671 mW, the maximum power consumption is 0.72 mW, the input current range is ± 60 μ A, the bandwidth is 31 MHz, the input referred noise current is 46 pA/√Hz, and the maximum linearity error is 3.9%. For the proposed voltage-mode multiplier, the static power consumption is 1.6 mW, the maximum power consumption is 1.85 mW, the input voltage range is ± 1V from ± 1.5V supply, the bandwidth is 25.34 MHz, the input referred noise voltage is 0.85 μV/√Hz, and the maximum linearity error is 4.1%. Mohammed A. Hashiesh was born in Elkharga, New Valley, Egypt, in 1979. He received the B.Sc. degree with honors from the Electrical Engineering Department, Cairo University, Fayoum-Campus, Egypt in 2001, and he received the M.Sc. degree in 2004 from the Electronics and Communication Engineering Department, Cairo University, Egypt. He is currently a Teacher Assistant at the Electrical Engineering Department, Cairo University, Fayoum-Campus. His research interests include analog CMOS integrated circuit design and signal processing, and digitally programmable CMOS analog building blocks. Soliman A. Mahmoud was born in Cairo, Egypt, in 1971. He received the B.Sc. degree with honors, the M.Sc. degree and the Ph.D. degree from the Electronics and Communications Department, Cairo University—Egypt in 1994, 1996 and 1999 respectively. He is currently an Assistant Professor at the Electrical Engineering Department, Cairo University, Fayoum-Campus. He has published more than 50 papers. His research and teaching interests are in circuit theory, fully integrated analog filters, high frequency transconductance amplifiers, low voltage analog CMOS circuit design, current-mode analog signal processing and mixed analog/digital programmable analog blocks. Ahmed M. Soliman was born in Cairo Egypt, on November 22, 1943. He received the B.Sc. degree with honors from Cairo University, Cairo, Egypt, in 1964, the M.S. and Ph.D. degrees from the University of Pittsburgh, Pittsburgh, PA., U.S.A., in 1967 and 1970, respectively, all in Electrical Engineering. He is currently Professor Electronics and Communications Engineering Department, Cairo University, Egypt. From September 1997–September 2003, Dr Soliman served as Professor and Chairman Electronics and Communications Engineering Department, Cairo University, Egypt. From 1985–1987, Dr. Soliman served as Professor and Chairman of the Electrical Engineering Department, United Arab Emirates University, and from 1987–1991 he was the Associate Dean of Engineering at the same University. He has held visiting academic appointments at San Francisco State University, Florida Atlantic University and the American University in Cairo. He was a visiting scholar at Bochum University, Germany (Summer 1985) and with the Technical University of Wien, Austria (Summer 1987). In 1977, Dr. Soliman was decorated with the First Class Science Medal, from the President of Egypt, for his services to the field of Engineering and Engineering Education. Dr Soliman is a member of the Editorial Board of Analog Integrated Circuits and Signal Processing. Presently Dr. Soliman is Associate Editor of the IEEE Transactions on Circuits and Systems I (Analog Circuits and Filters).     

Packet Error Rate Distribution Between Random Bluetooth Piconet Pairs

The packet error rate between two piconets depends on the temporal alignment of their packets and the spectral alignment of the intervals from which the frequencies in their hop sequence are chosen. The relationship between two randomly paired piconets is one of over 828 billion possible relationships. We define these relationships and derive an expression for determining the packet error rate for a specific pair of piconets using single-slot packets. We derive the probability mass function for the packet error rate and extend it to provide the possible packet error rates for an arbitrary number of neighboring piconets. We also derive a probability mass function for the goodput of a piconet with a neighboring piconet. The probability mass functions for the packet error rate is bimodal, meaning the expected value of the goodput or packet error rate is not a good choice for piconet performance analysis. Brian S. Peterson is Chief of the Advanced MASINT Research and Requirements Branch at the National Air and Space Intelligence Center, Wright-Patterson AFB, Ohio. He received the B.S.E.E degree in 1991 from the United States Air Force Academy, an M.S. degree in Systems Engineering in 1995 from, and an M.S.E.E. degree from Florida State University in 1998. He received his Ph.D. degree in Electrical Engineering in 2005 from the Air Force Institute of Technology. Dr. Peterson's research interests include computer communication protocols and wireless networking. Dr. Peterson is a member of the IEEE. Rusty O. Baldwin is an Associate Professor of Computer Engineering in the Department of Electrical and Computer Engineering at the Air Force Institute of Technology, Wright-Patterson AFB, Ohio. He received the B.S.E.E degree (with honors) in 1987 from the New Mexico State University and the M.S. degree in Computer Engineering in 1992 from AFIT. He received his Ph.D. degree in Electrical Engineering in 1999 from Virginia Polytechnic Institute and State University. Dr. Baldwin's research interests include computer communication protocols, information warfare, and wireless networking. Dr. Baldwin is a Senior member of the IEEE. Richard A. Raines is an Associate Professor of Electrical Engineering in the Department of Electrical and Computer Engineering at the Air Force Institute of Technology (AFIT), Wright-Patterson AFB, Ohio. He received the B.S.E.E degree (with honors) in 1985 from the Florida State University and the M.S. degree in Computer Engineering in 1987 from AFIT. He received his Ph.D. degree in Electrical Engineering in 1994 from Virginia Polytechnic Institute and State University. Dr. Raines' research interests include computer communication protocols, information security, and wireless networking. Dr. Raines is a Senior member of the IEEE.     

Design and implementation of an optimised wireless pressure sensor for biomedical application

This paper presents design and implementation of a wireless pressure sensor system for biomedical application. The system consists of a front-end Micro-Electro- Mechanical System (MEMS) sensing capacitor along with an optimised MEMS-based oscillator for signal conditioning circuit. In this design, vertical fringed comb capacitor is employed due to the advantages of smaller area, higher linearity and larger full scale change in capacitance compared to parallel plate counterparts. The MEMS components are designed in Coventorware design suite and their Verilog-A models are extracted and then imported to Cadence for co-simulation with the CMOS section of the system using AMI 0.6-micron CMOS process. In this paper, an optimisation method to significantly reduce the system power consumption while maintaining the system performance sufficient is also proposed. A phase noise optimisation approach is based on the algorithm to limit the oscillator tail current. Results show that for the pressure range of 0–300 mmHg the device capacitance range of 1.31 pF – 1.98 pF is achieved which results in a frequency sweep of 2.54 GHz – 1.95 GHz. Results also indicate that a 42% reduction of power consumption is achieved when the optimisation algorithm is applied. This characteristic makes the sensor system a better candidate for wireless biomedical applications where power consumption is the major factor. Hai Phuong Le received his B.E. (Hons) degree in Electronic and Computer System Engineering from University of Tasmania, Hobart, Australia in 2000. He received his Ph.D. degree in Microelectronics from Victoria University, Melbourne, Australia in 2005. At present, he is a post-doctoral research fellow and lecturer in the Centre for Telecommunications and Microelectronics, Victoria University. His research and teaching interests include data acquisition system, mixed-signal integrated circuit design and wireless smart sensor systems. Kriyang Shah received his B.E. Degree in Electronics and Communication Engineering from Sardar Patel University, Vallabh Vidyanagar, Gujarat, India and his Master Degree in Microelectronics in 2004. He is currently a Ph.D. research student in the Centre for Telecommunications and Microelectronics, Victoria University, Melbourne, Australia. His research interests include MEMS Sensors, RF MEMS, process integration for MEMS and CMOS and MEMS-CMOS co-simulation. Jugdutt (Jack) Singh received his B.Sc. in Electronics Engineering from University of Brighton, UK and M.Sc. in Electronics Engineering from University of Alberta, Canada in 1978 and 1986 respectively. He completed his Ph.D. at Victoria University, Australia in 1997. Since 1989 he has been at Victoria University, Melbourne, Australia. Currently he is a Professor of Microelectronics in the Centre for Telecommunications and Microelectronics at Victoria University. His major area of research interests are in the RF, analog and mixed signal design, reconfigurable architectures, low power VLSI circuits and systems design. He has published number of articles in education and research in microelectronics and small technologies area. Aladin Zayegh received his B.E. degree in Electrical Engineering from Aleppo University in 1970 and Ph.D. degree from Claude Bernard University, France in 1979. In 1980, he joined the Faculty of Engineering, Tripoli, Libya. Since 1984 he has held lecturing position at Victoria University, Melbourne, Australia. He is currently an Associate Professor and the Head of School in the School of Electrical Engineering, Faculty of Health, Engineering and Engineering and Science at Victoria University. His research interest includes microprocessor-based system, instrumentation, data acquisition and interfacing, and microelectronics.     

Set of Sequences for QS-CDMA Systems with Multi-User Detection and Multipath-Fading Channels

In this work Walsh–Hadamard, QS, Lin–Chang, LCZ-GMW, ZCZ sets of sequences are compared. The comparison is accomplished by analyzing the conventional receiver (Rake) and a parallel interference canceller (PIC) receiver performance using each one of these sequence sets in a multipath Rayleigh fading channel and similar system loads in quasi-synchronous condition.André Seichi Ribeiro Kuramoto received the B.S. degree in Electrical Engineering from UEL, Londrina State University (Brazil) in 2002. He is currently an M.Sc. student at EPUSP – Escola Politécnica of University of São Paulo (Brazil) and his current research interests are quasi-synchronous DS-CDMA systems and code sequences analysis.Taufik Abrão received the B.S., M.Sc. and Ph.D., all in Electrical Engineering from EPUSP – Escola Politécnica of University São Paulo (Brazil), in 1992, 1996, and 2001, respectively. He is currently an Adjunct Professor at the Electrical Engineering Department of UEL, State University of Londrina (Brazil) and his current research interests are CDMA systems, multi-user detection, and code sequences analysis.Paul Jean Etienne Jeszensky received the B.S., M.S. and Ph.D., all in Electrical Engineering from EPUSP – Escola Politécnica of University of São Paulo (Brazil), in 1972, 1981, and 1989, respectively. Since 1990, he has been with EPUSP where he is a full-time Associate Professor and Researcher in Communication Systems. He was visiting professor at UPC – Universitat Politécnica de Catalunya, Barcelona (Spain) in 1995 and at TUB – Technical University of Budapest (Hungary) in 2001. He is author of the book Sistemas Telefônicos (in Portuguese), Editora Manole, 2003, and his current research interests include CDMA systems, multi-user detection, code sequences analysis and related topics.     

Integrated Circuit Implementation of a Compact Discrete-Time Chaos Generator

A discrete-time chaos generator implemented with two nonlinear circuit cells has been fabricated in a 0.6 μm CMOS technology. Each cell is creating a function (map) which allows a chaos signal to be generated. Measurements of the chip were performed with a supply voltage of 5 V, up to a frequency of 2.5 MHz. A bifurcation diagram of the circuit and the Lyapunov exponent calculation are presented. The size of the generator layout (without the switches) is 32 × 19 μ m which makes it suitable for applications where many chaos signal generators are required on a single chip. Dan Juncu received the B.S. and M.Sc. degrees in Electrical and Electronics Engineering from the Technical University, Iasi, Romania in 1997 and 1998, respectively, and the Ph.D. degree in Electronics from UMIST, Manchester, UK in 2003. For his Ph.D. he did research on sensor interfaces for gas sensing devices; after that, he worked on RF IC on a new SiGe technology. In 2004 he joined Cambridge Consultants, Cambridge, UK. His current interests are in the area of switched capacitor filtering and computation, and sensor interfacing. Mandana Rafiei-Naeini received the B.Sc. degree in Electrical Engineering (majoring in Electronics) from Islamic Azad University of Tehran, Iran, in 2001 and the M.Sc. degree with distinction in Electronic Instrumentation Systems from University of Manchester in 2004. She is currently studying towards her Ph.D. degree in the School of Electrical and Electronic Engineering at The University of Manchester, working on clinical electrical impedance tomography systems for brain function imaging. She is a student member of IEE and IEEE. Piotr Dudek received his mgr in ż degree in electronic engineering from the Technical University of Gdańsk, Poland in 1997 and the M.Sc. and Ph.D. degrees from the University of Manchester Institute of Science and Technology (UMIST), Manchester, UK, in 1996 and 2000, respectively. He worked as a Research Associate at UMIST until 2002. Currently, he is a Lecturer in Integrated Circuit Engineering at The University of Manchester. His research interests are in analogue and mixed-mode VLSI circuits, smart sensors, machine vision, massively parallel processors, cellular arrays, bio-inspired engineering and spiking neural networks.     

Reconfigurable Discrete Wavelet Transform Processor for Heterogeneous Reconfigurable Multimedia Systems

In this paper, a novel reconfigurable discrete wavelet transform processor architecture is proposed to meet the diverse computing requirements of future generation multimedia SoC. The proposed architecture mainly consists of reconfigurable processing element array and reconfigurable address generator, featuring dynamically reconfigurable capability where the wavelet filters and wavelet decomposition structures can be reconfigured as desired at run-time. The lifting-based reconfigurable processing element array possesses better computation efficiency than convolution-based architectures, and a systematic design method is provided to generate the hardware configurations of different wavelet filters for it. The reconfigurable address generator handles flexible address generation for data I/O access in different wavelet decomposition structures. A prototyping chip has been fabricated by TSMC 0.35 μm 1P4M CMOS process. At 50 MHz, this chip can achieve at most 100 M pixels/sec transform throughput, together with energy efficiency and unique reconfigurability features, proving it to be a universal and extremely flexible computing engine for heterogeneous reconfigurable multimedia systems.Po-Chih Tseng was born in Tao-Yuan, Taiwan in 1977. He received the B.S. degree in Electrical and Control Engineering from National Chiao Tung University in 1999 and the M.S. degree in Electrical Engineering from National Taiwan University in 2001. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University. His research interests include VLSI design and implementation for signal processing systems, energy-efficient reconfigurable computing for multimedia systems, and power-aware image and video coding systems.Chao-Tsung Huang was born in Kaohsiung, Taiwan, R.O.C., in 1979. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 2001. He currently is working toward the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include VLSI design and implementation for signal processing systems.Liang-Gee Chen (S’84–M’86–SM’94–F’01) received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1979, 1981, and 1986, respectively. In 1988, he joined the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. During 1993–1994, he was a Visiting Consultant in the DSP Research Department, AT&T Bell Labs, Murray Hill, NJ. In 1997, he was a Visiting Scholar of the Department of Electrical Engineering, University of Washington, Seattle. Currently, he is Professor at National Taiwan University, Taipei, Taiwan, R.O.C. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY since 1996, as Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS since 1999, and as Associate Editor of IEEE TRANSACTIONS CIRCUITS AND SYSTEMS II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of VLSI Signal Processing Systems. He is also the Associate Editor of the PROCEEDINGS OF THE IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001–2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

Channel Estimation by Using Short Training Sequences in CDMA Systems

Multiuser detection techniques are known to be effective to counter the presence of multiuser interference in code division multiple access channels. Multiuser detectors can provide excellent performance only when the channel impulse responses of all the users are precisely known. Hence, channel estimation becomes a challenging issue in mobile communication systems. In this paper, we address the problem of efficient maximum likelihood mobile radio channel estimation at high channel efficiency that requires a short training sequence along with the known spreading sequence. The proposed system can be employed in both the uplink and downlink of a heavily loaded multiuser CDMA system. The extension of the approach with unknown users' delays are also proposed. We present results that show the success of this method in recovering the transmitted bits with a relatively small number of preamble bits. Ahmet Rizaner was born in Larnaca, Cyprus, on January 31, 1974. He received the B.S. and M.S. degrees in Electrical and Electronics Engineering from the Eastern Mediterranean University, Famagusta, North Cyprus, in 1996 and 1998, respectively. He completed his PhD. degree in Electrical and Electronic Engineering in Eastern Mediterranean University and joined Eastern Mediterranean University as a lecturer in 2004. He is lecturing in the School of Computing and Technology. His main research interests include CDMA communications, adaptive channel estimation, and multiuser detection techniques. Hasan Amca was born in 1961 in Nicosia-Cyprus. He graduated from the Higher Technological Institute in Magosa-Cyprus (which is renamed later as Eastern Mediterranean University). He joined EMU in 1985 after receiving a M.Sc. (Digital Signal Processing) degree from the University of Essex in England (1985). He took his Ph.D. (Mobile Communications) from the University of Bradford where he was on a Commonwealth scholarship. He has been teaching in the Electrical and Electronic Engineering Department of Eastern Mediterranean University since 1993 where he also served as the vice chairman from Spring 1998 to Spring 2000. He has been appointed as the Director of the School of Computing and Technology of the EMU since Spring 2000. His research interests include Multi User Detection of CDMA signals, Adaptive Equalisation, Multi Carrier Systems, Mobile Radio Systems and Networks, Internet and Information Technology Applications in Education. Kadri Hacıoğlu was born in Nicosia, Cyprus. He received the B.Sc., M.Sc., and Ph.D. degrees in electrical and electronic engineering from the Middle East Technical University, Ankara, Turkey, in 1980, 1984, and 1990, respectively. After his two-year military service, in 1992, he joined the faculty of Eastern Mediterranean University, Magosa, North Cyprus, as an Assistant Professor, and became an Associate Professor in 1997. While there, he taught several classes on electronics, digital communications, speech processing and neural networks. During this time, he conducted research on applying fuzzy logic, neural networks, and genetic algorithms to signal processing and communications problems. From 1998 to 2000, he was a Visiting Professor in the Department of Computer Science, University of Colorado, Boulder. Here, he taught classes on neural networks and continued his research. Since 2000, he has been a Research Associate at the Center for Spoken Language Research, University of Colorado. He has authored or coauthored numerous papers and supervised a dozen M.Sc./Ph.D. theses. His current research interests are concept-based language modeling, speech understanding, natural language generation, and search methods in speech recognition/understanding. He also does research on multiuser detection and equalization in CDMA systems. Ali Hakan Ulusoy was born in Eskişehir, Turkey, on June 3, 1974. He graduated from the double major program of the department of Electrical and Electronic Engineering and department of Physics in Eastern Mediterranean University as the first rank student of Faculty of Engineering in 1996. He received his M.S. degree in Electrical and Electronic Engineering in Eastern Mediterranean University in 1998. He completed his PhD. degree in Electrical and Electronic Engineering in Eastern Mediterranean University and joined Eastern Mediterranean University as a lecturer in 2004. He is lecturing in the School of Computing and Technology. His current research interests include receiver design, multi-user detection techniques, blind and trained channel estimation in Code Division Multiple Access (CDMA).     

VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization

Based on B-spline factorization, a new category of architectures for Discrete Wavelet Transform (DWT) is proposed in this paper. The B-spline factorization mainly consists of the B-spline part and the distributed part. The former is proposed to be constructed by use of the direct implementation or Pascal implementation. And the latter is the part introducing multipliers and can be implemented with the Type-I or Type-II polyphase decomposition. Since the degree of the distributed part is usually designed as small as possible, the proposed architectures could use fewer multipliers than previous arts, but more adders would be required. However, many adders can be implemented with smaller area and lower speed because only few adders are on the critical path. Three case studies, including the JPEG2000 default (9, 7) filter, the (6, 10) filter, and the (10, 18) filter, are given to demonstrate the efficiency of the proposed architectures.Chao-Tsung Huang was born in Kaohsiung, Taiwan, R.O.C., in 1979. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 2001. He currently is working toward the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include VLSI design and implementation for signal processing systems.Po-Chih Tseng was born in Tao-Yuan, Taiwan in 1977. He received the B.S. degree in Electrical and Control Engineering from National Chiao Tung University in 1999 and the M.S. degree in Electrical Engineering from National Taiwan University in 2001. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University. His research interests include VLSI design and implementation for signal processing systems, energy-efficient reconfigurable computing for multimedia systems, and power-aware image and video coding systems.Liang-Gee Chen received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1979, 1981, and 1986, respectively.In 1988, he joined the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. During 1993–1994, he was a Visiting Consultant in the DSP Research Department, AT&T Bell Labs, Murray Hill, NJ. In 1997, he was a Visiting Scholar of the Department of Electrical Engineering, University of Washington, Seattle. Currently, he is Professor at National Taiwan University, Taipei, Taiwan, R.O.C. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY since 1996, as Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS since 1999, and as Associate Editor of IEEE TRANSACTIONS CIRCUITS AND SYSTEMS II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the PROCEEDINGS OF THE IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications, During 2001-2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

Training Sequence Aided Signature Waveform Estimation

In code division multiple access channels multiuser detection techniques are known to be effective strategies to counter the presence of multiuser interference towards improving spectral efficiency. Generally, multiuser detectors can provide excellent performance only when the signature waveforms of all users are precisely known. Hence, the estimation of signature waveforms is a challenging issue in mobile communication systems. In this paper, we compare the performance of two short training sequence aided signature waveform estimators. One is maximum likelihood type signature waveform estimator that requires the knowledge of spreading sequences and short training sequences. The other estimator is recently proposed based on subspace method and requires the knowledge of training sequences only. Through the simulations, we show the signature waveform estimation performance of both systems and the effect of the estimation error on the performance of a multiuser detector. The complexity comparisons of both systems are also given. We use the term “signature waveform” to refer to the convolution of the channel and the spreading code throughout the paper. Hasan AMCA was born in 1961 in Nicosia-Cyprus. He graduated from the Higher Technological Institute in Magosa – Cyprus (which is renamed later as Eastern Mediterranean University). He joined EMU in 1985 after receiving a M.Sc. (Digital Signal Processing) degree from the University of Essex in England (1985). He took his Ph.D. (Mobile Communications) from the University of Bradford where he was on a Commonwealth scholarship. He has been teaching in the Electrical and Electronic Engineering Department of Eastern Mediterranean University since 1993 where he also served as the Vice Chairman from Spring 1998 to Spring 2000. He has been appointed as the Director of the School of Computing and Technology of the EMU since Spring 2000. His research interests include Multi User Detection of CDMA signals, Adaptive Equalisation, Multi Carrier Systems, Mobile Radio Systems and Networks, Internet and Information Technology Applications in Education. Ahmet Rizaner was born in Larnaca, Cyprus, on January 31, 1974. He received the B.S. and M.S. degrees in Electrical and Electronics Engineering from the Eastern Mediterranean University, Famagusta, North Cyprus, in 1996 and 1998, respectively. He completed his PhD. degree in Electrical and Electronic Engineering in Eastern Mediterranean University and joined Eastern Mediterranean University as a lecturer in 2004. He is lecturing in the School of Computing and Technology. His main research interests include CDMA communications, adaptive channel estimation, and multiuser detection technique. Kadri Hacioğlu was born in Nicosia, Cyprus. He received the B.Sc., M.Sc., and Ph.D. degrees in electrical and electronic engineering from the Middle East Technical University, Ankara, Turkey, in 1980, 1984, and 1990, respectively. After his two-year military service, in 1992, he joined the faculty of Eastern Mediterranean University, Magosa, North Cyprus, as an Assistant Professor, and became an Associate Professor in 1997. While there, he taught several classes on electronics, digital communications, speech processing and neural networks. During this time, he conducted research on applying fuzzy logic, neural networks, and genetic algorithms to signal processing and communications problems. From 1998 to 2000, he was a Visiting Professor in the Department of Computer Science, University of Colorado, Boulder. Here, he taught classes on neural networks and continued his research. Since 2000, he has been a Research Associate at the Center for Spoken Language Research, University of Colorado. He has authored or coauthored numerous papers and supervised a dozen M.Sc./Ph.D. theses. His current research interests are concept-based language modeling, speech understanding, natural language generation, and search methods in speech recognition/understanding. He also does research on multiuser detection and equalization in CDMA systems. Ali Hakan Ulusoy was born in Eskişehir, Turkey, on June 3, 1974. He graduated from the double major program of the department of Electrical and Electronic Engineering and department of Physics in Eastern Mediterranean University as the first rank student of Faculty of Engineering in 1996. He received his M.S. degree in Electrical and Electronic Engineering in Eastern Mediterranean University in 1998. He completed his Ph.D. degree in Electrical and Electronic Engineering in Eastern Mediterranean University and joined Eastern Mediterranean University as a lecturer in 2004. He is lecturing in the School of Computing and Technology. His current research interests include receiver design, multi-user detection techniques, blind and trained channel estimation in Code Division Multiple Access (CDMA).     

An Efficient Dictionary Organization for Maximum Diagnosis

The major problem of fault diagnosis with a fault dictionary is the enormous amount of data. The technique used to manage this data can have a significant effect on the outcome of the fault diagnosis procedure. If information is removed from a fault dictionary in order to reduce the size of the dictionary, its ability to diagnose stuck-at faults and unmodeled faults may be severely debased. Therefore, we focus on methods for producing a dictionary that is both small and lossless-compacted. We propose an efficient dictionary for maximum diagnosis, which is called SD-Dictionary. This dictionary consists of a static sub-dictionary and a dynamic sub-dictionary in order to make a smaller dictionary while maintaining the critical information needed for the diagnostic ability. Experimental results on ISCAS’ 85, ISCAS’ 89 and ITC’ 99 benchmark circuits show that the size of the proposed dictionary is substantially reduced, while the dictionary retains most or all of the diagnostic capability of the full dictionary. This work was supported by the “System IC 2010” project of Korea Ministry of Science and Technology and Ministry of Commerce, Industry and Energy. Editor: Y. Takamatsu Sunghoon Chun received the B.S. degrees in Electrical and Electronic Engineering from Yonsei University, Seoul, Korea, in 2002. He was a Reseach Engineer with ASIC Research Center in Yonsei University. He researched for test methodologies for SoC. He received the M.S. degrees in Electrical and Electronic Engineering from Yonsei University in 2005. He is currently working toward Ph.D. degree in Electrical and Electronic Engineering at Yonsei University. His area of interests includes SoC testing, delay testing, fault diagnosis, functional testing for processor based system and test methodologies for signal integrity faults. Sangwook Kim received the B.S., and M.S. degrees in Electrical and Electronic Engineering from Yonsei University, Seoul, Korea, in 1999, and 2001, respectively. He researched for Digital Signal Processor design and fault diagnosis of VLSI. He is a Research Engineer with SoC Design Group of System IC Division in LG Electronics, Inc. He is currently interested in SoC design for HDTV and design verification. Hong-Sik Kim was born in Seoul, Korea, on April 4, 1973. He received the B.S., M.S. and Ph.D. degrees in Electrical and Electronic Engineering from Yonsei University, Seoul, Korea, in 1977, 1999, and 2004, respectively. He was a Post-Doctorial Fellow with the Institute of Virginia Technology. He is currently working on System LSI Group in the Samsung Electronics. His current research interest includes design-for-testability, built-in self tests and fault diagnosis. Sungho Kang received the B.S. degree from Seoul National University, Seoul, Korea, and the M.S. and Ph.D. degrees in electrical and computer engineering from The University of Texas at Austin. He was a Post-Doctorial Fellow with the University of Texas at Austin, a Research Scientist with the Schlumberger Laboratory for Computer Science, Schlumberger Inc., and a Senior Staff Engineer with the Semiconductor Systems Design Technology, Motorola Inc. Since 1994, he has been an Associate Professor with the Department of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea. His current research interests include VLSI design, VLSI CAD and VLSI testing and design for testability.     

Reduced-Complexity Iterative Multiuser Detection for DS-CDMA

A reduced-complexity iterative multiuser detection scheme is proposed. The scheme involves a simple way of choosing only K + 1 user bit vectors instead of the full-complexity 2^K for the likelihood computation, thus reducing the complexity to O(K). An alternative, reduced computation method of increasing this list of vectors after each iteration is also presented. Simulations over AWGN, imperfect power control and multipath conditions demonstrate that the performance of the proposed reduced-complexity method is close to that of the full-complexity.Ju Yan Pan received the B.S.E.E. degree from Mississippi State University, U.S.A., in 1998 and the M.Eng. degree from Nanyang Technological University, Singapore, in 2002. He is currently working as a system design engineer at the wireless communication technology department of Oki Techno Centre Pte. Ltd. in Singapore Science Park II. His current reserach interests include third-generation WCDMA systems, turbo decoding and multiuser detection.Cheong Boon Soh received the Bachelor of Engineering in Electrical and Computer Systems Engineering (Hons I) and Ph.D. degrees from Monash University, Victoria, Australia, in 1983 and 1987, respectively. He is an Associate Professor in the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore. He has published more than one hundred international journal papers. His current research interests are robust control, system theory, nonlinear systems, coding theory, mobile communication systems and intelligent systems.Gunawan Erry received his B.Sc degree in Electrical and Electronic Engineering from the University of Leeds, U.K., in 1983. He then received his MBA and Ph.D. in total technology from Bradford University in 1984 and 1988 respectively. From 1984 to 1988, he worked for Communication Systems Research Ltd, U.K. as a satellite communication systems engineer. In 1988, he moved to Space Communications (SAT-TEL) Ltd, U.K. He joined the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore in 1989. Currently, he is an Associate Professor in the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore. His current research interests are in digital communications, mobile and satellite communications, error coding and spread-spectrum. He has published over sixty international research papers and has been a consultant to a local company on the study of DECT system and Bluetooth.     

Channel Sharing Scheme for Packet-Switched Cellular Networks

In this paper, we study an approach for sharing channels to improve network utilization in packet-switched cellular networks. Our scheme exploits unused resources in neighboring cells without the need for global coordination. We formulate a minimax approach to optimizing the allocation of channels in this sharing scheme. We develop a measurement-based distributed algorithm to achieve this objective and study its convergence. We illustrate, via simulation results, that the distributed channel sharing scheme performs significantly better than the fixed channel scheme over a wide variety of traffic conditions. This research was supported in part by the National Science Foundation through grants ECS-0098089, ANI-0099137, ANI-0207892, ANI-9805441, ANI-0099137, and ANI-0207728, and by an Indiana 21st century grant. A conference version of this paper appeared in INFOCOM 99. This work was done when all the authors were at Purdue University. Suresh Kalyanasundaram received his Bachelors degree in Electrical and Electronics Engineering and Masters degree in Physics from Birla Institute of Technology and Science, Pilani, India in 1996. He received his Ph.D. from the School of Electrical and Computer Engineering, Purdue University, in May 2000. Since then he has been with Motorola, working in the area of performance analysis of wireless networks. Junyi Li received his B.S. and M.S. degrees from Shanghai Jiao Tong University, and Ph.D. degree from Purdue University. He was with the Department of Digital Communications Research at Bell Labs, Lucent Technologies from 1998 to 2000. In 2000 as a founding member he jointed Flarion Technologies, where he is now Director of Technology. He is a senior member of IEEE. Edwin K.P. Chong received the B.E.(Hons.) degree with First Class Honors from the University of Adelaide, South Australia, in 1987; and the M.A. and Ph.D. degrees in 1989 and 1991, respectively, both from Princeton University, where he held an IBM Fellowship. He joined the School of Electrical and Computer Engineering at Purdue University in 1991, where he was named a University Faculty Scholar in 1999, and was promoted to Professor in 2001. Since August 2001, he has been a Professor of Electrical and Computer Engineering and a Professor of Mathematics at Colorado State University. His current interests are in communication networks and optimization methods. He coauthored the recent book, An Introduction to Optimization, 2nd Edition, Wiley-Interscience, 2001. He was on the editorial board of the IEEE Transactions on Automatic Control, and is currently an editor for Computer Networks. He is an IEEE Control Systems Society Distinguished Lecturer. He received the NSF CAREER Award in 1995 and the ASEE Frederick Emmons Terman Award in 1998. Ness B. Shroff received his Ph.D. degree from Columbia University, NY in 1994. He is currently an Associate Professor in the School of Electrical and Computer Engineering at Purdue University. His research interests span the areas of wireless and wireline communication networks. He is especially interested in fundamental problems in the design, performance, scheduling, capacity, pricing, and control of these networks. His research is funded by various companies such as Intel, Hewlett Packard, Nortel, AT&T, and L. G. Electronics; and government agencies such as the National Science Foundation, Indiana Dept. of Transportation, and the Indiana 21st Century fund. Dr. Shroff is an editor for IEEE/ACM Trans. on Networking and the Computer Networks Journal, and past editor of IEEE Communications Letters. He was the conference chair for the 14th Annual IEEE Computer Communications Workshop (in Estes Park, CO, October 1999) and program co-chair for the symposium on high-speed networks, Globecom 2001 (San Francisco, CA, November 2000). He is also the Technical Program co-chair for IEEE INFOCOM'03 and panel co-chair for ACM Mobicom'02. He received the NSF CAREER award in 1996.     

Hybrid Morphology Processing Unit Architecture for Moving Object Segmentation Systems

Video segmentation is a key operation in MPEG-4 content-based coding systems. For real-time applications, hardware implementation of video segmentation is inevitable. In this paper, we propose a hybrid morphology processing unit architecture for real-time moving object segmentation systems, where a prior effective moving object segmentation algorithm is implemented. The algorithm is first mapped to pixel-based operations and morphological operations, which makes the hardware implementation feasible. Then the high computation load, which is more than 4.2 GOPS, can be overcome with a dedicated morphology engine and a programmable morphology PE array. In addition, the hardware cost, memory size, and memory bandwidth can be reduced with the partial-result-reuse concept. This chip is designed with TSMC 0.35 μm 1P4M technology, and can achieve the processing speed of 30 QCIF frames or 7,680 morphological operations per second at 26 MHz. Simulation shows that the proposed hardware architecture is efficient in both hardware complexity and memory organization. It can be integrated into any content-based video processing and encoding systems. Shao-Yi Chien was born in Taipei, Taiwan, R.O.C., in 1977. He received the B.S. and Ph.D. degrees from the Department of Electrical Engineering, National Taiwan University (NTU), Taipei, in 1999 and 2003, respectively. During 2003 to 2004, he was a research staff in Quanta Research Institute, Tao Yuan Shien, Taiwan. In 2004, he joined the Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, as an Assistant Professor. His research interests include video segmentation algorithm, intelligent video coding technology, image processing, computer graphics, and associated VLSI architectures. Bing-Yu Hsieh was born in Taichung, Taiwan, in 1979. He received the B.S.E.E and M.S.E.E degrees from National Taiwan University (NTU), Taipei, in 2001 and 2003, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2003, where he develops integrated circuits related to multimedia systems and optical storage devices. His research interests include object tracking, video coding, baseband signal processing, and VLSI design. Yu-Wen Huang was born in Kaohsiung, Taiwan, in 1978. He received the B.S. degree in electrical engineering and Ph. D. degree in the Graduate Institute of Electronics Engineering from National Taiwan University (NTU), Taipei, in 2000 and 2004, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2004, where he develops integrated circuits related to video coding systems. His research interests include video segmentation, moving object detection and tracking, intelligent video coding technology, motion estimation, face detection and recognition, H.264/AVC video coding, and associated VLSI architectures. Shyh-Yih Ma received the B.S.E.E, M.S.E.E, and Ph.D. degrees from National Taiwan University in 1992, 1994, and 2001, respectively. He joined Vivotek, Inc., Taipei County, in 2000, where he developed multimedia communication systems on DSPs. His research interests include video processing algorithm design, algorithm optimization for DSP architecture, and embedded system design. Liang-Gee Chen was born in Yun-Lin, Taiwan, in 1956. He received the BS, MS, and Ph.D degrees in Electrical Engineering from National Cheng Kung University, in 1979, 1981, and 1986, respectively. He was an Instructor (1981–1986), and an Associate Professor (1986–1988) in the the Department of Electrical Engineering, National Cheng Kung University. In the military service during 1987 and 1988, he was an Associate Professor in the Institute of Resource Management, Defense Management College. From 1988, he joined the Department of Electrical Engineering, National Taiwan University. During 1993 to 1994 he was Visiting Consultant of DSP Research Department, AT&T Bell Lab, Murray Hill. At 1997, he was the visiting scholar of the Department of Electrical Engineering, University, of Washington, Seattle. Currently, he is Professor of National Taiwan University. From 2004, he is also the Executive Vice President and the General Director of Electronics Research and Service Organization (ERSO) in the Industrial Technology Research Institute (ITRI). His current research interests are DSP architecture design, video processor design, and video coding system. Dr. Chen is a Fellow of IEEE. He is also a member of the honor society Phi Tan Phi. He was the general chairman of the 7th VLSI Design CAD Symposium. He is also the general chairman of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He serves as Associate Editor of IEEE Trans. on Circuits and Systems for Video Technology from June 1996 until now and the Associate Editor of IEEE Trans. on VLSI Systems from January 1999 until now. He was the Associate Editor of the Journal of Circuits, Systems, and Signal Processing from 1999 until now. He served as the Guest Editor of The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, November 2001. He is also the Associate Editor of the IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing. From 2002, he is also the Associate Editor of Proceedings of the IEEE. Dr. Chen received the Best Paper Award from ROC Computer Society in 1990 and 1994. From 1991 to 1999, he received Long-Term (Acer) Paper Awards annually. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on Circuits and Systems in VLSI design track. In 1993, he received the Annual Paper Award of Chinese Engineer Society. In 1996, he received the Out-standing Research Award from NSC, and the Dragon Excellence Award for Acer. He is elected as the IEEE Circuits and Systems Distinguished Lecturer from 2001–2002.     

VLSI Architecture for Lifting-Based Shape-Adaptive Discrete Wavelet Transform with Odd-Symmetric Filters

In this paper, a VLSI architecture for lifting-based shape-adaptive discrete wavelet transform (SA-DWT) with odd-symmetric filters is proposed. The proposed architecture is comprised of a stage-based boundary extension strategy and the shape-adaptive boundary handling units. The former could reduce the complexity of multiplexers that are introduced to solve the shape-adaptive boundary extension. The latter consists of two multiplexers and can solve the shape-adaptive boundary extension locally without any additional register. Two case studies are presented, including the JPEG 2000 default (9, 7) filter and MPEG-4 default (9, 3) filter. According to comparison results with previous architectures, the efficiency of the proposed architectures is proven.Chao-Tsung Huang was born in Kaohsiung, Taiwan in 1979. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan in 2001. He is currently working toward the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include VLSI design and implementation for 1-D, 2-D, and 3-D Discrete Wavelet Transform. cthuang@video.ee.ntu.edu.twPo-Chih Tseng was born in Tao-Yuan, Taiwan in 1977. He received the B.S. degree in Electrical and Control Engineering from National Chiao Tung University in 1999 and the M.S. degree in Electrical Engineering from National Taiwan University in 2001. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University. His research interests include VLSI design and implementation for signal processing systems, energy-efficient reconfigurable computing for multimedia systems, and power-aware image and video coding systems. pctseng@video.ee.ntu.edu.twLiang-Gee Chen (S84–M86–SM94–F01) received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1979, 1981, and 1986, respectively.In 1988, he joined the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. During 1993–1994, he was a Visiting Consultant in the DSP Research Department, AT&T Bell Labs, Murray Hill, NJ. In 1997, he was a Visiting Scholar of the Department of Electrical Engineering, University of Washington, Seattle. Currently, he is Professor at National Taiwan University, Taipei, Taiwan, R.O.C. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY since 1996, as Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS since 1999, and as Associate Editor of IEEE TRANSACTIONS CIRCUITS AND SYSTEMS II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the PROCEEDINGS OF THE IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001–2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi. lgchen@video.ee.ntu.edu.tw     

Fault Detection in Switched Current Circuits Using Built-in Transient Current Sensors

Switched current (SI) circuits use analogue memory cells as building blocks. In these cells, like in most analogue circuits, there are hard-to-detect faults with conventional test methods. A test approach based on a built-in dynamic current sensor (BIDCS), whose detection method weights the highest frequency components of the dynamic supply current of the circuit under test, makes possible the detection of these faults, taking into account the changes in the slope of the dynamic supply current induced by the fault. A study of the influence of these faults in neighbouring cells helps to minimize the number of BICS needed in SI circuits as is shown in two algorithmic analogue-to-digital converters. Yolanda Lechuga received a degree in Industrial Engineering from the University of Cantabria (Spain) in April 2000. Since then, she has been collaborating with the Microelectronics Engineering Group at the University of Cantabria, in the Electronics Technology, Systems and Automation Engineering Department. Since October 2000 she has been a post-graduate student, to be appointed as lecturer at this university, where she is working in her Ph.D. She is interested in supply current test methods, fault simulation, BIST and design for test of mixed signal integrated circuits. Román Mozuelos received a degree in Physics with electronics from the University of Cantabria, Spain. From 1991 to 1995 he was working on the development of quartz crystal oscillators. Currently, he is a Ph.D. student and an assistant teacher at the University of Cantabria in the Department of Electronics Technology. His interests include mixed-signal design and test, fault simulation, and supply current monitoring. Miguel A. Allende received his graduate degree in 1985 and Ph.D. degree in 1994, both from the University of Cantabria, Santander, Spain. In 1996, he became an Assistant Professor of Electronics Technology at the same Institution, where he is a member of the Microelectronics Engineering Group at the Electronics Technology, Systems and Automation Engineering Department in the Industrial and Telecommunication Engineering School. His research interests include design of VLSI circuits for industrial applications, test and DfT in digital VLSI communication circuits, and power supply current test of mixed, analogue and digital circuits. Mar Martínez received her graduate degree and Ph.D. from the University of Cantabria (Spain) in 1986 and 1990. She has been Assistant Professor of Electronic Technology at the University of Cantabria (Spain) since 1991. At present, she is a member of the Electronics Technology, Systems and Automation Engineering Department in the Industrial and Telecommunication Engineering School. She has participated in several EU and Spanish National Research Projects. Her main research interest is mixed, analogue and digital circuit testing, using techniques based on supply current monitoring. She is also interested in test and design for test in digital VLSI circuits. Salvador Bracho obtained his graduate degree and Ph.D. from the University of Seville (Spain) in 1967 and 1970. He was appointed Professor of Electronic Technology at the University of Cantabria (Spain) in 1973, where, at present, he is a member of the Electronics Technology, Systems and Automation Engineering Department in the Industrial and Telecommunication Engineering School. He has participated, as leader of the Microelectronics Engineering Group at the University of Cantabria, in more than twenty EU and Spanish National Research Projects. His primary research interest is in the area of test and design for test, such as full scan, partial scan or self-test techniques in digital VLSI communication circuits. He is also interested in mixed-signal, analogue and digital test, using methods based on power supply current monitoring. Another research interest is the design of analogue and digital VLSI circuits for industrial applications. Prof. Bracho is a member of the Institute of Electrical and Electronic Engineers.