图形测试:多工位模拟和混合信号器件并行测试效率的关键

多工位测试是许多模拟和混合信号器件生产厂家大批量测试的基石.一直以来,模拟和混合信号器件测试系统面临架构的不足致使并行测试效率(PTE:ParallelTestEfficiency)降低。测试系统架构不断地发展寻求并行测试效率的提高。这一组文章说明并讨论多种测试系统硬件和软件的设计改进,产生更高的并行测试效率。     

基于测试码的测试：多测试位模拟和混合信号器件并行测试效率的关键问题

1介绍 多测试位测试是许多模拟和混合信号器件生产厂家大批量测试的基石。一直以来,模拟和混合信号器件测试系统面临架构的不足,使得并行测试效率降低。测试系统架构不断地发展,寻求并行测试效率的提高。这一组文章说明并讨论多种测试系统硬件和软件的设计改进,以实现更高的并行测试效率。     

图形测试:多工位模拟和混合信号器件并行测试效率的关键

1介绍多工位测试是大多数模拟和混合信号器件生产厂家大批量测试的基石.随着并行测试工位数的提高,模拟和混合信号器件测试系统的设计人员需要     

降低IC测试费用并行测试与多工位测试

集成度增加和功能多样的SOC在消费量最大的产品中,如移动通信手机、微控制器、监视器、游戏机等广泛使用,销售量攀升的同时价格不断下降,但测试费用却居高不下.抑制测试费用上升,挖掘测试系统潜力,实在是当前最迫切的任务.本文介绍的多工位测试与并行测试相结合就是一种可行的解决方案.简单说来,解决办法是将原来只有一个测试插座变成多个测试插座,将串行测试变成并行测试.如果多工位使测试效率提高m倍,并行测试使测试效率提高n倍,则总效率得到m×n倍的改善.     

PWM器件的量产测试方案

本文介绍了主要的PWM器件分类,并在此基础上,重点介绍了基于STS8200平台的PWM器件量产多工位并行测试解决方案,以及并行测试中的注意事项。     

SOC芯片并行测试中几个值得关注的问题

介绍了提高测试效率的SOC芯片在片测试的两种并行测试方法,结合上海集成电路技术与产业促进中心的多个实际的SOC芯片测试项目中所积累的成功经验,针对多工位测试和多测试项目平行测试这两种并行测试方法,主要阐述了在SOC芯片的并行测试中经常遇到的影响测试系统和测试方法的问题,提出了在SOC芯片在片测试中的直流参数测试、功能测试、模数/数模转换器(ADC/DAC)测试的影响因素和解决方案,并对SOC芯片在测试过程中经常遇到的干扰因素进行分析,尽可能保证SOC芯片在片测试获得的各项性能参数精确、可靠.     

泰瑞达的FLEX和若干测试解决方案

SEMICONChina2004是FLEX测试设备在中国第一次露面。FLEX透过灵活的变更结构,达到更快速的测试时间与高效率的并行测试,超越了测试的边界。它一系列的高密度仪器能覆盖广泛的应用范围,包括CD蛐DVD机,手机,和无线网。会展现场演示了包括:FLEX的混合信号测试能达到高于95%的并行测试效率,这一点在多位点的DVD伺服处理器芯片的测试解决方案上充分显示出来。FLEX结构的优势提供了稳定的高产量和高并行测试效率。通过使用Sync-Link结构和BBAC、DC30仪表,可以更加快速地对仪表进行设置和控制,从而获得更高的效率。更快捷的单位点…     

可编程器件

用于消费类芯片测试的量产测试设备科利登系统有限公司推出Sapphire系列的最新成员SapphireD-40系统。该产品利用高密度的集成技术整合了模拟、数字、混合信号和射频测试仪器,具有很好的性价比。SapphireD-40具有更强的数据处理和并行测试能力,能进一步提高量产测试的效率。Sap     

浅析模拟与混合信号电路测试与故障检测方法

模拟和混合信号电路本身具有相当高的复杂性及专业性,使得模拟和混合信号电路测试与故障检测无法在传统数字电路测试方法下得到满足。文章通过介绍模拟和混合信号电路测试与故障检测的研究现状,分析了模拟与混合信号电路的测试与故障检测方法,并在传统测试技术的基础上研究了新的诊断方法,具有参考价值。     

混合IC测试系统有效降低测试成本

Credence推出的Sapphire D-10是为满足，消费电子产品市场的低成本测试需求而设计的混合信号IC测试系统。Sapphire D-10是一个高产能、多功能的圆片和封装测试解决方案，该方案是为微控制器、无线基带、显示驱动器和消费类混合信号器件的低成本测试解决方案而特别设计的。它具有集成度高、体积小、模块化、较高的并行测试能力等特点。     

Application of Supply Current Testing to Analogue Circuits, Towards a Structural Analogue Test Methodology

This paper describes work in progress towards the development, evaluation and validation of a structural, cost effective and quantifiable analog and mixed-signal test methodology, applicable in a production test environment and based on the application of supply current testing. To enable and support the measurements at first an analog supply current monitor was realised. The monitor offers a measurement range of 50 mA, a bandwidth of 1.5 MHz and a resolution better than 1 A. Subsequently the monitor was used to carry out measurements on a mixed-signal Asynchronous Digital Subscriber Line (ADSL) ASIC, to evaluate the feasibility of the methodology. As these initial measurements provided very interesting results, the experiments towards the validation and quantification of the test methodology are now being repeated on a larger scale. The results gathered so far show the potential of the approach to enhance test quality combined with test cost reduction.     

Challenges in analog and mixed-signal fault models

The design and testing of mixed-signal integrated circuits have enjoyed a renaissance in recent years. As is customary with past developments, however, design outpaces testing, and the drive to integrate analog and digital circuits on the same chip exacerbates the test problems. This article reviews the recent results in analog fault modeling-a critical area of mixed-signal testing-and describes the coming challenges for both industrial and university researchers     

Low Cost On-Line Testing Strategy for RF Circuits

This work proposes the use of a simple 1-bit digitizer as an analog block observer, in order to enable the implementation of on-line test strategies for RF analog circuits in the System-on-Chip environment. The main advantages of using a simple digitizer for RF circuits are related to the increased observability of the RF signal path and minimum RF signal degradation, as neither reconfiguration of the signal path nor variable load for the analog RF circuit are introduced. As an additional advantage, the same digitizer can be used to implement BIST strategies, if required. The feasibility of using a 1-bit digitizer for the test of analog signals has already been presented in the literature for low frequency linear analog systems. This paper discusses the implementation of an on-line test strategy for analog RF circuits in the SoC environment, and presents new results for on-line RF testing. Moreover, we also provide detailed analysis regarding the overhead of the test strategy implementation. Experimental results illustrate the feasibility of the proposed technique.Marcelo Negreiros was born in Porto Alegre, Brazil, in 1969. He received the electrical engineering degree in 1992 and the M.S. degree in 1994, both from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil. Since then he was been working as an associate researcher in the Signal Processing Lab. (LaPSI) of the Electrical Engineering Department at UFRGS. Since 2000 he also works toward a Ph.D. in Computer Science from UFRGS. His main research interests include mixed-signal and analog testing and digital signal processing.Luigi Carro was born in Porto Alegre, Brazil, in 1962. He received the Electrical Engineering and the MSc. degrees from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil, in 1985 and 1989, respectively. From 1989 to 1991 he worked at ST-Microelectronics, Agrate, Italy, in the R&D group. In 1996 he received the Ph.D. degree in the area of Computer Science from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil. He is presently a lecturer at the Electrical Engineering Department of UFRGS, in charge of Digital Systems Design and Digital Signal processing disciplines at the graduate and undergraduate level. He is also a member of the Graduation Program in Computer Science of UFRGS, where he is responsible for courses in Embedded Systems, Digital Signal Processing, and VLSI Design. His primary research interests include mixed-signal design, digital signal processing, mixed-signal and analog testing, and fast system prototyping. He has published more than 90 technical papers in those topics and is the author of the book Digital Systems Design and Prototyping (in portuguese).Altamiro A. Susin was born in Vacaria-RS, Brazil, in 1945. He received the Electrical Engineering and the MSc. degrees from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil, in 1972 and 1977, respectively. Since 1968 he worked in the start up of Computer Centers of two local Universities. In 1981 he got his Dr Eng degree from Institut National Polytechnique de Grenoble-France. He is presently a lecturer at the Electrical Engineering Department of UFRGS, in charge of Digital Systems Design disciplines at the graduate and undergraduate level. He is also a member of the Graduation Program in Computer Science of UFRGS, where he is responsible for courses in VLSI Architecture and is also thesis director. His main research interests are integrated circuit architecture, embedded systems, signal processing with more than 50 technical papers published in those domains. He is/was responsible for several R&D projects either funded with public and/or industry resources.     

Utilizing On-chip Resources for Testing Embedded Mixed-signal Cores

For mixed-signal cores on System-on-a-Chip (SoC) platforms, the current methodology in test development is to use special test modes for block isolation such that mixed-signal cores are accessible from the chip boundary through a well-defined interface. Since the access mechanism to the core is preserved, this method facilitates fast test development when the core is re-used on another SoC. In order to obtain the shortest per-device test times on low-cost test platforms, we explore the option of operating the SoC in its designed functional mode where all on-chip resources are fully available for test support. We demonstrate this new method for a microcontroller with embedded ADCs. For high-volume products, the ultimate target is to minimize test costs by maximizing the efficiency of testing multiple devices in parallel on one tester. We demonstrate two benefits of testing in a functional mode that increases parallel test efficiency: (1) Simultaneous testing of multiple on-chip cores, and (2) On-chip post-processing to reduce the amount of test data.     

Built-in-self-test techniques for MEMS

As predicted by technology roadmaps, embedded micro-electro-mechanical-systems (MEMS) is yet another step in the continuous search for higher levels of integration and miniaturization. MEMS are analog components and the test paradigm is similar to the case of analog and mixed-signal circuits. However, given the fact that they work with signals other than electrical, the test of these embedded parts poses new challenges. In this paper, we will review some recent works in this field and we will present a complete approach to MEMS built-in-self-test (BIST) based on pseudorandom testing.     

Multi-VDD Testing for Analog Circuits

We present industrial results of a quiescent current testing technique suitable for RF testing. The operational method consists of ramping the power supply and of observing the corresponding quiescent current signatures. When the power supply is swept, all transistors are forced into various regions of operation. This has as advantage that the detection of faults is done for multiple supply voltages and corresponding quiescent currents, enhancing in this form the detectability of faults. We found that this method of structural testing yields fault coverage results comparable to functional RF tests making it a potential and attractive technique for production wafer testing due to its low cost, low testing times and low frequency requirements.José Pineda de Gyvez received the Ph.D. degree from the Eindhoven University of Technology. He is currently a principal scientist at Philips Research Laboratories, The Netherlands. Dr. Pineda was Associate Editor in IEEE Transactions on Circuits and Systems Part I and also Associate Editor for Technology in IEEE Transactions on Semiconductor Manufacturing. His research interests are in the general areas of design for manufacturability and analog signal processing.Guido Gronthoud received the electrical engineering degree from the Delft University in 1975. From 1976 to 1980 he worked at the Delft University on the design of Microwave systems. From 1980 he works with Philips. He has been working in the fields of circuit simulation and modelling for IC designs, CAD development for PCB design and electronic circuits and systems reliability. Since 1998 he is working on test innovation of digital and mixed-signal circuits. His interests are Defect Oriented Test, fault modeling and Process Related Test. He has authored and co-authored technical papers.     

Applications of Mixed-Signal Technology in Digital Testing

For reducing the test application time and required tester pins per device, we propose the use of multi-valued logic (MVL) signals, which increases data rate between the device under test (DUT) and automatic test equipment (ATE). An MVL signal sends multiple bits of information per clock cycle on a physical channel. Conversion of signals between binary and MVL is accomplished by digital to analog and analog to digital converters available in the mixed-signal technology. To support MVL test application and avoid reliability issues, we add necessary modifications on ATE and DUT sides. Theoretical calculation and a prototype experiment demonstrate significant data rate increase. We integrate the proposed MVL technique into test methodologies involving reduced pin-count test (RPCT) for multi-core system-on-chip (SoC) and test compression. An actual automatic test equipment (ATE) based test of a DUT shows notable reduction in test application time with MVL test application.     

Test throughput for mixed-signal devices

People encounter mixed-signal system-on-a-chip (SOC) devices in our daily lives in a broad range of products. Consumer products like PDAs, automobiles, and appliances all contain microcontrollers, battery management, and power chips; these can be mixed-signal devices. They use broadband products such as set-top boxes, cable modems, DSL, and DVD players that contain mixed-signal devices. Wireless products, cordless phones, cellular phones, WLAN, Bluetooth, GPS receivers, and cable tuners also contain mixed-signal SOC devices. The content of the mixed-signal SOC device is characterized by different types of cores. They may be analog cores or digital cores. Many applications include mixed analog and digital cores such as digital-to-analog converters (DACs) and analog-to-digital converters (ADCs). These devices can provide complete system functionality on a single chip. One of the important principles to improving test economics is to ensure that test times are as low as possible. When testing, it is important that the test system is not adding overhead time. Beyond fast test software, the device-limited test speed is approached when tester operations execute in parallel with device operation. The architecture of the test system is key when approaching test times that are device limited. This can be achieved with a test system architecture that controls instrumentation precisely in device clock time. Mixed-signal device testing has adopted the use of DSP techniques to obtain a set of test measurements from large data sets. Each core within the device can produce data simultaneously. In the case of the device described earlier, there may be three video converters and five audio converters, all producing large amounts of data.     

Wafer-Level Defect Screening for “Big-D/Small-A” Mixed-Signal SoCs

Product cost is a key driver in the consumer electronics market, which is characterized by low profit margins and the use of a variety of “big-D/small-A” mixed-signal system-on-chip (SoC) designs. Packaging cost has recently emerged as a major contributor to the product cost for such SoCs. Wafer-level testing can be used to screen defective dies, thereby reducing packaging cost. We propose a new correlation-based signature analysis technique that is especially suitable for mixed-signal test at the wafer-level using low-cost digital testers. The proposed method overcomes the limitations of measurement inaccuracies at the wafer-level. A generic cost model is used to evaluate the effectiveness of wafer-level testing of analog and digital cores in a mixed-signal SoC, and to study its impact on test escapes, yield loss, and packaging costs. Experimental results are presented for a typical mixed-signal “big-D/small-A” SoC, which contains a large section of flattened digital logic and several large mixed-signal cores.