Cellular automata-based built-in self-test structures for VLSI systems

Some of the fundamental algebraic properties of hybrid additive, null-bounded, cellular automata (HACA) are presented. Simple HACA have been obtained by spatially alternating additive rules 90 and 150 (in Wolfram's notation). The use of such HACA for on-chip pseudorandom test pattern generation is also described. The great advantage of HACA over linear feedback shift registers (LFSR), as their size increases, is the fact that HACA display locality and topological regularity, important attributes for VLSI implementation.<>     

A built-in self-test method for diagnosis of synchronous sequentialcircuits

We propose an approach for built-in fault diagnosis of synchronous sequential circuits. The proposed approach distinguishes faults based on their detection by modified versions of a fault detection test sequence generated on-chip. The modified versions are defined by one-bit-wide auxiliary sequences, also generated on-chip. The auxiliary sequences indicate which test vectors of the fault detection test sequence need to be applied to the circuit. Experimental results presented indicate that the proposed on-chip test generation method is effective in achieving high levels of diagnostic-resolution     

Built-in self-test (BIST) design of high-speed carry-free dividers

This paper presents the built-in self-test (BIST) design of a C-testable high-speed carry-free divider which can be fully tested by 72 test patterns irrespective of the divider size. Using a graph labeling scheme, the test patterns, expected outputs, and control signals can be represented by sets of labels and generated by a simple circuitry. As a result, test patterns can be easily generated inside chips, responses to test patterns need not to be stored, and use of expensive test equipment is not necessary. Results show that the hardware cost for generating such labels is virtually constant irrespective of the circuit size. For the BIST design of a 64 b C-testable divider, its hardware overhead is less than 5%     

Processor-based built-in self-test for embedded DRAM

A built-in self-test engine and test methodology have been developed for testing a family of high-bandwidth, high-density DRAM macros. The DRAM macros range in size from 256×16×128 to 2 K×16×256 (Word×Bit×Data) and are targeted for embedded applications in application-specific integrated circuit designs. The processor-based test engine, with two separate instruction storage memories, combines with flexible address, data, and clock generators to provide DRAM high-performance ac testing using a minimum of dedicated test pins. Test results are compressed through on-macro, two-dimensional, redundancy allocation logic to provide direct programming information for the fuser via a serial scan port. The design is intended for reuse on future DRAM-generation subarrays and can be adapted to any number of address or data-pin configurations     

内建自测试的测试生成方法研究

内建自测试（BIST）方法是目前可测试性设计（DFT）中应用前景最好的一种方法,其中测试生成是关系BIST性能好坏的一个重要方面。测试生成的目的在于生成尽可能少的测试向量并用以获得足够高的故障覆盖率,同时使得用于测试的硬件电路面积开销尽可能低、测试时间尽可能短。内建自测试的测试生成方法有多种,文中即对这些方法进行了简单介绍和对比研究,分析了各自的优缺点,并在此基础上探讨了BIST面临的主要问题及发展方向。     

带有自测试电路的10GSps 8bit DAC设计

We present a 10 Gsps 8 bit digital-to-analog converter （DAC） with a novel built-in self-test （BIST） circuit, which makes it possible to evaluate the DAC＇s performance without a complicated test setup. Design con- siderations and test results are included. According to the test results, the DAC core and the BIST circuit are able to work under 10 GHz. The chip is fabricated in 0.18μm SiGe HBTs with ft of 100 GHz. The DAC core occupies a die size of 260 × 250μm^2.     

On-chip ramp generators for mixed-signal BIST and ADC self-test

A practical approach to generate on-chip precise and slow analog ramps, intended for time-domain analog testing, monotonicity and histogram-based tests of ADCs is proposed. The technique uses an analog discrete-time adaptive scheme to calibrate the ramp generator. The lowest slope is 0.4V/ms. Three implementations are presented for different levels of accuracy and complexity. Measurement results show excellent accuracy and programmability, up to only 0.6% of slope error and maximum integral nonlinearity error of /spl plusmn/175/spl mu/V. Experimental and theoretical results are in good agreement.     

Unified built-in self-test for fully differential analog circuits

The reduction of test costs, especially in high safety systems, requires that the same test strategy is employed for design validation, manufacturing and maintenance tests, and concurrent error detection. This unification of off-line and on-line tests has already been attempted for digital circuits and it offers the advantage of serving to all phases of a system lifetime.Market pressure originating from the high costs of analog and mixed signal testing has resulted in renewed efforts for the test of analog parts. In this paper, off-line and on-line test techniques for fully differential analog circuits are presented within an unified approach. The high performance of these circuits makes them very popular for many applications, including high safety, low voltage and high speed systems.A test master compliant with IEEE Std. 1149.1 is described. The Analog Unified BIST (AUBIST) is exemplified for linear and non-linear switched-capacitor circuits. High fault coverage is achieved during concurrent/on-line testing. An off-line test ensures the goal of self-checking circuits and allows the diagnosis of faulty parts. The self-test of the AUBIST circuitry is also considered.This work is part of AMATIST ESPRIT-III Basic Research Project, funded by CEC under contract #8820.     

Equations of nonlinear analogue circuit for fault dictionary generation

A method for the generation of fault equations of a nonlinear analogue circuit is suggested. It is useful in the context of a fault dictionary. The method is easy to program as it is based on node analysis. Furthermore, the equations of the faulty network can be quickly derived from those of the nominal network.<>     

A new reconfigurable Test Vector Generator for built-in self-test applications

This paper proposes a new approach to designing a BIST Test Vector Generator (TVG) for random vector-resistant circuits based on reconfigurable Cellular Automata Registers (CARs). Each CAR configuration is constructed by combining rules 90 and 150 and the same approach can also be applied to the Linear Feedback Shift Register (LFSR). The TVG thus designed is able to produce 100% fault coverage with short test time at the cost of low area overhead. To achieve this objective, a new method called the Rank Order Clustering (ROC) method, is introduced in order to fix a number of inputs at certain values when generating pseudorandom vectors. It is shown that the ROC method is very simple and efficient in fixing inputs at these values in terms of complexity. Experimental results have been conducted to demonstrate the applicability of the proposed approach in terms of hardware size and test application time.     

电子电路的故障诊断基本技术

分析了电子电路的故障诊断基本技术。包括电子电路故障的分类,复杂设备无耗损区规律,设备全寿命故障率递减规律,常用模拟电路故障诊断的方法,数字电路故障测试基本技术等。     

应用数据融合实现电子电路的故障诊断

在电路故障诊断中,可通过直流分析、交流分析和灵敏度分析等方法,对电路的故障进行诊断.但由于不同的诊断方法对不同的故障敏感度不同,使得每种方法都带有局限性.为此,本文提出了采用数据融合进行电路故障诊断的新方法,介绍了D-S证据理论算法在电路故障诊断中的应用,给出了具体算法和仿真实例.理论分析和仿真结果表明,将数据融合技术用于电路的故障诊断是可行的.不同的诊断方法提供的信息经多次融合、反复抽取有用信息后,大大降低了判断的盲目性,提高了电路故障诊断的准确性.     

一种模拟电路故障诊断方法研究

将LSSVM算法应用于模拟电路故障诊断模型,使用PSO算法对LSSVM算法的参数进行寻优。以带通滤波器电路和双二次高通滤波器电路的故障诊断实例对该文研究的模拟电路故障诊断方法进行验证。使用三层小波包分解输出电压信号,得到8个频带能量特征向量,通过Monte Carlo仿真得到数据样本,用于故障诊断模型的训练和测试。结果表明,该文使用的改进LSSVM算法构建的故障诊断模型针对8种故障的诊断准确率均高于95%,具有较好的故障诊断性能。     

Mixed integer programming method for fault diagnosis of linear analogue circuits

Fault diagnosis of linear analogue circuits can be formulated as a mixed integer programming problem. This avoids testing all possible combinations of submatrices of the equations of the network to determine faults.<>     

A built-in Hamming code ECC circuit for DRAMs

An error checking and correcting (ECC) technique that checks multiple cell data simultaneously and allows fast column access is described. The ECC circuit is optimized with respect to the increase in the chip area and the access-time penalty, and can be applied to a 16-Mbit DRAM with 20% chip area increase and less access-time penalty. The soft error rate has been estimated to be about 100 times smaller than that of the basic horizontal-vertical parity-code ECC technique     

On minimal set of test nodes for fault dictionary of analog circuit fault diagnosis

A method is proposed to obtain a minimal set of test nodes of an analog circuit for isolating all faulty conditions in the fault dictionary approach. Relevant theorem along with the proof is also given. Proposed method is extremely fast. This method is illustrated with an active filter circuit example.     

Test generation,design-for-testability and built-in self-test for arithmetic units based on graph labeling

In this article we discuss a test generation, design-for-testability and built-in self-test methodology for two-dimensional iterative logic arrays (ILAs) that perform arithmetic functions. Our approach is unique because a single graph labeling procedure is used to generate test vectors, implement design-for-testability as well as design the circuitry for built-in self-test. The graph labeling is based on mathematical properties of full-addition such as symmetry and self-duality. Circuit modifications are introduced by a systematic procedure based on the graph labeling, that enable them to be tested with a fixed number of tests irrespective of their size. The approach is novel as it also greatly simplifies the processes of on-chip test vector generation and response comparison that are necessary for built-in self-test. Each circuit module is tested in a pseudo-exhaustive manner with deterministic as opposed to random test sequences. This results in a comprehensive test of the circuit for which built-in self-test is designed.This research was supported by the General Electric Company and by the Semiconductor Research Corporation under contracts SRC RSCH 88-DP-108 at the University of Illinois and SRC RSCH 89-DP-142 at the University of Texas at Austin.     

A self-test and dynamics characterization circuit for MEMS electrostatic actuators

This paper presents a high-bandwidth capacitance estimation and driving circuit especially tailored for its use with MEMS electrostatic actuators. The circuit can be integrated as a part of a system comprising an electrostatic actuator to provide self-testing and failure prediction capabilities and also as a simple and low-cost actuator dynamics characterization system capable of measuring both periodic and non-periodic movements.     

Quantitative analysis for linear hybrid cellular automata and LFSR as built-in self-test generators for sequential faults

This paper presents a combinatorial method of evaluating the effectiveness of linear hybrid cellular automata (LHCA) and linear feedback shift registers (LFSR) as generators for stimulating faults requiring a pair of vectors. We provide a theoretical analysis and empirical comparisons to see why the LHCA are better than the LFSRs as generators for sequential-type faults in a built-in self-test environment. Based on the concept of a partner set, the method derives the number of distinctk-cell substate vectors which have 2^2k , 1k[n/2], transition capability for ann-cell LHCA and ann-cell LFSR with maximum length cycles. Simulation studies of the ISCAS85 benchmark circuits provide evidence of the effectiveness of the theoretrical metric.This work was supported in part by Reserach Grants No. 5711 and No. 39409 and a Strategic Grant from the Natural Sciences and Engineering Research Council of Canada and by an equipments loan from the Canadian Microelectronics Corporation.A preliminary version of this paper is partially presented at theIEEE ISCAS'94, May 1994.