A novel SET/MOSFET hybrid static memory cell design

In this paper, a single electron transistor (SET)/metal-oxide-semiconductor field effect transistor (MOSFET)-based static memory cell is proposed. The negative differential conductance (NDC) characteristics of the SET block help us establish the static memory cell circuits more compactly than those in conventional technologies. The proposed memory cell consists of one MOSFET and two back-to-back connected SET blocks exhibiting the NDC. The peak-to-valley current ratio of the SET block is above four with C/sub G/=5.4C/sub T/ (C/sub T/=0.1 aF) at T=77K. The read and write operations of the proposed memory cell were validated with SET/MOSFET hybrid simulations at T=77 K. Even though the fabrication process that integrates MOSFET devices and SET blocks with NDC is not yet available, these results suggest that the proposed SET/MOSFET hybrid static memory cell is suitable for a high-density memory system.     

Contact-independent measurement of electrical conductance of a thin film with a nanoscale sensor

Contact effects are a common impediment to electrical measurements throughout the fields of nanoelectronics, organic electronics, and the emerging field of graphene electronics. We demonstrate a novel method of measuring electrical conductance in a thin film of amorphous germanium that is insensitive to contact effects. The measurement is based on the capacitive coupling of a nanoscale metal-oxide-semiconductor field-effect transistor (MOSFET) to the thin film so that the MOSFET senses charge diffusion in the film. We tune the contact resistance between the film and contact electrodes and show that our measurement is unaffected. With the MOSFET, we measure the temperature and field dependence of the conductance of the amorphous germanium, which are fit to a model of variable-range hopping. The device structure enables both a contact-independent and a conventional, contact-dependent measurement, which makes it possible to discern the effect of the contacts in the latter measurement. This measurement method can be used for reliable electrical characterization of new materials and to determine the effect of contacts on conventional electron transport measurements, thus guiding the choice of optimal contact materials.     

Substrate current enhancement in 65 nm metal-oxide-silicon field-effect transistor under external mechanical stress

An approach to get uniaxial tensile stress from the channel by using strained silicon to enhance drain current and mobility was developed. A 65 nm metal-oxide-semiconductor field-effect transistor (MOSFET) was bent by applying external mechanical stress. The drain current and transconductance of the transistor were found to increase 15% and 20%, respectively. In this paper, the behaviors of the substrate current and the impact ionization rate are also investigated. It was found that the substrate current and gate voltage corresponding to the maximum impact ionization current have significantly increased by increasing external mechanical stress. According to the relationship to the strain-induced mobility enhancement, the increase in impact ionization efficiency resulted from the decrease in threshold energy for impact ionization which was due to the narrowing of the bandgap.     

The other transistor: early history of the metal-oxidesemiconductor field-effect transistor

The silicon metal-oxide-semiconductor field-effect transistor (MOSFET or MOS transistor) did not become significant commercially until two decades after the 1948 announcement of the invention of the transistor by Bell Laboratories. The underlying concept of the MOSFET-modulation of conductivity in a semiconductor triode structure by a transverse electric field-first appeared in a 1928 patent application. It was confirmed experimentally in 1948. However early devices were not practical due to surface problems. Although these were solved at Bell Laboratories in 1958, Bell remained committed to earlier transistor technology. Development of the `other transistor' was first pursued elsewhere. It was finally the needs of computers and the opportunities created by integrated circuits that made the silicon MOSFET the basic element of late 20th-century digital electronics     

Electrostatic control of ions and molecules in nanofluidic transistors

We report a nanofluidic transistor based on a metal-oxide-solution (MOSol) system that is similar to a metal-oxide-semiconductor field-effect transistor (MOSFET). Using a combination of fluorescence and electrical measurements, we demonstrate that gate voltage modulates the concentration of ions and molecules in the channel and controls the ionic conductance. Our results illustrate the efficacy of field-effect control in nanofluidics, which could have broad implications on integrated nanofluidic circuits for manipulation of ions and biomolecules in sub-femtoliter volumes.     

Effects of dopant granularity on superhalo-channel MOSFETs according to two- and three-dimensional computer simulations

We have performed two-dimensional (2-D) and three-dimensional (3-D) computer simulations of random dopant fluctuations in 25-nm planar n-channel metal-oxide-semiconductor field effect transistor (MOSFET) with superhalo channel doping. Our study shows that 2-D simulations that neglect lateral percolation of the carriers can overestimate the impact on threshold voltage (V/sub T/) fluctuations by as much as a factor of four. Fundamental differences in the way the 2-D and 3-D models describe subthreshold and near-threshold conduction are highlighted in our study. Our models reveal that surface percolation of carriers is an effective agent for reducing V/sub T/ fluctuations. In addition, the halo only enhances the V/sub T/ fluctuations by approximately 10%. Though the influence of the superhalo in the device may be overwhelmed by atomistic granularity according to the 2-D model, 3-D simulations show that the halo continues to function coherently for the MOSFET ensemble when charge percolation is accounted.     

Optimum power-saving method for power MOSFET width of DC/DC converters

An optimum power metal-oxide-semiconductor field effect transistor (MOSFET) width technique is proposed for enhancing the efficiency characteristics of switching DC-DC converters. By implementing a one-cycle buck DC-DC converter, it is demonstrated that the dynamic power MOSFET width controlling technique has a much improved power reduction whether the load current is light or heavy. The maximum efficiency of the buck converter is ~92% with a 3% efficiency improvement for the heavy load condition. The efficiency is further improved by ~16% for the light load condition as a result of the power reduction from the large power MOSFET transistors. Also proposed is a new error-correction loop circuit to enable a better load regulation than that of previous designs. Compared with the adaptive gate driver voltage technique, the optimum power MOSFET width can achieve a significant improvement in power saving. It is also superior to the low-voltage-swing MOSFET gate drive technique for switching DC-DC converters     

SOI MOSFET with an insulator region (IR-SOI): A novel device for reliable nanoscale CMOS circuits

Device performance in the electronic circuits degrades with elapsed time. Therefore it is important to design a new device to have a reliable performance. In this paper, we present the unique features exhibited by a novel nanoscale silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistor (MOSFET) in which the silicon active layer consists of an insulator region (IR-SOI). The high-K dielectric HfO₂ as an insulator material is located in the silicon active layer and drain region. Our simulation results demonstrate that this leads to improve the hot electron reliability of the IR-SOI in comparison with the conventional SOI-MOSFET (C-SOI). The insulator region HfO₂ considerably decreases the electric field in the channel and drain regions. Therefore, the degradation mechanism in the proposed structure is lower than that in the C-SOI structure because of reduction of hot carrier effect (HCE). Also using two-dimensional and two-carrier device simulation, we have investigated the improvement in device performance focusing on the HCE, off current, gate current and gate induced drain leakage (GIDL) which can effect on the reliability of the CMOS devices.     

Source/drain junction fabrication for Ge metal-oxide-semiconductor field-effect transistors

We established fabrication methods for high-quality Ge n⁺/p and p⁺/n junctions using thermal diffusion of P and implantation of B, respectively. The carrier concentrations in n⁺ and p⁺ layers were as high as 4 × 10¹⁹ and 2 × 10¹⁹ cm^− 3, respectively. It was found that a peripheral surface-state current dominates the reverse leakage current in an n⁺/p junction diode. The protection of junction surfaces from plasma damage during the SiO₂ deposition was essential to achieve high-quality source/drain junctions. The surface passivation with a GeO₂ interlayer was harmful to an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) because of an increase in a surface leakage current due to inversion carriers. For a p-channel MOSFET, on the other hand, the GeO₂ interlayer plays a role in decreasing the surface leakage current.     

3-D Design and Analysis of Functional NEMS-gate MOSFETs and SETs

Nanoelectromechanical system (NEMS)-gate metal- oxide-semiconductor field effect transistor (MOSFET) and single- electron transistor (SET) structures are investigated by combining 3-D design and SPICE simulation. First, the metal gate is simulated by using a 3-D simulator, which enables to design realistic 3-D device structures, and its movement is studied for different design parameters. It is demonstrated that a low stiffness design of the structure is essential for a low-voltage actuation. Results are compared with theoretical numerical simulation and a tunable capacitor model is then embedded in a SPICE simulator and coupled either with a transistor model for MOS-NEMS or with a newly developed SET analytical model for SET-NEMS. It is shown that the use of NEMS membrane can add new functionalities to conventional MOSFET and SET, such as very abrupt switching of the current, which can break theoretical limits of MOSFET, or modulation of Coulomb oscillations governing SET characteristics     

SOI Pixel Based on a Floating Body Partially Depleted MOSFET in a Delta-Sigma Loop

Standard techniques used for measuring the photocurrent of an SOI phototransistor have failed due to two main reasons: the first being the low signal-to-noise ratio and the second being the slow transient. In this paper, the partially depleted silicon on insulator (SOI) metal-oxide-semiconductor field effect transistor (MOSFET) has been used as a light intensity sensor. Using a novel technique of measurement enables us to embed this phototransistor in the delta-sigma loop. The presented circuits implement a first-order delta-sigma modulator with limited number of transistors maximizing the fill factor. Measured data show that the implemented pixels were sensitive to flux densities as low as 3 $~{rm mW/m}^{2}$ with a resolution of 7.5 bits.      

Silicon nanotube field effect transistor with core-shell gate stacks for enhanced high-performance operation and area scaling benefits

We introduce the concept of a silicon nanotube field effect transistor whose unique core-shell gate stacks help achieve full volume inversion by giving a surge in minority carrier concentration in the near vicinity of the ultrathin channel and at the same time rapid roll-off at the source and drain junctions constituting velocity saturation-induced higher drive current-enhanced high performance per device with efficient real estate consumption. The core-shell gate stacks also provide superior short channel effects control than classical planar metal oxide semiconductor field effect transistor (MOSFET) and gate-all-around nanowire FET. The proposed device offers the true potential to be an ideal blend for quantum ballistic transport study of device property control by bottom-up approach and high-density integration compatibility using top-down state-of-the-art complementary metal oxide semiconductor flow.     

Spin injection, transport, and read/write operation in spin-based MOSFET

We proposed a novel spin-based MOSFET “Spin-Transfer-torque-Switching MOSFET (STS-MOSFET)” that offers non-volatile memory and transistor functions with complementary metal-oxide-semiconductor (CMOS) compatibility, high endurance and fast write time using STS. The STS-MOSFETs with Heusler alloy (Co₂Fe₁Al_0.5Si_0.5) were prepared and reconfigurability of a novel spintronics-based MOSFET, STS-MOSFET, was successfully realized for the transport properties owing to reduction of the contact resistance in ferromagnetic metal/thin insulator tunnel barrier/Si junctions. The device showed magnetocurrent (MC) and write characteristics with the endurance of over 10⁵ cycles. It was also clarified that the read characteristic can be improved in terms of MC ratio, however, is deteriorated in terms of the mobility by choosing connection configurations of the source and the drain in the STS-MOSFETs.     

Wavy Architecture Thin‐Film Transistor for Ultrahigh Resolution Flexible Displays

A novel wavy‐shaped thin‐film‐transistor (TFT) architecture, capable of achieving 70% higher drive current per unit chip area when compared with planar conventional TFT architectures, is reported for flexible display application. The transistor, due to its atypical architecture, does not alter the turn‐on voltage or the OFF current values, leading to higher performance without compromising static power consumption. The concept behind this architecture is expanding the transistor's width vertically through grooved trenches in a structural layer deposited on a flexible substrate. Operation of zinc oxide (ZnO)‐based TFTs is shown down to a bending radius of 5 mm with no degradation in the electrical performance or cracks in the gate stack. Finally, flexible low‐power LEDs driven by the respective currents of the novel wavy, and conventional coplanar architectures are demonstrated, where the novel architecture is able to drive the LED at 2 × the output power, 3 versus 1.5 mW, which demonstrates the potential use for ultrahigh resolution displays in an area efficient manner.     

A practical SPICE model based on the physics and characteristics of realistic single-electron transistors

A practical model for a single-electron transistor (SET) was developed based on the physical phenomena in realistic Si SETs, and implemented into a conventional circuit simulator. In the proposed model, the SET current calculated by the analytic model is combined with the parasitic MOSFET characteristics, which have been observed in many recently reported SETs formed on Si nanostructures. The SPICE simulation results were compared with the measured characteristics of the Si SETs. In terms of the bias, temperature, and size dependence of the realistic SET characteristics, an extensive comparison leads to good agreement within a reasonable level of accuracy. This result is noticeable in that a single set of model parameters was used, while considering divergent physical phenomena such as the parasitic MOSFET, the Coulomb oscillation phase shift, and the tunneling resistance modulated by the gate bias. When compared to the measured data, the accuracy of the voltage transfer characteristics of a single-electron inverter obtained from the SPICE simulation was within 15%. This new SPICE model can be applied to estimating the realistic performance of a CMOS/SET hybrid circuit or various SET logic architectures.     

High performance horizontal gate-all-around silicon nanowire field-effect transistors

Semiconducting nanowires have been pointed out as one of the most promising building blocks for submicron electrical applications. These nanometer materials open new opportunities in the area of post-planar traditional metal-oxide-semiconductor devices. Herein, we demonstrate a new technique to fabricate horizontally suspended silicon nanowires with gate-all-around field-effect transistors. We present the design, fabrication and electrical measurements of a high performance transistor with high on current density (～150?μA?μm(-1)), high on/off current ratio (10(6)), low threshold voltage (～?-?0.4?V), low subthreshold slope (～100?mV /dec) and high transconductance (g(m)?～?9.5?μS). These high performance characteristics were possible due to the tight electrostatic coupling of the surrounding gate, which significantly reduced the Schottky-barrier effective height, as was confirmed experimentally in this study.     

Integrations and challenges of novel high-k gate stacks in advanced CMOS technology

Due to the limitations in conventional complementary metal-oxide-semiconductor (CMOS) scaling technology in recent years, innovation in transistor structures and integration of novel materials has been a key to enhancing the performance of CMOS field-effect transistors (FETs) of past technology generations. Tremendous progress of high dielectric constant (high-k) gate stacks has been made in recent years and some of them have come into application in CMOS devices. However, many challenges remain, such as: (a) suitable permittivity, band gap and band alignment for dielectrics, on Si, (b) thermodynamic stability and interface engineering at both high-k/Si interface and metal/metal interface, (c) depletion effect, high gate resistance and its incompatibility with high-k for metal gate, and (d) low performance attributed to threshold voltage instability. Based on current progress and fundamental considerations, we review the current status and challenges in novel high-k dielectrics and metal gates research for planar CMOS devices and alternative device technologies to provide insights for future research. Finally, this review concludes with perspectives towards the future gate stack technology and challenges in advanced CMOS devices.     

Hydrogen ion sensors based on indium tin oxide thin film using radio frequency sputtering system

Indium tin oxide (ITO) thin films were deposited onto Si and SiO₂/Si substrates using a radio frequency sputtering system with a grain size of 30-50 nm and thickness of 270-280 nm. ITO/Si and ITO/SiO₂/Si sensing structures were achieved and connected to a standard metal-oxide-semiconductor field-effect transistor (MOSFET) as an ITO pH extended-gate field-effect transistor (ITO pH-EGFET). The semiconductor parameter analysis measurement (Keithley 4200) was utilized to measure the current-voltage (I-V) characteristics curves and study the sensing properties of the ITO pH-EGFET. The linear pH voltage sensitivities were about 41.43 and 43.04 mV/pH for the ITO/Si and ITO/SiO₂/Si sensing structures, respectively. At the same time, both pH current sensitivities were about 49.86 and 51.73 µA/pH, respectively. Consequently, both sensing structures can be applied as extended-gate sensing heads. The separative structure is suitable for application as a disposable pH sensor.     

Characterization of silicon dioxide films on a 4H-SiC Si(0001) face by fourier transform infrared (FT-IR) spectroscopy and cathodoluminescence spectroscopy

We used Fourier transform infrared (FT-IR) spectroscopy to characterize silicon dioxide (SiO(2)) films on a 4H-SiC(0001) Si face. We found that the peak frequency of the transverse optical (TO) phonon in SiO(2) films grown on a 4H-SiC substrate agrees well with that in SiO(2) films grown on a Si substrate, whereas the peak frequency of the longitudinal optical (LO) phonon in SiO(2) films on a 4H-SiC substrate is red-shifted by approximately 50 cm(-1) relative to that in SiO(2) films on a Si substrate. We concluded that this red-shift of the LO phonon is mainly caused by a change in inhomogeneity due to a decrease in density in the SiO(2) films. Furthermore, cathodoluminescence (CL) spectroscopy results indicated that the channel mobility of the SiC metal-oxide-semiconductor field-effect transistor (MOSFET) decreases roughly in proportion to the increase in the intensity of the CL peak at 460 and 490 nm, which is attributed to the increase in the number of oxygen vacancy centers (OVCs). FT-IR and CL spectroscopies provide us with a large amount of data on OVCs in the SiO(2) films on a 4H-SiC substrate.