Analysis of I–V measurements on PtSi-Si Schottky structures in a wide temperature range

I–V Measurements on PtSi-Si Schottky structures in a wide temperature range from 90 to 350 K were carried out. The contributions of thermionic-emission current and various other current-transport mechanisms were assumed when evaluating the Schottky barrier height Φ₀. Thus the generation-recombination, tunneling and leak currents caused by inhomogeneities and defects at the metal-semiconductor interface were taken into account.

Taking the above-mentioned mechanisms and their temperature dependence into consideration in the Schottky diode model, an outstanding agreement between theory and experiment was achieved in a wide temperature range.

Excluding the secondary current-transport mechanisms from the total current, a more exact value of the thermionic-emission saturation current I_te and thus a more accurate value ofΦ_b was reached.

The barrier height Φ_b and the modified Richardson constant A^** were calculated from the plot of thermionic-emission saturation current I_te as a function of temperature too. The proposed method of finding Φ_b is independent of the exact values of the metal-semiconductor contact area A and of the modified Richardson constant A^**. This fact can be used for determination of Φ_b in new Schottky structures based on multicomponent semiconductor materials.

Using the experimentally evaluated value A^** = 1.796 × 10⁶ Am⁻²K⁻² for the barrier height determination from I–V characteristics the value of Φ_b = 0.881 ± 0.002 eV was reached independent of temperature.

The more exact value of barrier height Φ_b is a relevant input parameter for Schottky diode computer-aided modeling and simulation, which provided a closer correlation between the experimental and theoretical characteristics.     

Modeling of the I–V characteristics of high-field stressed MOS structures using a Fowler–Nordheim-type tunneling expression

The gate current–voltage characteristic of a high-field stressed metal-oxide-semiconductor structure with trapped charge within the insulator barrier is consistent with a Fowler–Nordheim-type tunneling expression. Instead of considering a correction for the cathode electric field as usual, we use an effective local electric field that takes into account the distortion of the oxide conduction band profile caused by the trapped charge. An energy level at the injecting interface, introduced as an optimization parameter of the model, controls the tunneling distance used for calculating the effective field. Trap generation in the oxide is induced by high-field constant current stress and subsequent electron trapping at different injection levels is monitored by measuring the associated flat band voltage shift. The model applies for positive gate injection regardless the stress polarity and the involved parameters are obtained by fitting the experimental data without invoking any particular theoretical model for the trapping dynamics. In addition, it is shown how the presented model accounts for consistently both the current–voltage and voltage–current characteristics as a function of the injected charge through the oxide.     

Analytic expression for the Fowler–Nordheim V–I characteristic including the series resistance effect

It is shown in this communication that the Fowler-Nordheim (FN) tunneling expression for the current-voltage (I-V) characteristic can be analytically inverted so that an exact expression for the voltage-current (V-I) characteristic can be obtained. The solution of the resulting implicit equation is found using the Lambert W function, i.e. the solution of the transcendental equation we^w = x. The reported expressions are supported by experimental I-V curves measured in thin (≈5 nm) SiO₂ films in MOS capacitors. The analysis includes the case of a tunneling oxide with a large series resistance. For practical purposes, a closed-form expression for W based on a Padé-type approximation is also provided.     

A function-fit model for the hard breakdown I–V characteristics of ultra-thin oxides in MOS structures

A function-fit model for the hard breakdown current–voltage characteristics of ultra-thin oxides in metal–oxide–semiconductor structures based on the smoothing function concept is presented. The model is intended to capture the diode-like and resistance-like behaviours observed at low and high applied biases, respectively, by means of a simple, continuous and derivable function. These features make the proposed expression suited for circuit simulation environments. The effect of temperature on the model parameters is also analysed.     

Predicting the process induced warpage of electronic packages using the P–V–T–C equation and the Taguchi method

A critical issue in the manufacturing of electronic packages is the warpage induced during the molding process as a result of differences in the shrinkage of the constituent materials. Package warpage causes serious problems such as the quality degradation of devices and yield loss in manufacturing processes. Loss of lead coplanarity happens due to package warpage and causes difficulty in device testing and surface mount assembly. Internal stresses associated with package warpage can also cause device failures such as die cracking, broken circuits and package cracking.Warpage in IC package has drawn intensive attention in the past. Although the effects of thermal shrinkage were extensively investigated in the literatures, the influence of the cure shrinkage on package warpage had received less attention. Accordingly, this study develops a numerical approach for generating more accurate predictions of the package warpage by taking the effects of both thermal shrinkage and cure shrinkage into account. A three-dimensional finite element model of the small outline package (TSOP) DBS-27P is constructed and the proposed numerical approach, which is based on the P–V–T–C (pressure–volume–temperature–conversion) equation and the CTEs (coefficients of thermal expansion) of the package materials, is employed to predict the warpage at each of its corners under various packaging processing conditions. Using the Taguchi method, the relative influences of the transfer pressure, the packing pressure, the mold temperature and the curing time on the degree of package warpage are identified and the optimal processing conditions are established. A series of experimental packaging trials are performed using the optimal processing conditions. It is found that the warpage of the actual package is in good agreement with that predicted numerically. Therefore, the accuracy of the proposed numerical approach is confirmed. Moreover, the results also demonstrate the capability of the Taguchi method to identify the optimal packaging processing parameters on the basis of a limited number of simulation runs.     

Impact of the electron, proton and helium irradiation on the forward I–V characteristics of high-power P–i–N diode

2.5 kV/100 A high-power P–i–N diode was electron, proton and helium irradiated in a wide range of irradiation doses with irradiation energies in the MeV range. The resulting forward I–V curves were registered in the temperature range 30–125 °C to investigate the magnitude of the crossing point current of the I–V curves––I_XING. I_XING was found to decrease with increasing irradiation dose and to disappear at high doses for all three irradiation treatments with exception of ion irradiated diodes with defect peaks placed deeply into the anode region. Using a simple model based on the thermal and injection dependence of the carrier lifetime, the explanation of this effect is presented with the support of the non-isothermal 2-D device simulation of helium irradiated devices.     

Determination of the dice forward I–V characteristics of a power diode from a packaged device and its applications

The forward voltage drop (V_F) of a power diode is an important electrical parameter for a power diode. Diode with excessive V_F can be due to either defects in wafer fabrication or soldering processes. To identify if the defects in soldering process is the root cause to excessive V_F, the obvious method will be the method to extract the series resistance from the diode. However, the present series resistance extraction methods are either inaccurate or requires extensive computation time, and they are not practical for failure analysis and process monitoring. In this work, a modified series resistance extraction method is developed. Experimental results showed that the modified method is accurate, and the computation time is short.     

An accurate mobility model for the I–V characteristics of n-channel enhancement-mode MOSFETs with single-channel boron implantation

In this paper we develop an analytical mobility model for the I–V characteristics of n-channel enhancement-mode MOSFETs, in which the effects of the two-dimensional electric fields in the surface inversion channel and the parasitic resistances due to contact and interconnection are included. Most importantly, the developed mobility model easily takes the device structure and process into consideration. In order to demonstrate the capabilities of the developed model, the structure- and process-oriented parameters in the present mobility model are calculated explicitly for an n-channel enhancement-mode MOSFET with single-channel boron implantation. Moreover, n-channel MOSFETs with different channel lengths fabricated in a production line by using a set of test keys have been characterized and the measured mobilities have been compared to the model. Excellent agreement has been obtained for all ranges of the fabricated channel lengths, which strongly support the accuracy of the model.     

Anomalous I–V and pulse noise in reverse biased p–n junctions

A correlation between anomalous I-V characteristics and pulse noise in degraded p-n junctions under reverse bias conditions is found. In order to explain the appearance of two-polarity and multi-level pulse noise, a physical model of noise sources is proposed. The model is based on the presumptions that conduction channels and a p-inversion layer exist in degraded p-n junctions and that the current flow through the defects is modulated by traps adjacent to the defects. The experimental results for silicon field plated PIN photodiodes are in qualitative agreement with the model.     

Implant dose monitoring by MOS C–V measurement

The most critical parameter for deep sub-micron MOS field effect transistors is the threshold voltage, which is highly dependent on processing specifically, the ion implanted channel dose. Monitoring the channel doping on product wafers is highly desirable and is a major issue for process engineers. MOS C–V methods are widely used for process ramp up and monitoring and MOS C–V doping profiling is an introduced method for monitoring of low dose implants. However, the failure of the depletion approximation in the near surface region implies that conventional MOS C–V measurements yield erroneous doping profiles in that region. Integrating MOS C–V doping profiles yields only a partial implant dose excluding the important near surface dose portion. Here, we report a new approach, which enables the determination of the entire implant dose, taking into account the crucial surface region. Moreover, the MOS threshold voltage can be obtained self-consistently. The method is also applicable to MOS structures with ultra thin gate oxides.     

The stability of the CuInSe2 solar mini-module I–V characteristics under continuous and light/dark irradiation cycle tests

The stability of a CIS solar mini-module during a light/dark cycle and continuous light irradiation was investigated. Under both test conditions, the maximum power was improved during the early stages, then subsequently deteriorated. The major factors causing this phenomenon were changes in the fill-factor and open circuit voltage. The details of some parameters relevant to these factors are considered herein. In addition, the dependencies of light intensity and temperature in terms of the I–V characteristics were measured.     

Simulation and experimental results on the forward J–V characteristic of Al implanted 4H–SiC p–i–n diodes

In this work the forward J–V characteristics of 4H–SiC p–i–n diodes are analysed by means of a physics based device simulator tuned by comparison to experimental results. The circular devices have a diameter of 350 μm. The implanted anode region showed a plateau aluminium concentration of 6×10¹⁹ cm⁻³ located at the surface with a profile edge located at 0.2 μm and a profile tail crossing the n-type epilayer doping at 1.35 μm. Al atom ionization efficiency was carefully taken into account during the simulations. The final devices showed good rectifying properties and at room temperature a diode current density close to 370 A/cm² could be measured at 5 V. The simulation results were in good agreement with the experimental data taken at temperatures up to about 523 K in the whole explored current range extending over nine orders of magnitude. Simulations also allowed to estimate the effect of a different p⁺ doping electrically effective profile on the device current handling capabilities.     

Prediction of dielectric reliability from I–V characteristics: Poole–Frenkel conduction mechanism leading to √E model for silicon nitride MIM capacitor

Two assumptions lead to a correlation between the leakage mechanism of a dielectric and dielectric reliability: the degradation of the dielectric is a direct cause of the leakage current flowing through the dielectric and breakdown occurs after a critical charge has been forced through the dielectric. The field and temperature dependence of the leakage current mechanism then determine the voltage acceleration factor and the activation energy of TDDB experiments. This simple physical model describes the reliability of metal insulator metal (MIM) capacitors with PECVD SiN remarkably well. The current conduction mechanism is described by Poole–Frenkel theory, leading to a √E dependence of the time to breakdown on the applied electric field. The model predicts correctly the voltage acceleration factor and its temperature dependence and the activation energy.     

Temperature dependent current–voltage (I–V) characteristics of Au/n-Si (1 1 1) Schottky barrier diodes with PVA(Ni,Zn-doped) interfacial layer

Current–voltage (I–V) characteristics of Au/PVA/n-Si (1 1 1) Schottky barrier diodes (SBDs) have been investigated in the temperature range 80–400 K. Here, polyvinyl alcohol (PVA) has been used as interfacial layer between metal and semiconductor layers. The zero-bias barrier height (Φ_B0) and ideality factor (n) determined from the forward bias I–V characteristics were found strongly dependent on temperature. The forward bias semi-logarithmic I–V curves for different temperatures have an almost common cross-point at a certain bias voltage. The values of Φ_B0 increase with the increasing temperature whereas those of n decrease. Therefore, we have attempted to draw Φ_B0 vs. q/2kT plot in order to obtain evidence of a Gaussian distribution (GD) of the barrier heights (BHs). The mean value of BH and standard deviation (σ₀) were found to be 0.974 eV and 0.101 V from this plot, respectively. Thus, the slope and intercept of modified vs. q/kT plot give the values of and Richardson constant (A^?) as 0.966 eV and 118.75 A/cm²K², respectively, without using the temperature coefficient of the BH. This value of A^* 118.75 A/cm²K² is very close to the theoretical value of 120 A/cm²K² for n-type Si. Hence, it has been concluded that the temperature dependence of the forward I–V characteristics of Au/PVA/n-Si (1 1 1) SBDs can be successfully explained on the basis of the Thermionic Emission (TE) theory with a GD of the BHs at Au/n-Si interface.     

The effect of small-signal AC voltages on C–V characterization and parameter extraction of SiO2 thin films

The effect of different small-signal ac voltage amplitudes on C–V curves characterized by thin SiO₂ based p-type MOS capacitor with aluminum gate is reported. When the small-signal ac voltage is comparable to the gate bias, the thickness of SiO₂ thin films extracted from the accumulation capacitance is found to be independent of small-signal ac voltage amplitudes, but the flat band voltage shift and interface state density associated with the variation of depletion layer capacitance are dependent on small-signal ac voltage amplitudes. They all increase with the small-signal ac voltage amplitudes. The experimental results reveal that the optimum small-signal ac voltage should be less than 100 mV. The mechanisms involving the depletion layer changes with small-signal ac voltages in SiO₂ thin films are also discussed in this paper.     

Design of field-plate terminated 4H-SiC Schottky diodes using high-k dielectrics

Silicon carbide (SiC) field-plate terminated Schottky diodes using silicon dioxide (SiO₂) dielectric experience high electric field in the insulator and premature dielectric breakdown, attributed to the lower dielectric constant of the oxide. To alleviate this problem we explore the use of high-k dielectrics, silicon nitride (Si₃N₄) and sapphire (Al₂O₃), on 4H-SiC by numerical simulations using Medici. The simulation results show significant improvement in blocking voltages by as much as 30% and much lower electric field within the dielectrics. There is also a slight reduction in the specific-on resistance (R_sp-on) and a small increase in the forward current density due to the formation of an accumulation layer in SiC where the metal overlaps the dielectric. This effect is enhanced with increasing dielectric constant and decreasing dielectric thickness for a given dielectric.     

Characterization of charge trapping in SiO2/Al2O3 dielectric stacks by pulsed C–V technique

In this work, charge trapping in SiO₂/Al₂O₃ dielectric stacks is characterized by means of pulsed capacitance–voltage measurements. The proposed technique strongly reduces the measurement time and, as a consequence, the impact of charge trapping on the measurement results. Flat band voltage shift and fast current transient during short stress pulses are systematically monitored and the centroid and the amount of the trapped charge are extracted using a first-order model.     

An analytical parasitic resistance dependent Id–Vd model for planar doped InAlAs/InGaAs/InP HEMT using non-linear charge control analysis

An analytical parasitic resistance dependent model for the current voltage characteristics for InAlAs/InGaAs/InP HEMT is proposed. The model uses a new polynomial dependence of sheet carrier concentration on gate voltage to calculate I_d–V_d characteristics and has been extended to obtain transconductance, output conductance and cut-off frequency of the device. A maximum cut-off frequency of 83 and 175 GHz was obtained for channel length of 0.25 and 0.1 μm, respectively. Close agreement with published results confirms the validity of our approach.     

Effect of the design and technology factors on electrical characteristics of the Au/Ti-n-GaAs Schottky diodes

Electrical properties of the Au/Ti-n-GaAs Schottky diodes are studied in relation to the production technology. The forward and reverse current-voltage characteristics of the diodes at low electric fields are analyzed on the basis of the mechanism of thermionic emission through the metal-semiconductor barrier. It is assumed that an increase in the reverse currents in the voltage range from 20 to 60 V can be accounted for by the Pool-Frenkel effect. The excess reverse currents at voltages higher than 60 V are caused by the phonon-assisted tunneling via deep states in the depletion region of the semiconductor.     

Temperature dependent dielectric studies of Ni/n-GaP Schottky diodes by capacitance and conductance measurements

The dielectric properties of Ni/n-GaP Schottky diode were investigated in the temperature range 140–300 K by capacitance–voltage (C–V) and conductance–voltage (G/ω–V) measurements. The effect of temperature on series resistance (R_s) and interface state density (N_ss) were investigated. The dependency of dielectric constant (ε′), dielectric loss (ε′′), loss tangent (tan δ), ac conductivity (σ_ac), real (M′) and imaginary (M′′) parts of the electric modulus over temperature were evaluated and analyzed at 1 MHz frequency. The temperature dependent characteristics of ε′ and ε′′ reveal the contribution of various polarization effects, which increases with temperature. The Arrhenius plot of σ_ac shows two activation energies revealing the presence of two distinct trap states in the chosen temperature range. Moreover, the capacitance–frequency (C–f) measurement over 1 kHz to 1 MHz was carried out to study the effect of localized interface states.