Automated synthesis of multiple analog circuits using evolutionary computation for redundancy-based fault-tolerance

Analog circuits are one of the most important parts of modern electronic systems and the failure of electronic hardware presents a critical threat to the completion of modern aircraft, spacecraft, and robot missions. Compared to digital circuits, designing fault-tolerant analog circuits is a difficult and knowledge-intensive task. A simple but powerful method for robustness is a redundancy approach to use multiple circuits instead of single one. For example, if component failures occur, other redundant components can replace the functions of broken parts and the system can still work. However, there are several research issues to make the redundant system automatically. In this paper, we used evolutionary computation to generate multiple analog circuits automatically and then we combined the solutions to generate robust outputs. Evolutionary computation is a natural way to produce multiple redundant solutions because it is a population-based search. Experimental results on the evolution of the low-pass, high-pass and band-stop filters show that the combination of multiple evolved analog circuits produces results that are more robust than those of the best single circuit.     

On figures of merit in reversible and quantum logic designs

Five figures of merit including number of gates, quantum cost, number of constant inputs, number of garbage outputs, and delay are used casually in the literature to compare the performance of different reversible or quantum logic circuits. In this paper we propose new definitions and enhancements, and identify similarities between these figures of merit. We evaluate these measures to show their strength and weakness. Instead of the number of gates, we introduce the weighted number of gates, where a weighting factor is assigned to each quantum or reversible gate, based on its type, size and technology. We compare the quantum cost with weighted number of gates of a circuit and show three major differences between these measures. It is proved that it is not possible to define a universal reversible logic gate without adding constant inputs. We prove that there is an optimum value for number of constant inputs to obtain a circuit with minimum quantum cost. Some reversible logic benchmarks have been synthesized using Toffoli and Fredkin gates to obtain their optimum values of number of constant inputs. We show that the garbage outputs can also be used to decrease the quantum cost of the circuit. A new definition of delay in quantum and reversible logic circuits is proposed for music line style representation. We also propose a procedure to calculate the delay of a circuit, based on the quantum cost and the depth of the circuit. The results of this research show that to achieve a fair comparison among designs, figures of merit should be considered more thoroughly.      

Surrogate measures to optimize structures for robust and predictable progressive failure

Optimizing complex structures for robust and predictable progressive failure using probabilistic approaches is computationally expensive. In this paper we investigate the progressive failure characteristics of structures subjected to random variability and deduce patterns to identify surrogate measures that correlate with robustness and predictability of the design’s progressive failure. The procedure is demonstrated for the optimization of robustness and predictability in progressive failure of truss structures. Deterministic optimization of trusses was used to generate candidate designs to compare and contrast robustness and predictability. The stochastic analyses of the candidate designs are then used to identify surrogate features that correlate to robustness and predictability of progressive failure response. These features are converted to numerical surrogate objectives or constraints and used in optimization to demonstrate their effectiveness and computational efficiency. The example shows that surrogate measures can be developed for robustness and predictability optimization, and that such measures are computationally efficient compared to robustness optimization using sampling based methods.     

Synthesis of operational transconductance amplifier-based analogfuzzy functional blocks and its application

A synthesis of analog fuzzy functional blocks (a complementary membership function circuit, a maximum circuit, a complementary maximum circuit, and a defuzzifier circuit) based on operational transconductance amplifiers (OTA's) is presented. The complementary membership function circuit and the maximum circuit are synthesized from the formulations using bounded-difference operations. The defuzzifier circuit is synthesized as the follower-aggregation circuit composed of multiplier-type OTA's, SPICE simulations showed that the proposed fuzzy functional blocks feature high-speed operations and low power consumption. The complementary membership function circuit, the maximum circuit, and the complementary maximum circuit were built with discrete components and commercially available OTA's, and the performances of these circuits were confirmed by experiments. As an application, a singleton fuzzy controller with 3×3 rules is synthesized using the proposed circuits. The simulation of this controller showed that the inference speed of the order of 15 MRPS (rules per second) is easily realizable     

Improved error detection performance of logic implication checking in FPGA circuits

Increased feature scaling to achieve high performance of miniaturized circuits has increased concerns related to their reliability as smaller circuits age faster. This means that more computational errors due to defects are expected in modern nanoscale circuits. Logic implication checking is a concurrent error detection technique that can detect a partial number of these errors at reduced hardware costs. However, implications-based error detection suffers from a low error coverage in FPGA-implemented circuits making it useless for any practical purposes. In this paper, we identify the reasons for a degraded performance of implication checking in FPGAs and propose multi-wire implications towards achieving better error detection probabilities (P_detection). The addition of multi-wire implications boosts the number of candidate implications and contributes more valuable implications thereby increasing the average P_detection achieved by almost 1.7 times at around 65.7% with only a 25% increase in the average area overhead for the given test circuits. Moreover, we show that the efficiency of implications in detecting errors not only varies from one circuit to another but that it also depends largely on the specific implementation of the circuit under test as supported through analytic analyses and comparisons between experimental results obtained from hardware fault injection of the implemented circuits and fault simulations on corresponding circuit netlists.     

Explorations in design space: unconventional electronics designthrough artificial evolution

Three hypotheses are formulated. First, in the “design space” of possible electronic circuits, conventional design methods work within constrained regions, never considering most of the whole. Second, evolutionary algorithms can explore some of the regions beyond the scope of contentional methods, raising the possibility that better designs can be found. Third, evolutionary algorithms can in practice produce designs that are beyond the scope of conventional methods, and that are in some sense better. A reconfigurable hardware controller for a robot is evolved, using a conventional architecture with and without orthodox design constraints. In the unconstrained case, evolution exploited the enhanced capabilities of the hardware. A tone discriminator circuit is evolved on an FPGA without constraints, resulting in a structure and dynamics that are foreign to conventional design and analysis. The first two hypotheses are true. Evolution can explore the forms and processes that are natural to the electronic medium, and nonbehavioral requirements can be integrated into this design process, such as fault tolerance. A strategy to evolve circuit robustness tailored to the task, the circuit, and the medium, is presented. Hardware and software tools enabling research progress are discussed. The third hypothesis is a good working one: practically useful but radically unconventional evolved circuits are in sight     

基于DWT域的半脆弱“鸡尾酒水印”算法

随着数字图像技术和网络的发展,数字图像的盗版现象日益猖獗,于是数字水印技术应运而生。半脆弱水印技术主要是解决图像内容认证的问题,一般的半脆弱水印都具有鲁棒性不足的缺点。提出一种新的半脆弱“鸡尾酒”水印算法进行图像认证。从水印嵌入的调制策略入手,在图像中隐藏两种正向和负向互补的数字水印,使得水印在受到攻击时至少有一种能够存活,以提高半脆弱水印的鲁棒性。实验证明,这种水印算法具有较好的鲁棒性,能够经受各类攻击。     

Computing motion using analog VLSI vision chips: An experimental comparison among different approaches

We have designed, built and tested a number of analog CMOS VLSI circuits for computing 1-D motion from the time-varying intensity values provided by an array of on-chip phototransistors. We present experimental data for two such circuits and discuss their relative performance. One circuit approximates the correlation model while a second chip uses resistive grids to compute zero-crossings to be tracked over time by a separate digital processor. Both circuits integrate image acquisition with image processing functions and compute velocity in real time. For comparison, we also describe the performance of a simple motion algorithm using off-the-shelf digital components. We conclude that analog circuits implementing various correlation-like motion algorithms are more robust than our previous analog circuits implementing gradient-like motion algorithms.     

三值量子基本门及其对量子Fourier变换的电路实现

理论上可以把量子基本门组合在一起来实现任何量子电路和构建可伸缩的量子计算机。但由于构建量子线路的量子基本门数量庞大,要正确控制这些量子门十分困难。因此,如何减少构建量子线路的基本门数量是一个非常重要和非常有意义的课题。提出采用三值量子态系统构建量子计算机,并给出了一组三值量子基本门的功能定义、算子矩阵和量子线路图。定义的基本门主要包括三值量子非门、三值控制非门、三值Hadamard门、三值量子交换门和三值控制CR_k门等。通过把量子Fourier变换推广到三值量子态,成功运用部分三值量子基本门构建出能实现量子Fourier变换的量子线路。通过定量分析发现,三值量子Fourier变换的线路复杂度比二值情况降低了至少50%,表明三值量子基本门在降低量子计算线路复杂度方面具有巨大优势。     

Is Asynchronous Logic More Robust Than Synchronous Logic?

With clock rates beyond 1 GHz, the model of a systemwide synchronous clock is becoming difficult to maintain; therefore, asynchronous design styles are increasingly receiving attention. While the traditional synchronous design style is well-proven and backed up by a rich field experience, comparatively little is known about the properties of asynchronous circuits in practical application. In the face of increased transient fault rates, robustness is a crucial property, and from a conceptual view, the so-called “delay-insensitive” asynchronous design approaches promise to be more robust than synchronous ones, since their operation does not depend on tight timing margins, and data are two-rail coded. A practical assessment of asynchronous designs in fault-injection (FI) studies, however, can rarely be found, and there is a lack of adequate methods and tools in this particular domain. Therefore, the objective of this work is 1) to provide a common approach for efficient and accurate FI in synchronous and in asynchronous designs, and 2) to experimentally compare the robustness of both synchronous and asynchronous designs. To this end, a synchronous 16-bit processor as well as its asynchronous (delay insensitive) equivalent are subjected to signal flips and delay faults. The results of over 489 million experiments are summarized and discussed, and a detailed discussion on the specific properties of the chosen asynchronous design style is given.     

Designing new ternary reversible subtractor circuits

The reducing of the width of quantum reversible circuits makes multiple-valued reversible logic a very promising research area. Ternary logic is one of the most popular types of multiple-valued reversible logic, along with the Subtractor, which is among the major components of the ALU of a classical computer and complex hardware. In this paper the authors will be presenting an improved design of a ternary reversible half subtractor circuit. The authors shall compare the improved design with the existing designs and shall highlight the improvements made after which the authors will propose a new ternary reversible full subtractor circuit. Ternary Shift gates and ternary Muthukrishnan–Stroud gates were used to build such newly designed complex circuits and it is believed that the proposed designs can be used in ternary quantum computers. The minimization of the number of constant inputs and garbage outputs, hardware complexity, quantum cost and delay time is an important issue in reversible logic design. In this study a significant improvement as compared to the existing designs has been achieved in as such that with the reduction in the number of ternary shift and Muthukrishnan-Stroud gates used the authors have produced ternary subtractor circuits.     

A circuit representation technique for automated circuit design

We present a method of automatically generating circuit designs using evolutionary search and a set of circuit constructing primitives arranged in a linear sequence. This representation has the desirable property that virtually all sets of circuit-constructing primitives result in valid circuit graphs. While this representation excludes certain circuit topologies, it is capable of generating a rich set of them including many of the useful topologies seen in hand-designed circuits. Our system allows circuit size (number of devices), circuit topology, and device values to he evolved. Using a parallel genetic algorithm and circuit simulation software, we present experimental results as applied to three analog filter and two amplifier design tasks. In all tasks, our system is able to generate circuits that achieve the target specifications. Although the evolved circuits exist as software models, detailed examinations of each suggest that they are electrically well behaved and thus suitable for physical implementation. The modest computational requirements suggest that the ability to evolve complex analog circuit representations in software is becoming more approachable on a single engineering workstation     

Feasibility analysis for robustness quantification by symbolic model checking

We propose and investigate a robustness evaluation procedure for sequential circuits subject to particle strikes inducing bit-flips in memory elements. We define a general fault model, a parametric reparation model and quantitative measures reflecting the robustness capability of the circuit with respect to these fault and reparation models. We provide algorithms to compute these metrics and show how they can be interpreted in order to better understand the robustness capability of several circuits (a simple circuit coming from the VIS distribution, circuits from the itc-99 benchmarks and a CAN-Bus interface).     

On the design of reconfigurable multipliers for integer and Galois field multiplication

Multiplication is a vital function for practically any DSP system. Some common DSP algorithms require different multiplication types, specifically integer or Galois Field (GF) multiplication. Since both functions share similarities in their structures, the potential is given for efficiently combining them in a single reconfigurable VLSI circuit, leading to competitive designs in terms of area, performance, and power consumption. This will be analysed and discussed in detail for 10 reconfigurable multiplier alternatives that are based on different strategies for the combination of integer and GF multiplication. Each result is compared to a reference architecture, showing area savings of up to 20% at a marginal increase in delay, and an increase in power consumption of 25% and above. This gives evidence that function-specific reconfigurable circuits can achieve considerable improvements in at least one design objective with only a moderate degradation in others. From this perspective, function-specific reconfigurable circuits can be considered feasible alternatives to standard ASIC solutions.     

Advanced fault collapsing [logic circuits testing]

The partitioning of faults into equivalence classes so that only one representative fault per class must be explicitly considered in fault simulation and test generation, called fault collapsing, is addressed. Two types of equivalence, which are relevant to the work reported, are summarized. New theorems on fault equivalence and dominance, forming the basis of an algorithm that collapses all the structurally equivalent faults in a circuit, plus many of the functionally equivalent faults, are presented. Application of the algorithm to a set of benchmark circuits establishes that identification of functionally equivalent faults is feasible, and that, in some cases, they are a large fraction of the faults in a circuit. The collapsing algorithm applies not only to combinational designs but to synchronous sequential circuits as well     

Creating geometrically robust designs for highly sensitive problems using topology optimization

Resonance and wave-propagation problems are known to be highly sensitive towards parameter variations. This paper discusses topology optimization formulations for creating designs that perform robustly under spatial variations for acoustic cavity problems. For several structural problems, robust topology optimization methods have already proven their worth. However, it is shown that direct application of such methods is not suitable for the acoustic problem under consideration. A new double filter approach is suggested which makes robust optimization for spatial variations possible. Its effect and limitations are discussed. In addition, a known explicit penalization approach is considered for comparison. For near-uniform spatial variations it is shown that highly robust designs can be obtained using the double filter approach. It is finally demonstrated that taking non-uniform variations into account further improves the robustness of the designs.     

Sequential circuit realizations with pulse input fundamental mode sequential circuits

Summary This paper gives a unified treatment for electronic sequential circuit realizations and suitable procedures for synthesizing them. This is done by showing that every sequential circuit operating in synchronous mode can be transformed into an equivalent sequential circuit operating in fundamental mode with the same number of internal states. The basic idea is to consider, for both the major types of sequential circuits, circuits having pulse inputs—PS circuits for sequential circuits operating in synchronous mode, andPF circuits for sequential circuits operating in fundamental mode—and to investigate the relationship between them. A concurrent and a self concurrent operation is defined forPF circuits, and it is shown that any synchronon mode sequential circuit can be transformed into an equivalent normal or self-concurrentPF circuit realization inherently free ofessential hazards and critical races. Moreover, it is seen that static hazards that can influence the circuit operation can be detected and eliminated by formal methods. The circuit realizations discussed in this paper are composed by a defined number of subcircuits, and it is shown that these subcircuits can in turn be decomposed to obtain circuit realizations with flip-flops or register elements. Finally, it is shown that by similar methods level-input fundamental mode sequential circuits can also be transformed into self-concurrentPF circuit realizations in order to eliminate essential hazards and critical races. This paper has been communicated at the ?Colloque d'Algebre de Boole?, Grenoble, January 11–15, 1965, and reported in the C.S.C.E. Internal Report II. 9. May, 1965.     

复杂系统可靠控制中的潜在问题互连神经网络分析方法

潜在问题是影响大型复杂系统安全性、可靠性的重要因素. 神经网络是一种新的潜在问题分析方法, 但是其分析结果难以解释. 本文提出了一种基于电路结构的神经网络模型 (Neural network model based on circuit architecture, CArNN), 将 CArNN 作为个体进行集成, 形成神经网络集成用于潜在问题分析. 对 CArNN 模型的鲁棒性进行了分析, 提出了两个保证模型鲁棒性的约束条件. 利用此方法对一个经典电路进行了分析, 结果显示, 此方法对潜在电路的正确识别率达到94\%.     

Open-ended evolution to discover analogue circuits for beyond conventional applications

Analogue circuits synthesised by means of open-ended evolutionary algorithms often have unconventional designs. However, these circuits are typically highly compact, and the general nature of the evolutionary search methodology allows such designs to be used in many applications. Previous work on the evolutionary design of analogue circuits has focused on circuits that lie well within analogue application domain. In contrast, our paper considers the evolution of analogue circuits that are usually synthesised in digital logic. We have developed?four computational circuits, two voltage distributor circuits and a time interval metre circuit. The approach, despite its simplicity, succeeds over the design tasks owing to the employment of substructure reuse and incremental evolution. Our findings expand the range of applications that are considered suitable for evolutionary electronics.     

Reversible binary subtractor design using quantum dot-cellular automata

In the field of nanotechnology, quantum dot-cellular automata (QCA) is the promising archetype that can provide an alternative solution to conventional complementary metal oxide semiconductor (CMOS) circuit. QCA has high device density, high operating speed, and extremely low power consumption. Reversible logic has widespread applications in QCA. Researchers have explored several designs of QCA-based reversible logic circuits, but still not much work has been reported on QCA-based reversible binary subtractors. The low power dissipation and high circuit density of QCA pledge the energy-efficient design of logic circuit at a nano-scale level. However, the necessity of too many logic gates and detrimental garbage outputs may limit the functionality of a QCA-based logic circuit. In this paper we describe the design and implementation of a DG gate in QCA. The universal nature of the DG gate has been established. The QCA building block of the DG gate is used to achieve new reversible binary subtractors. The proposed reversible subtractors have low quantum cost and garbage outputs compared to the existing reversible subtractors. The proposed circuits are designed and simulated using QCA Designer-2.0.3.