Statistical estimation of delay fault detectabilities and fault grading

In this paper we present a technique to statistically estimate transition delay and path delay fault coverage. The basic method is an extension of STAFAN to include delay faults. By partitioning a combinational circuit into non-overlapping fanout free logic cones, we accurately calculate the transition sensitization controllabilities of 0 1 and 1 0 transitions of the lines within a fanout free logic cone to the output of the fanout free logic cone for each fanout free logic cone. A strategy to calculate the transition observabilities of fanout stems is proposed. The detectability of a path delay fault is evaluated as the product of the observabilities of the input line to its head gate within each fanout free logic cone on the path multiplied by the transition controllability of the path. When compared with the fault simulations, the estimations of transition delay fault coverage are within 2.3%. Also, the technique gives reasonably good path delay fault coverage estimation for large fault set of the ISCAS85 benchmark circuits.     

诊断权衡优化测试性分析技术

现今对于电子设备进行故障诊断以及后续PHM的需求越来越多,本文结合测试性分析的流程,提出了一种面向诊断的测试性分析方法,并使用开发的软件对某型号的发电机进行测试性建模与分析,按照给出的诊断策略进行测试可以取得比较好的效果。     

基于嵌入式M C U的计算器电路的可测性设计

给出了两种可测性设计方法,详细介绍了基于4位嵌入式MCU的计算器电路的可测性设计,包括ROM内容测试和模块划分,通过这些设计,大大提高了电路的可控制性和可观察性。     

False-Path Removal Using Delay Fault Simulation

Some false paths are caused by redundant stuck-at faults. Removal of those stuck-at faults automatically eliminates such false paths from the circuit. However, there are other false paths that are not associated with any redundant stuck-at fault. All segments of such a false path are shared with other testable paths. We focus on the elimination of this type of false paths. We use a non-enumerative path delay fault simulator based on the path status graph (PSG) data-structure, which duplicates selected gates to separate the detected and undetected path delay faults. The expanded circuit may contain new redundant stuck-at faults, corresponding to those undetected paths that are false. This happens because the expanded circuit has some new interconnects with only false paths passing through them. Such links become the sites for redundant stuck-at faults. Removal of these redundant faults eliminates false paths. The reported results show that the quality of the result may depend on the coverage of testable paths by the vectors that are simulated. When non-enumerative path delay simulation and implication-based redundancy removal techniques are used, the present procedure of false-path elimination can be applied to very large circuits.     

Constant testability of combinational cellular tree structures

This paper presents various approaches for testing cellular tree structures with a constant number of test vectors, that is, independent of the number of cells (size of the tree). The necessary and sufficient conditions which must be satisfied in the state table of a basic combinational cell for achieving C-testability and one-step C-testability in a homogeneous tree, are proved. The design modifications required to accomplish this objective in arbitrary cells, are discussed. It is proved that three additional rows and three additional columns are needed in the state table of a cell; the characteristics of the additional states are also analyzed. The complexity of the proposed testing process is quadratic with respect to the number of entries in the state table of a cell. Illustrative examples are also given.This research supported in part by grants from NATO and NSF.     

Cell delay fault testing for iterative logic arrays

C-testable iterative logic arrays for cell-delay faults are proposed. A cell delay fault occurs if and only if an input transition can not be propagated to the cell's output through a path in the cell in a specified clock period. The set of single-path propagation, hazard-free robust tests that completely check all the paths in a cell is first derived, and then necessary conditions for sending this test set to each cell in the array and simultaneously propagating the fault effects to the primary outputs are given. Test set minimization can be solved in a similar way as for the fault cover problem. We use the pipelined array multiplier as an example, and show that it is C-testable with 214 two-pattern tests. With a small number of additional patterns, all the combinational faults can be detected pseudoexhaustive.     

Partial scan flip-flop selection by use of empirical testability

Partial serial scan as a design for testability technique permits automatic generation of high fault coverage tests for sequential circuits with less hardware overhead and less performance degradation than full serial scan. The objective of the partial scan flip-flop selection method proposed here is to obtain maximum fault coverage for the number of scan flip-flops selected. Empirical Testability Difference (ETD), a measure of potential improvement in the testability of the circuit, is used to successively select one or more flip-flops for addition or deletion of scan logic. ETD is calculated by using testability measures based on empirical evaluation of the circuit with the acutal automatic test pattern generation (ATPG) system. In addition, once such faults are known, ETD focuses on the hard-to-detect faults rather than all faults and uses heuristics to permit effective selection of multiple flip-flops without global optimization. Two ETD algorithms have been extensively tested by using FASTEST ATPG [1, 2] on fourteen of the ISCAS89 [3] sequential circuits. The results of these tests indicate that ETD yields, on average, 35% fewer uncovered detectable faults for the same number of scanned flip-flops or 27% fewer scanned flip-flops for comparable fault coverage relative to cycle-breaking methods.This work was performed while the author was with the University of Wisconsin-Madison.     

一种基于模型的测试性分析评估方法

产品可测试性设计是否满足测试性要求需要进行测试性分析和评估,基于模型的测试性分析评估方法因为它独特的优势被广泛用于产品测试性辅助分析之中。针对多层次系统产品的结构功能特点,提出一种基于相关性数学模型和多信号流图模型的测试性建模分析评估方法。该方法分析目标系统的测试性模型要素,建立了两测试性模型,以测试性工程和维修系统软件(TEAMS)为平台,通过软件仿真评估对模型进行校验,使其符合真实系统的故障传播关系和故障定位过程,在此基础上改进测试性设计,使其达到测试性定量指标。运用该方法对某装备电子系统部分进行实例分析,仿真结果验证了该方法的有效性和可行性,结论表明:基于相关性数学模型和多信号流图模型的测试性建模方法能够满足装备电子系统的测试性分析评估需求。     

An efficient built-in self test method for robust path delay fault testing

Single Input Change (SIC) testing has been proposed for robust path delay fault testing. In this letter a new Built-In Self Test (BIST) method for SIC vector generation is presented. The proposed method compares favourably to the previously proposed methods for SIC pattern generation with respect to hardware overhead and time required for completion of the test.     

数字调谐系统芯片DTSO614的可测性设计

介绍了集成电路可测性设计的概念和分类方法,然后以数字调谐系统芯片DTS0614为例,具体介绍了其中的一种即针对性可测性设计方法,包括模块划分、增加控制线和观察点.最后给出了提高电路可测性的另一种方法--内建自测试方法.     

Efficient multiple path propagating tests for delay faults

This paper presents a test generation procedure for obtainingmaximal multiple-path-propagating robust tests, which detect the largest possible number of path faults simultaneously. Specialized heuristics are used to facilitate the generation of such tests in two-level circuits, and methods are given for extensions to multi-level circuits. Experimental results are presented to demonstrate the efficacy of this approach, which is seen to significantly reduce test-set lengths for path delay faults by generating highlyefficient robust tests. Limitations of the method are discussed, together with suggestions for future research.     

Design of a C-testable booth multiplier using a realistic fault model

A Booth multiplier is the most widely used type of multiplier. In this article, the testability issues involved in its design are discussed. In contrast to previous work, the fault model includes not only node stuck-at faults, but also transistor stuck-open and stuck-close faults. Moreover, as a result of adopting a hierarchical testability approach, the designed Booth multiplier turns out to be fully C-testable. To achieve this C-testability, only three additional controllable inputs are required, which results in a negligible area and delay overhead.Currently with Alcatel Bell Telephone.     

On Selecting Testable Paths in Scan Designs

We propose an efficient method to select a minimal set of testable paths in scan designs, such that every line in the circuit is covered by at least one of the longest testable paths that contain it (if there are any). The proposed path selection approach is based on a stepwise path expansion procedure that uses delay information and compact information about untestable paths to select longest paths while avoiding untestable paths. Techniques called delay analysis and delay-constrained path expansion are used to speedup the selection of paths to test. Compared to earlier approaches, the proposed approach is fast and it is guaranteed to find testable paths. Additionally the procedure also derives tests for the selected paths. Experimental results for ISCAS89 benchmark circuits using standard scan and broadside testing are presented to demonstrate the effectiveness of the proposed method.     

无线传感器网络中基于链路质量的路径延时分析

基于链路质量给出了路径满足实时性概率的上界,并证明了计算其上界的时间复杂度为指数级。另外在考虑链路质量的基础上,提出了一种在给定的延迟阈值下最大化端到端数据分组发送成功概率的贪心算法(RROP)。根据给定的延迟阈值和链路质量,RROP算法通过设置每跳链路的最大重传次数来优化端到端数据分组发送成功的概率。证明该算法能够在多项式时间内找到最优解并且通过该最优解获得路径满足实时性概率的一个近似最优的下界。实验结果表明给出的路径延迟分析上界和下界是准确的,并且提出的RROP算法在节省能量和满足实时性上比传统的方法能够获得高出10%以上的性能。     

故障树最小割集和最小路集在火箭故障诊断中的应用

基于提高火箭故障诊断效率的目的,采用故障树分析原理,结合火箭故障的诊断实际,研究了一种基于故障树最小割集和最小路集的火箭故障快速诊断决策方案。为系统的故障源搜寻提供了具体有效的测试步骤。并给出了应用实例。     

基于扫描的VLSI全速测试方法

当工艺进入到超深亚微米以下,传统的故障模型不再适用,必须对电路传输延迟引发的故障采用延迟故障模型进行全速测试.给出了常用的延迟故障模型,介绍了一种基于扫描的全速测试方法,并给出了全速测试中片上时钟控制器的电路实现方案.对芯片进行测试,可以直接利用片内锁相环电路输出的高速时钟对电路施加激励和捕获响应,而测试向量的扫描输入和响应扫描输出则可以采用测试机提供的低速时钟,从而降低了全速测试对测试机时钟频率的要求.最后,对于全速测试方案提出了若干建议.     

A fault simulation method: Parallel pattern critical path tracing

We present a fast fault simulation algorithm for combinational circuits which combines parallel pattern evaluation and critical path tracing. When the number of faults is large, our algorithm exploits the full advantages of critical path tracing. As fault dropping progresses, the overhead for critical path tracing surpasses its advantages. On the other hand, the efficiency of Parallel Pattern Single Fault Propagation (PPSFP) increases rapidly since relatively few undetected faults remain, and they tend to be inactive. To avoid the overhead of critical path tracing and achieve the advantages of PPSFP, dynamic update of node classes is used to produce a smooth transition from critical path tracing to PPSFP. By using this approach, we get high performance for both small and large numbers of test patterns. Also, preprocessing related to structure analysis is avoided while achieving almost all of its advantages.This work was supported in part by National Science Foundation grant MIP-9003292.     

Design of CMOS checkers with improved testability of bridging and transistor stuck-on faults

This work presents a design technique for CMOS static and dynamic checkers (to be used in self-checking circuits), that allows the detection of all internal single transistor stuck-on and bridging faults causing unacceptable degradations of the circuit dynamic performance (but not logical errors). Such a technique exploits simple voltage detector circuits to make sure that the intermediate faulty voltages inevitably produced by the faults of interest are always propagated at the checker output as logic errors.With the use of our technique, the main disadvantages of static checkers, so far preventing their use in practical applications, are overcome.The method has been applied to the particular case of two-rail (static as well as dynamic) checkers and its validity has been verified by means of electrical level simulations.