Characteristics of sub-100-nm p+/n junctions fabricatedby plasma immersion ion implantation

Plasma immersion ion implantation (PIII) is an efficient method for fabricating high-quality p⁺/n diodes with junction depths below 100 nm. SiF₄ is implanted to create an amorphous Si layer to retard B channeling and diffusion, and then BF₃ is implanted. Ultrashallow p⁺/n junctions are formed by annealing at 1060 °C for 10 s. With the shallow implants, no extended defects are observed in device or peripheral areas due to rapid outdiffusion of fluorine. Diode electrical characteristics yield forward ideality factor of 1.05-1.06 and leakage current density below 2 nA/cm ² in the diode bulk. Minority-carrier lifetime below the junction is greater than 250 μs     

Low-resistance bandgap-engineeredW/Si1-xGex/Si contacts

Bandgap-engineered W/Si_1-xGe_x/Si junctions (p⁺ and n⁺) with ultra-low contact resistivity and low leakage have been fabricated and characterized. The junctions are formed via outdiffusion from a selectively deposited Si_0.7Ge _0.3 layer which is implanted and annealed using RTA. The Si _1-xGe_x layer can then be selectively thinned using NH₄OH/H₂O₂/H₂O at 75°C with little change in characteristics or left as-deposited. Leakage currents were better than 1.6×10^-9 A/cm² (areal), 7.45×10^-12 A/cm (peripheral) for p⁺/n and 3.5×10^-10 A/cm² (peripheral) for n⁺/p. W contacts were formed using selective LPCVD on Si_1-xGe_x. A specific contact resistivity of better than 3.2×10^-8 Ω cm² for p ⁺/n and 2.2×10^-8 Ω cm² for n⁺/p is demonstrated-an order of magnitude n⁺ better than current TiSi₂ technology. W/Si_1-xGe _x/Si junctions show great potential for ULSI applications     

The influence of Ge-implantation on the electrical characteristicsof the ultra-shallow junction formed by using silicide as a diffusionsource

The electrical characteristics of ultra-shallow p⁺/n junctions formed by implanting a 60 keV Ge⁺ into a TiSi₂ layer have been studied. A very low reverse leakage current density (≅0.4 nA/cm² at -5 V) and a very good forward ideality factor n (≅1.001) were achieved in these ultra-shallow p ⁺/n junctions. From the secondary ion mass spectrometry (SIMS) analysis, the junction depth was measured to be 600 Å and the surface concentration was about 3 times higher than that of the conventional samples     

Process limitation and device design tradeoffs of self-aligned TiSi2 junction formation in submicrometer CMOS devices

Submicrometer CMOS transistors require shallow junctions to minimize punchthrough and short-channel effects. Salicide technology is a very attractive metallization scheme to solve many CMOS scaling problems. However, to achieve a shallow junction with a salicide structure requires careful optimization for device design tradeoffs. Several proposed techniques to form shallow titanium silicide junctions are critically examined. Boron, BF₂, arsenic, and phosphorus dopants were used to study the process parameters for low-leakage TiSi ₂ p⁺/n and n⁺/p junctions in submicrometer CMOS applications. It is concluded that the dopant drive-out (DDO) from the TiSi₂ layer to form a shallow junction scheme is not an efficient method for titanium salicide structure; poor device performance and unacceptably leaky junctions are obtained by this scheme. The conventional post junction salicide (PJS) scheme can produce shallow n⁺/p and p⁺/n junctions with junction depths of 0.12 to 0.20 μm below the TiSi₂. Deep submicrometer CMOS devices with channel length of 0.40 to 0.45 μm can be fabricated with such junctions     

Formation of 0.05-μm p+-n and n+-pjunctions by very low (<500 eV) ion implantation

The current-voltage (I-V) characteristics of ultrashallow p⁺ -n and n⁺-p diodes, obtained using very-low-energy (<500-eV) implantation of B and As, are presented. the p⁺-n junctions were formed by implanting B⁺ ions into n-type Si (100) at 200 eV and at a dose of 6×10¹⁴ cm^-2, and n⁺-p junctions were obtained by implanting As⁺ ions into p-type (100) Si at 500 eV and at a dose 4×10¹² cm^-2. A rapid thermal annealing (RTA) of 800°C/10 s was performed before I-V measurements. Using secondary ion mass spectrometry (SIMS) on samples in-situ capped with a 20-nm ²⁸Si isotopic layer grown by a low-energy (40 eV) ion-beam deposition (IBD) technique, the depth profiles of these junctions were estimated to be 40 and 20 nm for p⁺-n and n⁺-p junctions, respectively. These are the shallowest junctions reported in the literature. The results show that these diodes exhibit excellent I-V characteristics, with ideality factor of 1.1 and a reverse bias leakage current at -6 V of 8×10^-12 and 2×10^-11 A for p⁺-n and n⁺-p diodes, respectively, using a junction area of 1.96×10^-3 cm²     

Electrical characterization of ultra-shallow junctions formed bydiffusion from a CoSi2 layer

Ultra-shallow p⁺/n and n⁺/p junctions were fabricated using a Silicide-As-Diffusion-Source (SADS) process and a low thermal budget (800-900°C). A thin layer (50 nm) of CoSi₂ was implanted with As or with BF₂ and subsequently annealed at different temperatures and times to form two ultra-shallow junctions with a distance between the silicide/silicon interface and the junction of 14 and 20 nm, respectively. These diodes were investigated by I-V and C-V measurements in the range of temperature between 80 and 500 K. The reverse leakage currents for the SADS diodes were as low as 9×10 ^-10 A/cm² for p⁺/n and 2.7×10^-9 A/cm² for n⁺/p, respectively. The temperature dependence of the reverse current in the p ⁺/n diode is characterized by a unique activation energy (1.1 eV) over all the investigated range, while in the n⁺/p diode an activation energy of about 0.42 eV is obtained at 330 K. The analysis of the forward characteristic of the diodes indicate that the p⁺ /n junctions have an ideal behavior, while the n⁺/p junctions have an ideality factor greater than one for all the temperature range of the measurements. TEM delineation results confirm that, in the case of As diffusion from CoSi₂, the junction depth is not uniform and in some regions a Schottky diode is observed in parallel to the n⁺/p junction. Finally, from the C-V measurements, an increase of the diodes area of about a factor two is measured, and it is associated with the silicide/silicon interface roughness     

Formation of cobalt silicided shallow junction using implantinto/through silicide technology and low temperature furnace annealing

This work investigates the shallow CoSi₂ contacted junctions formed by BF₂⁺ and As⁺ implantation, respectively, into/through cobalt silicide followed by low temperature furnace annealing. For p⁺n junctions fabricated by 20 keV BF₂⁺ implantation to a dose of 5×10¹⁵ cm^-2, diodes with a leakage current density less than 2 nA/cm² at 5 V reverse bias can be achieved by a 700°C/60 min annealing. This diode has a junction depth less than 0.08 μm measured from the original silicon surface. For n⁺p junctions fabricated by 40 keV As⁺ implantation to a dose of 5×10¹⁵ cm^-2, diodes with a leakage current density less than 5 nA/cm² at 5 V reverse bias can be achieved by a 700°C/90 min annealing; the junction depth is about 0.1 μm measured from the original silicon surface. Since the As⁺ implanted silicide film exhibited degraded characteristics, an additional fluorine implantation was conducted to improve the stability of the thin silicide film. The fluorine implantation can improve the silicide/silicon interface morphology, but it also introduces extra defects. Thus, one should determine a tradeoff between junction characteristics, silicide film resistivity, and annealing temperature     

A novel self-aligned TiN formation by N2+implantation during two-step annealing Ti-salicidation for submicrometerCMOS technology application

A new technology of self-aligned TiN/TiSi₂ formation using N₂⁺ implantation during two-step annealing Ti-salicidation process has been developed. The formation of TiN was confirmed by RBS analysis. The leakage currents of n⁺/p junction diodes fabricated using this technology were measured to investigate the phenomena of Al spiking into Si-substrate. The measured reverse-bias leakage current of diode per unit junction area with Al/TiN/TiSi₂ contact is 1.2 nA/cm² at -5 V, which is less than all of reported data. Also it can sustain the annealing process for 30 min at 500°C. Thus, TiN formed with this technology process is suggested as a very effective barrier layer between TiSi₂ and Al for submicron CMOS technology applications     

The effect of Co incorporation on electrical characteristics of n+/p shallow junction formed by dopant implantation into CoSi2 and anneal

The impact of Co incorporation on the electrical characteristics has been investigated in n⁺/p junction formed by dopant implantation into CoSi₂ and drive-in anneal. The junctions were formed by As⁺ (30 or 40 keV, 1×10¹⁶ cm ^-2) implantation into 35 nm-thick CoSi₂ followed by drive-in annealing at 900°C for 30 s in an N₂ ambient. Deeper junction implanted by As⁺ at 40 keV was not influenced by the Co incorporation. However, for shallower junction implanted by As ⁺ at 30 keV, incorporation of Co atoms increased its leakage current, which were supposed to be dissociated from the CoSi₂ layer by silicide agglomeration during annealing. The mechanism of such a high leakage current was found to be Poole-Frenkel barrier lowering induced by high density of Co traps     

Electrical properties of Ga-implanted Si p+-n shallowjunctions fabricated by low-temperature rapid thermal annealing

p⁺-n shallow-junction diodes were fabricated using on-axis Ga⁶⁹ implantation into crystalline and preamorphized Si, at energies of 25-75 keV for a dose of 1×10¹⁵/cm ², which is in excess of the dosage (2×10¹⁴/cm²) required to render the implanted layer amorphous. Rapid thermal annealing at 550-600°C for 30 s resulted in the solid-phase epitaxial (SPE) regrowth of the implanted region accompanied by high Ga activation and shallow junction (60-130 nm) formation. Good diode electrical characteristics for the Ga implantation into crystalline Si were obtained; leakage current density of 1-1.5 nA/cm² and ideality factor of 1.01-1.03. Ga implantation into preamorphized Si resulted in a two to three times decrease in sheet resistance, but a leakage current density orders of magnitude higher     

The reverse anneal of junction characteristics in forming shallow p+-n junction by BF2+ implantation intothin Co films on Si substrate

Silicided shallow p⁺-n junctions, formed by BF₂ ⁺ implantation into thin Co films on Si substrates and subsequently annealed, showed a reverse anneal of junction characteristics in the temperature range between 550 and 600°C. The reverse anneal means behavior showing degradation of the considered parameters with increasing annealing temperature. A higher implant dosage caused a more distinct reverse anneal. The reverse anneal of electrical characteristics was associated with the reverse anneal of substitutional boron. A shallow p⁺-n junction with a leakage current density lower than 3 nA/cm₂, a forward ideality factor of better than 1.01, and a junction depth of about 0.1 μm was achieved by just a 550°C anneal     

Shallow-junction diode formation by implantation of arsenic andboron through titanium-silicide films and rapid thermal annealing

The performance of diodes fabricated on n-type and p-type Si substrates by implanting As or B through a low-resistivity titanium-silicide layer is discussed. The effects of varying the implant dose, energy, and postimplant thermal treatment were investigated. After implantation, a rapid thermal anneal was found to remove most of the implant damage and activate the dopants, which resulted in n⁺-p and p⁺-n junctions under a low-resistivity silicide layer. The n⁺-p junctions were as shallow as 1000 Å with reverse leakage currents as low as 5.5 μA/cm². A conventional furnace anneal resulted in a further reduction of this leakage. Shallow p⁺-n junctions could not be formed with boron implantation because of the large projected range of boron ions at the lowest available energy. Ti silicide films thinner than 600 Å exhibited a sharp rise in sheet resistivity after a furnace anneal, whereas thicker films exhibited more stable behavior. This is attributed to coalescence of the films. High-temperature furnace annealing diffused some of the dopants into the silicide film, reducing the surface concentrations at the TiSi₂ -Si interface     

Formation of TiN/TiSi2/p+-Si/n-Si by rapid thermal annealing (RTA) silicon implanted with boron through titanium

A low temperature method of fabricating conductive (3.5 Ω/ sq.) p⁺/n junction diodes possessing excellentI-Vcharacteristics with reverse-bias leakage less than -3 nA.cm^-2at -5 V is described. Single crystal n-type 〈100〉 Si is implanted with 60 keV¹¹B+through 0.028-µm thick sputtered Ti film. Rapid thermal annealing (RTA) in an N2ambient simultaneously forms a 0.36-µm deep p⁺/n junction and a 0.063-µm thick bilayer of TiN and TiSi2with a resistivity of 22 µΩ.cm. The electrical properties of these diodes are not degraded by annealing for 30 min at 500°C, suggesting that the outer layer of TiN is an effective diffusion barrier between TiSi2and Al.     

Optimization of the germanium preamorphization conditions forshallow-junction formation

Shallow p⁺-n and n⁺-p junctions were formed in germanium preamorphized Si substrates. Germanium implantation was carried out over the energy range of 50-125 keV and at doses from 3×10¹⁴ to 1×10¹⁵ cm^-2. p ⁺-n junctions were formed by 10-keV boron implantation at a dose of 1×10¹⁵ cm^-2. Arsenic was implanted at 50 keV at a dose of 5×10¹⁵ cm^-2 to form the n⁺-p junctions. Rapid thermal annealing was used for dopant activation and damage removal. Ge, B, and As distribution profiles were measured by secondary ion mass spectroscopy. Rutherford backscattering spectrometry was used to study the dependence of the amorphous layer formation on the energy and dose of germanium ion implantation. Cross-sectional transmission electron microscopy was used to study the residual defects formed due to preamorphization. Complete elimination of the residual end-of-range damage was achieved in samples preamorphized by 50-keV/1×10¹⁵ cm^-2 germanium implantation. Areal and peripheral leakage current densities of the junctions were studied as a function of germanium implantation parameters. The results show that high-quality p⁺-n and n⁺-p junctions can be formed in germanium preamorphized substrates if the preamorphization conditions are optimized     

Comparison of transformation to low-resistivity phase andagglomeration of TiSi2 and CoSi2

The phase transformation and stability of TiSi₂ on n ⁺ diffusions are investigated. Narrower n⁺ diffusions require higher anneal temperatures, or longer anneal times, than wider diffusions for complete transitions from the high-resistivity C49 phase to the low-resistivity C54 phase. A model is presented which explains this in terms of the probability of forming C54 nuclei on narrow diffusions and the influence of diffusion width on C54 grain size. The results are that more C49 and C54 nucleation events are required to completely transform narrow lines. For thin TiSi₂ (40 nm), there is a narrow process window for achieving complete transformation without causing agglomeration of the TiSi₂. The process window decreases with decreasing silicide thickness. A significantly larger process window is achieved with short-time rapid annealing. Similar studies are performed for CoSi₂ on n⁺ and p⁺ diffusions. No linewidth dependence is observed for the transformation from CoSi_x to CoSi₂. There is a broad process window from 575°C to 850°C using furnace annealing, for which the low-resistivity phase is obtained without causing agglomeration     

The effects of boron penetration on p+ polysilicon gatedPMOS devices

The penetration of boron into and through the gate oxides of PMOS devices which employ p⁺ doped polysilicon gates is studied. Boron penetration results in large positive shifts in V_FB , increased PMOS subthreshold slope and electron trapping rate, and decreased low-field mobility and interface trap density. Fluorine-related effects caused by BF₂ implantations into the polysilicon gate are shown to result in PMOS threshold voltage instabilities. Inclusion of a phosphorus co-implant or TiSi₂ salicide prior to gate implantation is shown to minimize this effect. The boron penetration phenomenon is modeled by a very shallow, fully-depleted p-type layer in the silicon substrate close to the SiO ₂/Si interface     

Suppression of cobalt silicide agglomeration using nitrogen(N2+) implantation

In this paper, the effects of nitrogen coimplantation with boron into p⁺-poly gate in PMOSFETs on the agglomeration effects of CoSi₂ are studied. The thermal stability of CoSi₂/poly-Si stacked layers can be significantly improved by using nitrogen implantation. Samples with 40-nm cobalt silicide (CoSi ₂) on 210-nm poly-Si implanted by 2×10¹⁵/cm ² N₂⁺ are thermally stable above 950°C for 30 s in N₂ ambient. If the dose of nitrogen is increased up to 6×10¹⁵/cm², the sheet resistance of CoSi₂ film is not increased at all, and TEM photographs show that the agglomeration of CoSi₂ film is completely suppressed     

Formation of TiSi2 and shallow junction byAs+ ion-beam mixing and infrared rapid heat treatment

A technique for forming shallow junctions with low-resistance silicide contacts developed for the use in VLSI with scaled MOSFETs is discussed. The salicide (self-aligned silicide) MOSFET gate and source-drain features self-aligned refractory metal silicide and are isolated from one another even without any insulating spacer on the gate sides. A critical step in such a MOSFET fabrication process is the ion implantation through metal silicidation technique, which includes As⁺ ion-beam-induced titanium-silicon interface mixing and infrared rapid heat treatment to form simultaneously the n⁺-p junction and a high-quality TiN covered TiSi₂ contact layer     

Rapid thermal annealing effects on Si p+-n junctionsfabricated by low-energy FIB Ga+ implantation

Effects of rapid thermal annealing (RTA) on sub-100 nm p⁺ -n Si junctions fabricated using 10 kV FIB Ga⁺ implantation at doses ranging from 10¹³ to 10¹⁵ cm ^-2 are reported. Annealing temperature and time were varied from 550 to 700°C and 30 to 120 s. It was observed that a maximum in the active carrier concentration is achieved at the critical annealing temperature of 600°C. Temperatures above and below the critical temperature were followed by a decrease in the active concentration, leading to a `reverse' annealing effect     

Shallow p+n junctions formed by using a two-stepannealing scheme with low thermal budget

Shallow p⁺n junctions have been formed by directly implanting BF₂ dopant into the Si substrate and then treating the samples by an annealing scheme with low thermal budget. A junction leakage smaller than 10 nA/cm² can be achieved by an annealing scheme that employs low-temperature long-time furnace annealing (FA) at 600°C for 3 h followed by medium-temperature rapid thermal annealing (RTA) at 800°C for 30 s. No considerable dopant diffusion is observed by using this low-thermal-budget annealing process. In addition, a moderate low-temperature annealing time of about 2-3 h should be employed to optimize the shallow p⁺n junction formed by this scheme. However, the annealing process that employs medium-temperature RTA followed by low-temperature FA treatment produces worse junctions than the annealing scheme that employs long-time FA at 600°C followed by RTA at 800°C