A sampling technique and its CMOS implementation with 1 Gb/sbandwidth and 25 ps resolution

This paper presents a technique and circuitry for high-resolution sampling of a digital waveform. Very fine sampling resolution is achieved by simultaneously propagating both data and clock signals through delay elements in such a way that resolution is controlled by the difference in the delay of clock and data signals. Delay units were designed using biased CMOS and differential CMOS inverters. A sampler circuit with 64 stages has been fabricated in 1.2 μm CMOS technology, and test results show a bandwidth of up to 1 Gb/s for the input data and a sampling resolution externally adjustable between 25 and 250 ps. The fabricated circuit has shown sampling stability, monotonicity in sampling, and uniformity in sampling resolution     

NRZ timing recovery technique for band-limited channels

Nonreturn-to-zero (NRZ) data, when transmitted over band-limited channels, suffer from the lack of zero crossings because the elongated tail of each pulse interferes with subsequent ones, causing intersymbol interference (ISI). An NRZ timing recovery technique working with a decision-feedback equalizer (DFE) recovers the clock from the equalized waveform and enables data transmission at a rate ten times higher than the channel bandwidth. The proposed timing recovery technique uses a data-triggered low-jitter phase detector to sustain phase locking even with 600 missing transitions, A data rate of 30 Mb/s in 3-MHz bandwidth is demonstrated with a peak-peak clock jitter of 2 ns using 2-μm CMOS     

A monolithic 156 Mb/s clock and data recovery PLL circuit using thesample-and-hold technique

The PLL circuit described here performs the function of data and clock recovery for random data patterns by using a sample-and-hold technique, and four component circuits (a phase comparator, a delay circuit, a voltage-controlled oscillator, and a S/H switch with a low-pass-filter) were specially designed to further stabilize the PLL operation. A test chip fabricated using Si bipolar process technology demonstrated error-free operation with an input of 2²³-1 PRBS data at 156 Mb/s. The rms data pattern jitter was reduced to only 1.2 degrees with only an external power supply bypass capacitor     

一种环路带宽自适应调整的时钟数据恢复电路

针对SONTE OC-192、PCIE3.0、USB3.2等协议在串行时钟数据恢复时对抖动容限、环路稳定时间的要求,提出了一种环路带宽自适应调整、半速率相位插值的时钟数据恢复电路(CDR)。设计了自适应控制电路,能适时动态调整环路带宽,实现串行信号时钟恢复过程中环路的快速稳定,提高了时钟数据恢复电路抖动容限。增加了补偿型相位插值控制器,进一步降低了数据接收误码率。该CDR电路基于55 nm CMOS工艺设计,数据输入范围为8～11.5 Gbit/s。采用随机码PRBS31对CDR电路的仿真测试结果表明,稳定时间小于400 ns,输入抖动容限大于0.55UI@10 MHz,功耗小于23 mW。     

A 20-mW 640-MHz CMOS Continuous-Time Σ∆ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB

A wide bandwidth continuous-time sigma-delta ADC, operating between 20 and 40 MS/s output data rate, is implemented in 130-nm CMOS. The circuit is targeted for applications that demand high bandwidth, high resolution, and low power, such as wireless and wireline communications, medical imaging, video, and instrumentation. The third-order continuous-time SigmaDelta modulator comprises a third-order RC operational-amplifier-based loop filter and 4-bit internal quantizer operating at 640 MHz. A 400-fs rms jitter LC PLL with 450-kHz bandwidth is integrated, generating the low-jitter clock for the jitter-sensitive continuous-time SigmaDelta ADC from a single-ended input clock between 13.5 and 40 MHz. To reduce clock jitter sensitivity, nonreturn-to-zero (NRZ) DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer and the degradation of modulator stability due to excess loop delay is avoided with a new architecture. The SigmaDelta ADC achieves 76-dB SNR, -78-dB THD, and a 74-dB SNDR or 12 ENOB over a 20-MHz signal band at an OSR of 16. The power consumption of the CT SigmaDelta modulator itself is 20 mW and in total the ADC dissipates 58 mW from the 1.2-V supply     

A monolithic 480 Mb/s parallel AGG/decision/clock-recovery circuitin 1.2-μm CMOS

A parallel architecture for high-data-rate AGC/decision/clock-recovery circuit, recovering digital NRZ data in optical-fiber receivers, is described. Improvement over traditional architecture in throughput is achieved through the use of parallel signal paths. An experimental prototype, fabricated in a 1.2-μm double-poly double-metal n-well CMOS process, achieves a maximum bit rate of 480 Mb/s. The chip contains variable gain amplifiers, clock recovery, and demultiplexing circuits. It yields a BER of 10^-11 with an 18 mV_p-p differential input signal. The power consumption is 900 mW from a single 5 V supply     

A 900-Mb/s CMOS data recovery DLL using half-frequency clock

A data recovery delay-locked loop (DILL) for nonreturn-to-zero (NRZ) data transmission is described. A reference clock is delayed for triggering a latch that samples the incoming NRZ data stream. The data rate can be twice the reference clock frequency. The circuit has a proportional nondead-zone sampling phase detector that also serves the role of charge pump. A self-correcting function reduces the problem of the finite phase capture range associated with conventional DLLs. The prototype circuit is fabricated in 2.5-V 0.25-μm CMOS and occupies an area of only 270 × 50 μm². It is demonstrated that at 900-Mb/s NRZ data, jitter is reduced from 118.2- to 31.3-ps rms jitter for a power consumption of only 3 mW     

The Effects of Polarization-Mode Dispersion on the Phase of the Recovered Clock

The impact of polarization-mode dispersion (PMD) on the phase of the recovered clock in the receiver is analyzed. The effects of first-order PMD on different clock-recovery configurations utilized for return-to-zero (RZ) and non-RZ (NRZ) formats are studied. Closed-form expressions relating the PMD-induced sampling time shift with the differential group delay and the power ratio between the principal states of polarization are obtained for each high-Q filter-based clock recovery. An experimental validation at 10 Gb/s is also shown for the case of NRZ data format     

A power and area efficient CMOS clock/data recovery circuit forhigh-speed serial interfaces

A power and area efficient CMOS clock/data recovery circuit designed for a wide range of applications in high-speed serial data communications is described. It uses an analog phase-locked loop (PLL) to generate the high-speed clocks with an absolute rms jitter of less than 60 ps and a digital PLL which is designed to minimize chip area and power consumption to recover the clock and data signals from the incoming data stream. Fabricated in a 0.8 μm single-polysilicon, double-metal CMOS process, the digital PLL only consumes 45 mW at 125 Mb/s from a single 5 V supply, while the analog PLL consumes 92 mW. The chip area is 1.7 mm² for the digital PLL and 0.44 mm² for the analog PLL. It can handle an input data rate up to 280 Mb/s     

Experimental sensitivity studies of diode-clamped FET-SEEDsmart-pixel optical receivers

Experimental studies of monolithically integrated double-clamped smart-pixel optical receivers are presented. Circuits are realized in FET-SEED (field-effect transistor self-electrooptic effect device) integration technology, which permits fabrication of GaAs-based FET's, together with normal-incidence multiple-quantum-well detector/modulator devices. Novel features of the circuit include the use of two input signal beams, and the ability to control the input voltage swing with clamping diodes. Two variations of our circuit are found to have input capacitances of 50 or 60 fF. Resultant input optical switching energies depend on the voltage swing, the FET performance, and the input data format, but operation at 200 Mb/s with 40 fJ is demonstrated under ideal conditions with nonreturn-to-zero (NRZ) data. Finally, operation of the receiver with pulses that are short compared to the bit period is found to be advantageous as compared to the case of pulses equal to the bit period in length (NRZ format). 650 Mb/s operation is demonstrated     

2.5-Gb/s low-jitter low-power monolithically integrated optical receiver

A high-scale integrated optical receiver including a preamplifier, a limiting amplifier, a clock and data recovery (CDR) block, and a 1:4 demultiplexer (DEMUX) has been realized in a 0.25???m CMOS technology. Using the loop parameter optimization method and the low-jitter circuit design technique, the rms and peak-to-peak jitter of the recovered 625-MHz clock are 9.4 and 46.3?ps, respectively, which meet the jitter specifications stipulated in ITU-T recommendation G.958. The recovered and frequency divided 625?MHz clock has a phase noise of ?83.8 dBc/Hz at 20?kHz offset in response to 2.5?Gb/s PRBS input data (2²³?C1), and the 2.5?Gb/s PRBS data has been demultiplexed into four 625?Mb/s data. The power dissipation is only 0.3?W under a single 3.3 V supply (excluding output buffers).     

A 700-Mb/s/pin CMOS signaling interface using current integratingreceivers

A high speed CMOS signaling interface for application in multiprocessor interconnection networks has been developed. The interface utilizes I-V push-pull drivers, a delay line phase-locked loop (PLL), and sampling of the data on both edges of the clock. In order to increase the noise immunity of the reception, a current-integrating input pin sampler is used to receive the incoming data. Chips fabricated in a 0.8 μm CMOS technology achieve transfer rates of 740 Mb/s/pin operating from a 3.3 V supply with a bit error rate of less than 10^-14     

A CMOS 400-Mb/s serial link for AS-memory systems using a PWMscheme

In this paper, a serial link for AS-memory systems fabricated in a 0.25-μm standard CMOS technology is presented. This serial link utilizes a pulsewidth modulation (PWM) technique. By transmitting the PWM-encoded signal with periodic rising edges, the clock can be implicitly embedded in the data stream and the associating overhead needed in clock/data recovery circuits can, be mitigated. The symbol rate is 200 Mb/s and the equivalent data rate is 400 Mb/s. The PWM transceiver dissipates 66.5 mW at a 2.5-V supply voltage. It is suitable for the AS-memory systems in which the pin count is limited and elaborate clock/data recovery circuits are not required     

A 10-Gb/s 16:1 multiplexer and 10-GHz clock synthesizer in0.25-μm SiGe BiCMOS

A 10-Gb/s 16:1 multiplexer, 10-GHz clock generator phase-locked loop (PLL), and 6 × 16 b input data buffer are integrated in a 0.25-μm SiGe BiCMOS technology. The chip multiplexes 16 parallel input data streams each at 622 Mb/s into a 9.953-Gb/s serial output stream. The device also produces a 9.953-GHz output clock from a 622- or 155-MHz reference frequency. The on-board 10-GHz voltage-controlled oscillator (VCO) has a 10% tuning range allowing the chip to accommodate both the SONET/SDH data rate of 9.953 Gb/s and a forward error correction coding rate of 10.664 Gb/s. The 6 × 16 b input data buffer accommodates ±2.4 ns of parallel input data phase drift at 622 Mb/s. A delay-locked loop (DLL) in the input data buffer allows the support of multiple input clocking modes. Using a clock generator PLL bandwidth of 6 MHz, the 9.953-GHz output clock exhibits a generated jitter of less than 0.05 UI_P-P over a 50-kHz to 80-MHz bandwidth and jitter peaking of less than 0.05 dB     

A PLL-based 2.5-Gb/s GaAs clock and data regenerator IC

A GaAs IC that performs clock recovery and data retiming functions in 2.5-Gb/s fiber-optic communication systems is presented. Rather than using surface acoustic wave (SAW) filter technology, the IC employs a frequency- and phase-lock loop (FPLL) to recover a stable clock from pseudo-random non-return-to-zero (NRZ) data. The IC is mounted on a 1-in×1-in ceramic substrate along with a companion Si bipolar chip that contains a loop filter and acquisition circuitry. At the synchronous optical network (SONET) OC-48 rate of 2.488 Gb/s, the circuit meets requirements for jitter tolerance, jitter transfer, and jitter generation. The data input ambiguity is 25 mV while the recovered clock has less than 2° rms edge jitter. The circuit functions up to 4 Gb/s with a 40-mV input ambiguity and 2° RMS clock jitter. Total current consumption from a single 5.2-V supply is 250 mA     

A 2.5-GHz Built-in Jitter Measurement System in a Serial-Link Transceiver

A 2.5-GHz built-in jitter measurement (BIJM) system is adopted to measure the clock jitter on a transmitter and receiver. The proposed Vernier caliper and autofocus approaches reduce the area cost of delay cells by 48.78% relative to pure Vernier delay line structure with a wide measurement range. The counter circuit occupies an area of 19 $mu$ m $times$ 61 $mu$ m in the traditional stepping scan approach. The proposed equivalent-signal sampling technique removes the input jitter transfer path from the sampling clock. The power supply rejection design is incorporated into the delay cell and the judge circuit. The layout implementation, calibration, and test time of the proposed BIJM system are all improved. The core circuit occupies an area of only 0.5 mm $times$ 0.15 mm with the 90-nm CMOS process. The Gaussian and uniform distributions jitter is verified at a 5-ps timing resolution and a 2.5-GHz input clock frequency .      

Multi-Rate SerDes Transceiver for IEEE 1394b Applications

This paper presents the implementation of a multi-rate SerDes transceiver for IEEE 1394b applications. Simple and effective pre-emphasis and equalizer circuits are used in the transmitter and receiver, respectively. A phase interpolator based clock and data recovery circuit with optimized linearity is also described. With an on-chip fully integrated phase locked loop, the transceiver works at data rates of 100 Mb/s, 400 Mb/s, and 800 Mb/s, supporting three different operating modes of S100b, S400b, and S800b for IEEE 1394b. The chip has been fabricated using 0.13 μm technology. The die area of transceiver is 2.9×1.6 mm2 including bonding pads and the total power dissipation is 284 mW with 1.2 V core supply and 3.3 V input/output supply voltages.     

Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection

A fully integrated clock and data recovery circuit (CDR) using a multiplying shifted-averaging delay locked loop and a rate-detection circuit is presented. It can achieve wide range and low jitter operation. A duty-cycle-insensitive phase detector is also proposed to mitigate the dependency on clock duty cycle variations. The experimental prototype has been fabricated in a 0.25-/spl mu/m 1P5M CMOS technology and occupies an active area of 2.89 mm/sup 2/. The measured CDR could operate from 125 Mb/s to 2.0 Gb/s with a bit error rate better than 10/sup -12/ from a 2.5-V supply. Over the entire operating frequency range, the maximum rms jitter of the recovered clock is less than 4 ps.     

A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL

Three circuit techniques for a 1.5 V, 512 Mb graphic DDR4 (GDDR4) SDRAM using a 90-nm DRAM process have been developed. First, a dual-clock system increases clocking accuracy and expands internal timing margins for harmonious core operation regardless of external clock frequency. Second, a four-phase data input strobe scheme helps to increase the input data valid window. Third, a fully analog delay-locked loop which provides a stable I/O clock and has 31.67 ps peak-to-peak jitter characteristics is designed. On the basis of these circuit techniques, the data rate is 3.2 Gbps/pin, which corresponds to 12.8 Gbps in times32 GDDR4-based I/O. Also, a multidivided architecture consisting of four independent 128 Mb core arrays is designed to reduce power line and output noise.     

一种适用于NRZ数据的时钟数据恢复电路

提出了一种基于传统电荷泵锁相环结构的时钟数据恢复电路.采用一种适用于NRZ数据的新型鉴频鉴相器电路,以克服传统鉴频鉴相器在恢复NRZ信号时出现错误脉冲的问题,从而准确地恢复出NRZ数据.同时,对其他电路也采用优化的结构,以提高时钟数据恢复电路的性能.设计的电路可在1.1 V超低电压下工作,适合RF ID等需要低电压、低功耗的系统使用.