一种考虑MOS效应及频变特性的类传输线型锥形TSV通孔电学模型

为准确描述锥形TSV通孔寄生电阻、电容、电感高频下MOS效应及其频变特性,本文首先推导出了锥形TSV通孔压控MOS电容的解析模型。其次基于修正后的双传输线寄生参数提取公式对锥形TSV通孔内寄生参数进行了提取。最终建立了一种考虑MOS效应及频变特性的类传输线型锥形TSV通孔电学模型。通过仿真工具验证模型精度,结果显示：在100GHz频带内模型与仿真结果吻合度较高,可以准确描述高频下锥形TSV通孔内寄生参数的半导体物理特性及频变特性,可用来预测锥形TSV通孔的电学特性,对优化三维集成电路电学性能有一定指导意义。     

一种0.18μm CMOS毫米波带通滤波器的设计

基于SMIC 0.18μm RF-CMOS工艺,设计了一种采用垂直地平面共面波导(VGPCPW)传输线的片上30 GHz带通滤波器。通过对传统CPW和VGP CPW两种不同结构传输线的理论研究,对比分析了两者的损耗、特征阻抗及隔离特性,建立了VGP CPW长度可扩展的传输线模型。使用特征阻抗为50Ω的低损耗VGP CPW传输线结构,结合VGP CPW长度可扩展模型与EM分析方法,设计了30 GHz带通滤波器。在片测试结果表明,该毫米波VGP CPW传输线滤波器模型仿真和电磁场仿真S参数曲线与测试结果比较吻合,可为毫米波集成电路滤波器设计提供借鉴。     

一种“L-2L”传输线去嵌入方法的优化分析

介绍了一种基于硅基微波共面波导传输线的"L-2L"去嵌入技术的改进方法。该方法可更加精确地剥离在片器件S参数中探针焊盘寄生效应的影响。利用ADS软件对无焊盘的理想传输线结构进行了电磁仿真,确立了去嵌入结果精确度的判定标准。使用GSG微波探针提取了测试样品的S参数,推导了π型寄生参量等效电路模型中并联导纳Y不同位置(m=0,0.5,1)下左、右探针焊盘的ABCD矩阵,得到了去嵌入后在片器件的本征传输特性S参数,并结合电磁仿真对比。结果表明:m=1时,其S参数曲线与仿真结果最为接近(平均偏差量ΔS_(11)=18.431,ΔS_(21)=4.405,ΔS=11.418)。对于不同在片测试器件需要着重考虑m的取值。     

Characterization and Modeling of Finite-Ground Coplanar Waveguides in 0.13μm CMOS

讨论了利用TSMC 0.13μm CMOS工艺实现的共面波导的特性及其建模.通过Momentum等电磁场仿真软件计算了传输线的基本参数,例如特征阻抗和衰减常数.并设计了特征阻抗分别为30,50,70和100Ω的共面波导传输线元件库.最后,在0.1～40GHz的范围内利用网络分析仪和SOLT(short-open-load-thru)测试技术测得特征阻抗和衰减常数,共面波导的分布参数则通过提取测试得到的S参数得到.     

0.13μm CMOS上接地板宽度有限共面波导的特性与建模

讨论了利用TSMC 0.13μm CMOS工艺实现的共面波导的特性及其建模.通过Momentum等电磁场仿真软件计算了传输线的基本参数,例如特征阻抗和衰减常数.并设计了特征阻抗分别为30,50,70和100Ω的共面波导传输线元件库.最后,在0.1～40GHz的范围内利用网络分析仪和SOLT(short-open-load-thru)测试技术测得特征阻抗和衰减常数,共面波导的分布参数则通过提取测试得到的S参数得到.     

一种基于传输线理论的pn结二极管小信号模型

为了精确表征毫米波频段pn结二极管的特性,提出了一种基于传输线理论的pn结二极管小信号模型。该模型包括表征pn结的本征部分和寄生部分。以量化的pn结耗尽区串联电阻作为中间项,通过非线性传输线理论近似方法,推导出全新的pn结二极管小信号模型的拓扑结构。通过导纳参数和阻抗参数的参数解析提取方法,提取等效电路中各元件参数值。使用某磷化铟(InP)工艺线加工所得2×3μm、8×8μm、4×16μm二极管的散射参数数据进行验证。结果表明,在1～110 GHz频率范围内,不同偏压的模型仿真结果与测试结果均吻合较好,同时也能表明模型在毫米波频段内有良好的适用性。     

空心硅通孔的设计及其传输性能

硅通孔(TSV)能够实现信号的垂直传输,是微系统三维集成中的关键技术,在微波毫米波领域,硅通孔的高频传输特性成为研究的重点。针对微系统三维集成中,无源集成的硅基转接板的空心TSV垂直传输结构低损耗的传输要求,进行硅通孔的互连设计和传输性能分析。采用传输线校准方式,首先在硅基转接板上设计TSV阵列接地的共面波导(CPW)传输线和带TSV过孔的传输结构,并分别进行仿真分析,计算得出带TSV过孔的传输结构的插入损耗;然后通过后道TSV工艺,在硅基转接板上制作传输线和带TSV过孔的传输结构,用矢量网络分析仪法测试传输线和带TSV过孔的传输结构的插入损耗;最后计算得到单个TSV过孔的插入损耗,结果显示在0.1～30 GHz频段内其插入损耗S21≤0.1 dB,实现了基于TSV的低损耗信号传输。     

3D封装玻璃通孔高频特性分析与优化

建立了3D封装玻璃通孔(TGV)电磁仿真分析模型,对TGV高频信号特性进行了分析,得到了回波损耗S11仿真结果,并研究了信号频率、通孔类型、通孔最大直径、通孔高度、通孔最小直径对S11的影响。选取TGV关键结构通孔最大直径、通孔高度、通孔最小直径尺寸为设计参数,以TGV在信号频率10 GHz下的S11作为目标值,采用响应曲面法,设计17组试验进行仿真,并拟合了TGV S11与其关键结构参数的关系模型。结合遗传算法对拟合模型进行优化,得到TGV S11最优的组合参数:通孔最大直径65 μm、通孔高度360 μm、通孔最小直径尺寸44 μm。对最优组合参数进行验证,发现最优参数组合仿真结果较基本模型S11减小了1.593 5 dB,实现了TGV的结构优化。     

新型的3D堆叠封装制备工艺及其实验测试

为了满足超大规模集成电路(VLSI)芯片高性能、多功能、小尺寸和低功耗的需求,采用了一种基于贯穿硅通孔(TSV)技术的3D堆叠式封装模型.先用深反应离子刻蚀法(DRIE)形成通孔,然后利用离子化金属电浆(IMP)溅镀法填充通孔,最后用Cu/Sn混合凸点互连芯片和基板,从而形成了3D堆叠式封装的制备工艺样本.对该样本的接触电阻进行了实验测试,结果表明,100 μm2Cu/Sn混合凸点接触电阻约为6.7 mΩ高90 μm的斜通孔电阻在20～30mΩ该模型在高达10 GHz的频率下具有良好的机械和电气性能.     

消除硅通孔侧壁刻蚀损伤的方法

硅通孔刻蚀是TSV技术的重要工序步骤,采用标准博世（Bosch）工艺刻蚀硅通孔（宽为150μm）,发现硅通孔侧壁出现多处刻蚀损伤。通过优化Bosch工艺参数增加沉积保护,消除了硅通孔侧壁刻蚀损伤问题,通孔开口差值,即通孔下开口宽度与通孔上开口宽度的差,从原来的22μm减小到13μm。利用优化后的工艺配方对硅通孔和硅腔(宽为1 500μm)同时进行刻蚀时,发现硅腔刻蚀后会产生硅针,不能应用到实际生产。经过多轮次Bosch工艺参数调整,把Bosch工艺沉积步骤的偏置功率设置为10 W,同时解决了硅通孔侧壁刻蚀损伤和硅腔刻蚀出现硅针问题,最终成功应用到MEMS环形器系列产品当中。     

双根锥形硅通孔结构的精确RLGC电路模型

A fast RLGC circuit model with analytical expression is proposed for the dual tapered through-silicon via （TSV） structure in three-dimensional integrated circuits under different slope angles at the wide frequency region. By describing the electrical characteristics of the dual tapered TSV structure, the RLGC parameters are extracted based on the numerical integration method. The RLGC model includes metal resistance, metal inductance, substrate resistance, outer inductance with skin effect and eddy effect taken into account. The proposed analytical model is verified to be nearly as accurate as the Q3D extractor but more efficient.     

Capacitance characterization of tapered through-silicon-via considering MOS effect

In this paper, closed-form expression for the parasitic capacitance of tapered TSV (T-TSV) considering metal–oxide–semiconductor (MOS) effect is proposed by solving two-dimensional (2D) Poisson's equation. ANSYS Q3D Extractor is employed to verify the proposed model for the slope wall angle of 75°, 80°, 85° and 90°. It is shown that error is less than ~5%. The capacitance characterization of copper T-TSV is studied in detail, by taking slope wall angle of 80° for instance. The results show that the capacitance of T-TSV acts as that of MOS device in changing the bias voltage; the increases of the bottom radius of T-TSV (from 1 to 5 μm), dielectric liner thickness (from 0.1 to 0.5 μm), liner dielectric constant (from 1 to 5), T-TSV height (from 10 to 50 μm) and acceptor concentration (from 1×10¹⁵ to 5×10¹⁵ cm⁻³) cause increase of T-TSV capacitance by about 25 fF, −12 fF, 12 fF, 210 fF and 12 fF, respectively. Finally, the condition for T-TSV simplified to cylindrical TSV is obtained.     

Air-gap-based RF coaxial TSV and its characteristic analysis

Many 3D IC applications such as MEMS and RF systems require Through-Silicon Via （TSV） with operations for high-speed vertical communication. In this paper, we introduce a novel air-gap coaxial TSV that is suiTab, for such RF applications. Firstly, the detailed fabrication process is described to explain how to acquire such a structure. Then, an Resistor Inductance Conductance Capacitance （RLGC） model is developed to profile the transverse electromagnetic field effect of the proposed air-gap TSV. The model is further verified by a 3D field solver program through the S-parameter comparison. With reference to the numerically simulated results, this analytical model delivers a maximum deviation of less than 6%0, on the conditions of varying diameters, outer to inner radius ratios, and SU-8 central angles, etc. Taking advantages of scalability of the model, a number of air-gap-based TSV designs are simulated, providing 1.6-4.0 times higher bandwidth than the con- ventional coaxial TSVs and leading to an efficient high frequency vertical RF interconnection solution for 3D ICs.     

A new low-parasitic polysilicon SCR ESD protection structure for RF ICs

Robust low-parasitic electrostatic discharge (ESD) protection is highly desirable for RF ICs. This letter reports design of a new low-parasitic polysilicon silicon controlled rectifier (SCR) ESD protection structure designed and implemented in a commercial 0.35-/spl mu/m SiGe BiCMOS technology. The concept was verified by simulation and experiment with the results showing that the new structure has much lower parasitic capacitance (C/sub ESD/) and higher F-factor than that of other ESD protection devices. A small polysilicon SCR structure of 750-/spl mu/m/sup 2/ all-inclusive provides a high human body model ESD protection of 3.2 kV while featuring a high F-factor of /spl sim/42 and a low C/sub ESD/ of /spl sim/92.3 fF. The new polysilicon SCR ESD protection structure seems to be an attractive solution to high-GHz RF ICs.     

湿法腐蚀和干法刻蚀工艺对850 nmVCSEL高速调制性能的影响

垂直腔面发射激光器(VCSEL)以其低功耗、低阈值电流、高调制速率和易制作二维阵列器件等特点,广泛应用于短距离光互连领域.湿法腐蚀和干法刻蚀作为高速VCSEL台面结构制备的两种工艺,影响VCSEL氧化层的大小.文章研究了氧化层面积对寄生电容的影响,并计算得到7 μm氧化孔径下采用干法刻蚀工艺的垂直腔面发射激光器,相比较湿法腐蚀工艺,氧化层电容由902.23 fF减小至581.32 fF,谐振腔电容由320.72 fF减小至206.65 fF.通过对采用湿法腐蚀和干法刻蚀工艺制备的GaAs量子阱结构高速VCSEL进行小信号调制响应测试,结果表明,7μm氧化孔径下干法刻蚀VCSEL小信号调制带宽提高至16.1 GHz.     

18V LDMOS器件ESD电流非均匀分布的模拟和测试分析

通过二维器件仿真,分析单指、多指18V nLDMOS器件在静电放电防护中电流分布的非均匀性问题。经仿真分析可知,寄生三极管的部分导通是单指器件电流分布不均匀的原因;器件的大面积特征、材料本身的不均匀性等因素导致叉指不同时触发,同时,由于nLDMOS各叉指基极被深N阱隔离,先被触发的叉指无法抬高未触发叉指的基极电位帮助其开启,是多指器件电流分布不均匀的原因。器件的TLP(Transmission line pulse)测试结果与仿真分析吻合,指长分别为50μm和90μm的单指器件ESD电流泄放能力分别为21mA/μm和15mA/μm;指长为50μm的单指、双指、四指和八指器件的ESD失效电流分别为1.037A、1.055A、1.937A和1.710A,不与指数成比例增大。     

Improved transmission line model for high-frequency modelling of through silicon vias

Accurate and reliable models can support Through Silicon Via (TSV) testing methods and improve the quality of 3D ICs. A model for expressing resistance and inductance of TSVs at frequencies up to 50 GHz is proposed. It is based on the two-parallel transmission cylindrical wires model, known also as the Transmission Line Model and improved through the fitting to ANSYS Q3D simulation results. The proximity effect between neighbouring TSVs that alters the paths through which current flows is empowered at high frequencies. The consideration of the dependence of the proximity effect on frequency for calculating TSV resistance and inductance is the main contribution of this work. Additionally, the modelling of resistance is extended to accurately correspond to a TSV in an array. The proposed models are in good agreement with the simulator results with an average error below 2% and 5.4% for the resistance and the inductance, respectively. The maximum error is 3% and 9.1%, respectively. In the case of the resistance of a TSV in an array, the maximum error is 4.7%. As long as the coefficients of the proposed equations have been extracted, the time for resistance and inductance calculation based on the presented models is negligible, compared to the time-consuming EM simulation.     

Evaluation of RF electrostatic discharge (ESD) protection in 0.18-μm CMOS technology

Electrostatic discharge (ESD) protection design is challenging for RF integrated circuits (ICs) because of the trade-off between the ESD robustness and parasitic capacitance. ESD protection devices are fabricated using the 0.18-μm RF CMOS process and their RF ESD characteristics are investigated by the transmission line pulsing (TLP) tester. The results suggest that the silicon controlled rectifier (SCR) is superior to the diode and NMOS from the perspective of ESD robustness and parasitic, but the SCR nevertheless possesses a longer turn-on time.     

Through-silicon-via insertion for performance optimization in three-dimensional integrated circuits

Through-silicon-via (TSV) interconnect is one of the main technologies for three-dimensional integrated circuits production (3-D ICs). Based on a parasitic parameters extraction model, first order expressions for the TSV resistances, inductances, and capacitance as functions of physical dimension and material characteristic are derived. Analyzing the impact of TSV size and placement on the interconnect timing performance and signal integrity, this paper presents an approach for TSV insertion in 3D ICs to minimize the propagation delay with consideration to signal reflection. Simulation results in multiple heterogeneous 3D architectures demonstrate that our approach in generally can result in a 49.96% improvement in average delay, a 62.28% decrease in the reflection coefficient, and the optimization for delay can be more effective for higher non-uniform inter-plane interconnects. The proposed approach can be integrated into the TSV-aware design and optimization tools for 3-D circuits to enhance system performance.     

基于SiGe BiCMOS工艺的25Gbit/s跨阻放大器设计

采用0.25 μm SiGe双极CMOS (BiCMOS)工艺设计并实现了一种传输速率为25 Gbit/s的高速跨阻前置放大器(TIA).在寄生电容为65fF的情况下,电路分为主放大器模块、两级差分模块和输出缓冲模块.相比传统的跨阻放大器,TIA采用Dummy形式实现了一种伪差分的输入,减小了共模噪声,提高了电路的稳定性;在差分级加入了电容简并技术,有效地提高了跨阻放大器的带宽;在各级之间引入了射极跟随器,减小了前后级之间的影响,改善了电路的频域特性.电路整体采用了差分结构,抑制了电源噪声和衬底噪声.仿真结果表明跨阻放大器的增益为63.6 dBQ,带宽可达20.4 GHz,灵敏度为-18.2 dBm,最大输出电压为260 mV,功耗为82 mW.