模塑阵列封装BGA的翘曲问题

全球BGA封装市场正在不断增大，然而，与QFP封装相比较，BGA封装也存在不足之处。模塑阵列封装BGA(MAP—BGA)的翘曲问题是其主要缺陷，为了减小翘曲，提高BGA封装的特性，应研究模塑料、粘片胶和基板材料，并使这些材料最佳化。     

对细间距球栅阵列封装（FPBGA）焊料裂纹抵抗力问题的探讨

全球BGA封装市场正在增大，这是由于其易于安装到PCB板上。然而，与QFP封装相比较，BGA封装具有一些缺点，如细间距BGA封装的抗焊料裂纹能力较低是其主要缺点。为提高BGA封装的可靠性，应研究各种模塑料、粘片胶和基板材科的最佳组合。     

避免发生芯片裂纹的倒装片BGA技术概述

介绍了把断裂力学法应用于倒装片BGA的设计方法。概述了一些关键的材料特性和封装尺寸对倒装片BGA芯片裂纹的影响作用，从而断定基板厚度和芯片厚度是倒装片BGA芯片发生裂纹的两个最重要的因素。     

BGA封装倒装焊点不同接触面跌落失效的研究

采用自由跌落的试验方法,研究了BGA(球栅阵列)封装自由跌落到不同材质基板后的可靠性,对比分析焊点裂纹产生、扩展直至断裂的机理。对失效封装芯片进行了染色处理,观察BGA封装中焊点的失效位置和焊点内部裂纹的形貌。结果表明,不同接触面上焊球裂纹都经历稳态-扩展-失效的过程,石质接触面上裂纹出现最早,裂纹扩展最快,失效最快,钢质接触面次之,最后是木质接触面。木质接触面的焊点失效模式主要是焊盘失效;钢质和石质接触面的焊点的失效模式以金属间化合物失效为主。比例风险模型(PHM)估计得到的寿命值与试验结果误差较小,能有效预测焊点自由跌落条件下的寿命。     

应用Dragon-i技术的Ultra BGA封装基板

初期的BGA封装主要以BT或高Tg的FR-4类的塑性材料为基板，称为PBGA(Plastic BGA)，而使用PBGA封装基板因其具有较大的热阻，因此应用到高速、高功率芯片的封装将会限制芯片性能的正常发挥。1994年Amkor公司为改善PBGA的热耗散特性，开发出Super BGA。Super BGA是第一个专     

焊球阵列转变与绝缘基板技术

在半导体整体的焊球阵列封装(BGA)领域,一份针对数个关键封装形式所进行的分析报告中,显示了造成不同焊球阵列封装形式成长或下跌的原因,并更清楚地点出了目前使用的数种基板技术的缺点。这篇分析报告列出了主要的焊球阵列封装的形式和基板发展潮流,还清楚地指出焊球阵列封装整体的发展延缓了硅芯片技术的演进,这在某些BGA领域中尤其明显,主要是因为缺乏先进的基板技术。因此文后得出结论,封装产业供货供应链基板市场中可能出现新的厂商,其也许来自主机板市场。     

基于内聚力模型脱粘仿真的内埋芯片PI分层研究

芯片埋入式封装技术的难点主要集中在封装制造过程对芯片造成的一系列不利影响,如裂纹、分层、翘曲、静电等.基板埋入芯片的特殊结构,大大增加了封装工艺难度.首先根据开发过程中出现的芯片聚酰亚胺分层现象建立简化模型,其次应用ANSYS工具中的内聚力单元对界面脱粘过程进行了模拟仿真,并分析了模型的等效应力值分布.结果 表明,实验...     

IC封装基板格局三足鼎立成本趋于下降

传统的IC封装是采用导线框架作为IC导通线路与支撑IC的载具,它连接引脚于导线框架的两旁或四周。随着IC封装技术的发展,引脚数量的增多(超过300以上个引脚)、布线密度的增大、基板层数的增多,使得传统的QFP等封装形式在其发展上有所限制。20世纪90年代中期一种以BGA、CSP为代表的新型IC封装形式问世,随之也产生了一种半导体芯片封装的必要新载体,这就是IC封装基板(IC Package Substrate,又称为IC封装载板)。近年来,BGA、CSP以及Flip Chip(FC)等形式的IC封装基板,在应用领域上得到迅速扩大,广为流行。世界从事封装制造业的主…     

BGA封装技术

本文简述了BGA封装产品的特点、结构以及一些BGA产品的封装工艺流程,对BGA封装中芯片和基板两种互连方法——引线键合/倒装焊键合进行了比较以及对几种常规BGA封装的成本/性能的比较,并介绍了BGA产品的可靠性。另外,还对开发我国BGA封装技术提出了建议。     

BGA植球工艺技术

BGA(ball grid array)球栅阵列封装技术是20世纪90年代以后发展起来的一种先进的高性能封装技术,是一种用于多引脚器件与电路的封装技术。BGA最大的特点就是采用焊球作为引脚,这不仅提高了封装密度,也提高了封装性能。而植球工艺作为BGA封装中的关键工艺将会直接影响器件与电路的性能及可靠性。影响BGA植球工艺的主要因素有:植球材料、植球工艺及回流焊工艺。文章通过对BGA植球的基板、焊膏/助焊剂、焊球等材料的详细介绍,详实阐述了植球工艺过程,并对BGA后处理的回流焊工艺进行了详细描述,提供了BGA植球工艺的检测方法,对植球工艺的可靠性进行了探讨。     

Measurement of water absorption in ball grid array package

The plastic ball grid array (BGA) package has poor resistance to popcorn cracking, which occurs when high temperatures involved in soldering cause water vapor to expand rapidly. Popcorn cracking occurs at die attach paste, and therefore water absorption and desorption occurring in the vicinity of die attach paste must be studied. We examine the mechanism of popcorn cracking in a BGA, particularly from the aspect of water absorption distribution. Water absorption was simulated by use of deuterium oxide, because the absorption performance of deuterium oxide approximates that of water. Deuterium oxide absorption distribution was measured by time of flight secondary ion mass spectroscopy (ToF-SIMS). We found that the water is absorbed mainly through the upper side of molded portion of the BGA package, and that absorption through the substrate is small. A BGA substrate has a laminated structure, and therefore water cannot penetrate the substrate first. On the basis of the results obtained in our study, we designed a BGA package system that is not prone to popcorn cracking     

Use of C-SAM acoustical microscopy in package evaluations and failure analysis

Acoustical microscopy is gaining wide acceptance in the microelectronic packaging community. C-mode scanning acoustical microscopy, C-SAM, is widely used in package evaluations and for failure analysis. This paper discusses several specific topics. These include: (1) popcorn cracking in SMDs; (2) an evaluation of solder die attach in power packages; (3) an instance of top of die delamination which resulted in electrical failures; and (4) moisture sensitivity of other surface mount power packages and how it resulted in ball bond degradation during a new product qualification.     

Characterization of chip scale packaging materials

The mechanical stability of Chip Scale Packages (CSP) used in surface mount technology is of primary concern. The dominant issues are package warpage and solder fatigue in solder joints under cyclic loads. To address these issues, molding compound and die attach film were characterized with finite element method which employed a viscoelastic and viscoplastic constitutive model. The model was verified with experiments on package warpage, PCB warpage and solder joint reliability. After the correlation was observed, the effect of molding compound and die attach film on package warpage and solder joint reliability was investigated. It was found that package warpage tremendously affected solder joint reliability. Furthermore, a die attach film was developed based on results of the modeling. CSP with the developed die attach film are robust and capable of withstanding the thermal stresses, humidity and high temperatures encountered in typical package assembly and die attach processes. Also, a lead free solder is discussed based on the results of creep testing. This paper presents the viscoelastic and viscoplastic constitutive model and its verification, the optimum material properties, the experimental and simulated reliability and performance results of the u*BGA packages, and the lead free solder creep.     

Study of self-alignment of /spl mu/BGA packages

In this paper, a detailed study of the self-alignment of /spl mu/BGA packages is presented. Complete self-alignment can be achieved even for a misalignment of the package of larger than 50% off the test board pad centres. A small residual displacement of the package from perfect alignment after reflow is observed. The reason for this displacement is the action of gas flow viscous drag on the package during reflow. The use of eutectic SnPb solder paste slightly reduces self-aligning ability, due to the increase in the solder volume, which reduces the restoring force. Exposure of the solder paste to a 25/spl deg/C and 85% RH humidity environment also has a detrimental effect on the self-alignment of the /spl mu/BGA package, due to solvent evaporation and moisture absorption in the paste causing solderability degradation. The self-alignment of the package is also affected when there is slow spreading of molten solder on the pad surface. This is attributed to the reduction of restoring force due to the decrease in effective wetting surface area of the board pad.     

High-lead flip chip bump cracking on the thin organic substrate in a module package

Flip chip bump cracking was observed after Si die attach reflow on the organic substrate of a module package. High-lead bump and eutectic SnPb cladding were used on Si die and the substrate sides, respectively. The reflow peak temperature was 260 °C for compatibility with passive components attach using lead-free solder. Flip chip bump cracking occurred at high-lead solder close to the die side. The cracking was eliminated by lowering the reflow peak temperature down to 225 °C. Main cause of the cracking at 260 °C reflow was attributed to the extensive Sn diffusion into high lead bump. This decreased the melting point of the high-lead solder around the die side, which in turn worsened the adhesion between solder and die due to the coexistence of solid and liquid. Diffusion length estimation showed both of the liquid- and solid-state diffusions of Sn. Crack gap in the solder bump was consistent with thermal expansion mismatch between Si die and organic substrate. The bump cracking was mitigated by use of 225 °C reflow, limiting Sn diffusion and providing a good integrity of high lead bumps on die side.     

传统PQFP与BGA封装技术的比较及其发展趋势

本文简要论述了传统 PQFP 封装技术,并根据 I/O 数、密度(面积)、电性能、生产量及“爆玉米花”效应,对它们进行了比较,最后简述了这两种封装技术的发展趋势。     

High density packaging technology ultra thin package & new tab package

As electronic devices become more highly integrated, the demand for small, high pin count packages has been increasing. We have developed two new types of IC packages in response to this demand. One is an ultra thin small outline package (TSOP) which has been reduced in size from the standard SOP and the other, which uses Tape Automated Bonding (TAB) technology, is a super thin, high pin count TAB in cap (T.I.C.) package. In this paper, we present these packages and their features along with the technologies used to improve package reliability and TAB. Thin packages are vulnerable to high humidity exposure, especially after heat shock.1 The following items were therefore investigated in order to improve humidity resistance: (1) The molding compound thermal stress, (2) Water absorption into the molding compound and its effect on package cracking during solder dipping, (3) Chip attach pad area and its affect on package cracking, (4) Adhesion between molding resin and chip attach pad and its affect on humidity resistance. With the improvements made as a result of these investigations, the reliability of the new thin packages is similar to that of the standard thicker plastic packages.     

Exposed Die-Top Encapsulation Molding for an Improved High- Performance Flip Chip BGA Package

The recent advancement in high- performance semiconductor packages has been driven by the need for higher pin count and superior heat dissipation. A one-piece cavity lid flip chip ball grid array (BGA) package with high pin count and targeted reliability has emerged as a popular choice. The flip chip technology can accommodate an I/O count of more than five hundreds500, and the die junction temperature can be reduced to a minimum level by a metal heat spreader attachment. None the less, greater expectations on these high-performance packages arose such as better substrate real estate utilization for multiple chips, ease in handling for thinner core substrates, and improved board- level solder joint reliability. A new design of the flip chip BGA package has been looked into for meeting such requirements. By encapsulating the flip chip with molding compound leaving the die top exposed, a planar top surface can be formed. A, and a flat lid can then be mounted on the planar mold/die top surface. In this manner the direct interaction of the metal lid with the substrate can be removed. The new package is thus less rigid under thermal loading and solder joint reliability enhancement is expected. This paper discusses the process development of the new package and its advantages for improved solder joint fatigue life, and being a multichip package and thin core substrate options. Finite-element simulations have been employed for the study of its structural integrity, thermal, and electrical performances. Detailed package and board-level reliability test results will also be reported