Low-Temperature Materials and Thin Film Transistors for Flexible Electronics

This paper addresses the low-temperature deposition processes and electronic properties of silicon based thin film semiconductors and dielectrics to enable the fabrication of mechanically flexible electronic devices on plastic substrates. Device quality amorphous hydrogenated silicon (a-Si:H), nanocrystalline silicon (nc-Si), and amorphous silicon nitride (a-SiN/sub x/) films and thin film transistors (TFTs) were made using existing industrial plasma deposition equipment at the process temperatures as low as 75/spl deg/C and 120/spl deg/C. The a-Si:H TFTs fabricated at 120/spl deg/C demonstrate performance similar to their high-temperature counterparts, including the field effect mobility (/spl mu//sub FE/) of 0.8 cm/sup 2/V/sup -1/s/sup -1/, the threshold voltage (V/sub T/) of 4.5 V, and the subthreshold slope of 0.5 V/dec, and can be used in active matrix (AM) displays including organic light emitting diode (OLED) displays. The a-Si:H TFTs fabricated at 75/spl deg/C exhibit /spl mu//sub FE/ of 0.6 cm/sup 2/V/sup -1/s/sup -1/, and V/sub T/ of 4 V. It is shown that further improvement in TFT performance can be achieved by using n/sup +/ nc-Si contact layers and plasma treatments of the interface between the gate dielectric and the channel layer. The results demonstrate that with appropriate process optimization, the large area thin film Si technology suits well the fabrication of electronic devices on low-cost plastic substrates.     

Nonalloyed ohmic contacts in AlGaN/GaN HEMTs by ion implantation with reduced activation annealing temperature

This letter reports AlGaN/GaN high-electron mobility transistors with capless activation annealing of implanted Si for nonalloyed ohmic contacts. Source and drain areas were implanted with an Si dose of 1/spl times/10/sup 16/ cm/sup -2/ and were activated at /spl sim/1260/spl deg/C in a metal-organic chemical vapor deposition system in ammonia and nitrogen at atmospheric pressure. Nonalloyed ohmic contacts to ion-implanted devices showed a contact resistance of 0.96 /spl Omega//spl middot/mm to the channel. An output power density of 5 W/mm was measured at 4 GHz, with 58% power-added efficiency and a gain of 11.7 dB at a drain bias of 30 V.     

Thermally stable Ge/Ag/Ni Ohmic contact for InAlAs/InGaAs/InP HEMTs

Excellent annealed ohmic contacts based on Ge/Ag/Ni metallization have been realized in a temperature range between 385 and 500/spl deg/C, with a minimum contact resistance of 0.06 /spl Omega//spl middot/mm and a specific contact resistivity of 2.62 /spl times/10/sup -7/ /spl Omega//spl middot/cm/sup 2/ obtained at an annealing temperature of 425/spl deg/C for 60 s in a rapid thermal annealing (RTA) system. Thermal storage tests at temperatures of 215 and 250/spl deg/C in a nitrogen ambient showed that the Ge/Ag/Ni based ohmic contacts with an overlay of Ti/Pt/Au had far superior thermal stabilities than the conventional annealed AuGe/Ni ohmic contacts for InAlAs/InGaAs high electron mobility transistors (HEMTs). During the storage test at 215/spl deg/C, the ohmic contacts showed no degradation after 200 h. At 250/spl deg/C, the contact resistance value of the Ge/Ag/Ni ohmic contact increased only to a value of 0.1 /spl Omega//spl middot/mm over a 250-h period. Depletion-mode HEMTs (D-HEMTs) with a gate length of 0.2 /spl mu/m fabricated using Ge/Ag/Ni ohmic contacts with an overlay of Ti/Pt/Au demonstrated excellent dc and RF characteristics.     

Si interlayer passivation on germanium MOS capacitors with high-/spl kappa/ dielectric and metal gate

We have demonstrated the advantages of silicon interlayer passivation on germanium MOS devices, with CVD HfO/sub 2/ as the high-/spl kappa/ dielectric and PVD TaN as the gate electrode. A silicon interlayer between a germanium substrate and a high-/spl kappa/ dielectric, deposited using SiH/sub 4/ gas at 580/spl deg/C, significantly improved the electrical characteristics of germanium devices in terms of low D/sub it/ (7/spl times/10/sup 10//cm/sup 2/-eV), less C- V hysteresis and frequency dispersion. Low leakage current density of 5/spl times/10/sup -7/ A/cm/sup 2/ at 1 V bias with EOT of 12.4 /spl Aring/ was achieved. Post-metallization annealing caused continuing V/sub fb/ positive shift and J/sub g/ increase with increased annealing temperature, which was possibly attributed to Ge diffusion into the dielectric during annealing.     

Low resistance and reflective Mg-doped indium oxide-Ag ohmic contacts for flip-chip light-emitting diodes

We have investigated an Mg-doped In/sub x/O/sub y/(MIO)-Ag scheme for the formation of high-quality ohmic contacts to p-type GaN for flip-chip light-emitting diodes (LEDs). The as-deposited sample shows nonlinear current-voltage (I--V) characteristics. However, annealing the contacts at temperatures of 330/spl deg/C-530/spl deg/C for 1 min in air ambient results in linear I--V behaviors, producing specific contact resistances of 10/sup -4/--10/sup -5/ /spl Omega//spl middot/cm/sup 2/. In addition, blue LEDs fabricated with the MIO-Ag contact layers give forward-bias voltages of 3.13-3.15 V at an injection current of 20 mA. It is further shown that LEDs made with the MIO-Ag contact layers give higher output power compared with that with the Ag contact layer. This result strongly indicates that the MIO-Ag can be a promising scheme for the realization of high brightness LEDs for solid-state lighting application.     

Si/SiGe resonant interband tunnel diode with f/sub r0/ 20.2 GHz and peak current density 218 kA/cm/sup 2/ for K-band mixed-signal applications

This letter presents the room-temperature high-frequency operation of Si/SiGe-based resonant interband tunnel diodes that were fabricated by low-temperature molecular beam epitaxy. The resulting devices show a resistive cutoff frequency f/sub r0/ of 20.2 GHz with a peak current density of 218 kA/cm/sup 2/, a speed index of 35.9 mV/ps, and a peak-to-valley current ratio of 1.47. A specific contact resistivity of 5.3/spl times/10/sup -7/ /spl Omega//spl middot/cm/sup 2/ extracted from RF measurements was achieved by Ni silicidation through a P /spl delta/-doped quantum well by rapid thermal sintering at 430/spl deg/C for 30 s. The resulting devices are very good candidates for RF high-power mixed-signal applications. The device structures presented here are compatible with a standard complementary metal-oxide-semiconductor or heterojunction bipolar transistor process.     

Collector-pedestal InGaAs/InP DHBTs fabricated in a single-growth, triple-implant process

This letter reports InP/In/sub 0.53/Ga/sub 0.47/As/InP double heterojunction bipolar transistors (DHBTs) employing an N/sup +/ subcollector and N/sup +/ collector pedestal-formed by blanket Fe and patterned Si ion implants, intended to reduce the extrinsic collector-base capacitance C/sub cb/ associated with the device footprint. The Fe implant is used to compensate Si within the upper 130 nm of the N/sup +/ subcollector that lies underneath the base ohmic contact, as well as compensate the /spl sim/1-7/spl times/10/sup -7/ C/cm/sup 2/ surface charge at the interface between the indium phosphide (InP) substrate and the N/sup $/collector drift layer. By implanting the subcollector, C/sub cb/ associated with the base interconnect pad is eliminated, and when combined with the Fe implant and selective Si pedestal implant, further reduces C/sub cb/ by creating a thick extrinsic collector region underneath the base contact. Unlike previous InP heterojunction bipolar transistor collector pedestal processes, multiple epitaxial growths are not required. The InP DHBTs here have simultaneous 352-GHz f/sub /spl tau// and 403-GHz f/sub max/. The dc current gain /spl beta//spl ap/38, BV/sub ceo/=6.0 V, BV/sub cbo/=5.4 V, and I/sub cbo/<50 pA at V/sub cb/=0.3 V.     

A dependency of quantum efficiency of silicon CMOS n/sup +/pp/sup +/ LEDs on current density

A dependency of quantum efficiency of nn/sup +/pp/sup +/ silicon complementary metal-oxide-semiconductor integrated light-emitting devices on the current density through the active device areas is demonstrated. It was observed that an increase in current density from 1.6/spl times/10/sup +2/ to 2.2/spl times/10/sup +4/ A/spl middot/cm/sup -2/ through the active regions of silicon n/sup +/pp/sup +/ light-emitting diodes results in an increase in the external quantum efficiency from 1.6/spl times/10/sup -7/ to 5.8/spl times/10/sup -6/ (approximately two orders of magnitude). The light intensity correspondingly increase from 10/sup -6/ to 10/sup -1/ W/spl middot/cm/sup -2//spl middot/mA (approximately five orders of magnitude). In our study, the highest efficiency device operate in the p-n junction reverse bias avalanche mode and utilize current density increase by means of vertical and lateral electrical field confinement at a wedge-shaped n/sup +/ tip placed in a region of lower doping density and opposite highly conductive p/sup +/ regions.     

High-power P-i-N diode with local lifetime control using palladium diffusion controlled by radiation defects

We demonstrate for the first time a high-power P-i-N diode with local lifetime control using palladium (Pd) diffusion. Low-temperature (600/spl deg/C-700/spl deg/C) diffusion of Pd is stimulated by radiation defects resulting from alpha-particle irradiation (/sup 4/He/sup 2+/: 10 MeV, 10/sup 12/ cm/sup -2/). The region of maximal radiation damage of Gaussian shape is decorated by substitutional Pd after diffusion from a palladium silicide surface layer through the P/sup +/--P region into the N-base close to the anode junction. Significantly lower leakage current compared to that of standard /sup 4/He/sup 2+/ irradiation and very good ruggedness under fast recovery (di/dt/spl ap/500 A//spl mu/s, V/sub R//spl ap/2 kV) is demonstrated for Pd diffusion at 600/spl deg/C.     

Improvement of the luminous intensity of light-emitting diodes by using highly transparent Ag-indium tin oxide p-type ohmic contacts

We have investigated Ag-indium tin oxide (ITO) scheme for obtaining high-quality p-type ohmic contacts for GaN-based light-emitting diodes (LEDs). The Ag(1 nm)-ITO(200 nm) contacts exhibit greatly improved electrical characteristics when annealed at temperatures in the range 400/spl deg/C-600/spl deg/C for 1 min in air, yielding specific contact resistances of /spl sim/10/sup -4/ /spl Omega//spl middot/cm/sup 2/. In addition, the contacts give transmittance of about 96% at 460 nm, which is far better than that of the conventionally used oxidized Ni-Au contacts. It is shown that the luminous intensity of blue LEDs fabricated with the Ag-ITO contacts is about three times higher than that of LEDs with oxidized Ni-Au contacts. This result strongly indicates that the Ag-ITO scheme can serve as a highly promising p-type ohmic contact for the realization of high brightness near ultraviolet LEDs.     

Reduction of boron diffusion in silicon-germanium by fluorine implantation

This letter investigates the effect of a 185 keV, 2.3 /spl times/ 10/sup 15/ cm/sup -2/ F/sup +/ implant on boron transient enhanced diffusion (TED) and boron thermal diffusion in SiGe by characterizing the diffusion of a boron marker layer in samples with and without a 288 keV, 6 /spl times/ 10/sup 13/ cm/sup -2/ P/sup +/ implant. In samples implanted with F/sup +/ only, the fluorine suppresses boron thermal diffusion by 58%. In samples given both P/sup +/ and F/sup +/ implants, the fluorine completely eliminates boron transient enhanced diffusion caused by the P/sup +/ implant and also significantly reduces boron thermal diffusion. SIMS profiles after anneal show a fluorine concentration in the SiGe layer that is approximately 8 /spl times/ higher than after implant, indicating that fluorine accumulates in the SiGe layer during anneal. A comparison with fluorine profiles in comparable silicon samples also shows that the fluorine concentration after anneal is dramatically higher in SiGe samples than in Si samples. This accumulation of fluorine in the SiGe layer during anneal will have major benefits for boron diffusion suppression in devices like SiGe HBTs, where boron must be kept within the SiGe layer.     

Formation of Ni germano-silicide on single crystalline Si/sub 0.3/Ge/sub 0.7//Si

We have studied the Ni and Co germano-silicide on Si/sub 0.3/Ge/sub 0.7//Si. The Ni germano-silicide shows a low sheet resistance of 4-6 /spl Omega///spl square/on both P/sup +/N and N/sup +/P junctions, which is much smaller than Co germano-silicide. In addition, small junction leakage currents of 3/spl times/10/sup -8/ A/cm/sup 2/ and 2/spl times/10/sup -7/ A/cm/sup 2/ are obtained for Ni germano-silicide on P/sup +/N and N/sup +/P junctions, respectively. The good germano-silicide integrity is due to the relatively uniform thickness as observed by cross-sectional TEM.     

Rapid thermal annealed InGaN/GaN flip-chip LEDs

Nitride-based flip-chip (FC) light-emitting diodes (LEDs) emitting at 465 nm with Ni transparent ohmic contact layers and Ag reflective mirrors were fabricated. With an incident light wavelength of 465 nm, it was found that transmittance of normalized 300/spl deg/C rapid thermal annealed (RTA) Ni(2.5 nm) was 93% while normalized reflectance of 300/spl deg/C RTA Ni(2.5 nm)/Ag(200 nm) was 92%. It was also found that 300/spl deg/C RTA Ni(2.5 nm) formed good ohmic contact on n/sup +/ short-period-superlattice structure with specific contact resistance of 7.8/spl times/10/sup -4/ /spl Omega//spl middot/cm/sup 2/. With 20-mA current injection, it was found that forward voltage and output power were 3.15 V and 16.2 mW for FC LED with 300/spl deg/C RTA Ni(2.5 nm)/Ag(200 nm). Furthermore, it was found that reliabilities of FC LEDs were good.     

Study of nickel silicide contact on Si/Si/sub 1-x/Ge/sub x/

The properties of nickel silicide formed by depositing nickel on Si/p/sup +/-Si/sub 1-x/Ge/sub x/ layer are compared with that of nickel germanosilicide on p/sup +/-Si/sub 1-x/Ge/sub x/ layer formed by depositing Ni directly on p/sup +/-Si/sub 1-x/Ge/sub x/ layer without silicon consuming layer. After thermal annealing, nickel silicide on Si/p/sup +/-Si/sub 1-x/Ge/sub x/ layer shows lower sheet resistance and specific contact resistivity than that of nickel germanosilicide on p/sup +/-Si/sub 1-x/Ge/sub x/ layer. In addition, small junction leakage current is also observed for nickel silicide on a Si/p/sup +/-Si/sub 1-x/Ge/sub x//n-Si diode. In summary, with a Si consuming layer on top of the Si/sub 1-x/Ge/sub x/, the nickel silicide contact formed demonstrated improved electrical and materials characteristics as compared with the nickel germanosilicide contact which was formed directly on the Si/sub 1-x/Ge/sub x/ layer.     

Optimization of AuGe-Ni-Au ohmic contacts for GaAs MOSFETs

GaAs-based metal-oxide-semiconductor field-effect transistors (MOSFETs) are promising devices for high-speed and high-power applications. One important factor influencing the performance of a GaAs MOSFET is the characteristics of ohmic contacts at the drain and source terminals. In this paper, AuGe-Ni-Au metal contacts fabricated on a thin (930 /spl Aring/) and lightly doped (4/spl times/10/sup 17/ cm/sup -3/) n-type GaAs MOSFET channel layer were studied. The effects of controllable processing factors such as the AuGe thickness, the Ni/AuGe thickness ratio, alloy temperature, and alloy time to the characteristics of the ohmic contacts were analyzed. Contact qualities including specific contact resistance, contact uniformity, and surface morphology were optimized by controlling these processing factors. Using the optimized process conditions, a specific contact resistance of 5.6/spl times/10/sup -6/ /spl Omega//spl middot/cm/sup 2/ was achieved. The deviation of contact resistance and surface roughness were improved to 1.5% and 84 /spl Aring/, respectively. Using the improved ohmic contacts, high-performance GaAs MOSFETs (2 /spl mu/m/spl times/100 /spl mu/m) with a large drain current density (350 mA/mm) and a high transconductance (90 mS/mm) were fabricated.     

Thin-film transistors on plastic and glass substrates using silicon deposited by microwave plasma ECR-CVD

Thin-film transistors (TFTs) were fabricated on polyimide and glass substrates at low temperatures using microwave ECR-CVD deposited amorphous and nanocrystalline silicon as active layers. The amorphous Si TFT fabricated at 200 /spl deg/C on the polyimide foil had a saturation region field effect mobility of 4.5 cm/sup 2//V-s, a linear region mobility of 5.1 cm/sup 2//V-s, a threshold voltage of 3.7 V, a subthreshold swing of 0.69 V/decade, and an ON/OFF current ratio of 7.9 /spl times/ 10/sup 6/. This large mobility and high ON/OFF current ratio were attributed to the high-quality channel materials with less dangling bond defect states. Nanocrystalline Si TFTs fabricated on glass substrates at 400 /spl deg/C showed a saturation region mobility of 14.1 cm/sup 2//V-s, a linear region mobility of 15.3 cm/sup 2//V-s, a threshold voltage of 3.6 V, and an ON/OFF current ratio of 6.7 /spl times/ 10/sup 6/. TFT performance was mostly independent of substrate type when fabrication conditions were the same.     

Anodic Oxidation of Si in Oxygen/Chlorine Plasma

By adding a few percent of chlorine to oxygen plasma, the anodization rate of Si was enhanced; for example, the rate was doubled for oxygen containing 3-percent chlorine. With a chlorine concentration of 1.5 percent, the density of trap states at the Si-SiO/sub 2/ interface was reduced from 7 X 10/sup 11//cm/sup 2//spl dot/eV to 5 X 10/sup 11//cm/sup 2/ /spl dot/eV at the midgap of Si; after annealing at 800/spl deg/C in argon for 60 min, it was reduced to 8 X 10/sup 10//cm/sup 2//spl dot/eV, and did not return to the original value after heating the specimen to 800/spl deg/C. The density and capture cross section of traps in plasma-anodic oxide were also measured using the constant-current avalanche-injection method. The number of electron traps with small cross sections in plasma-anodic SiO/sub 2/ films was reduced by annealing them at 800/spl deg/C in argon, but SiO/sub 2/ films which were anodized in oxygen/chlorine plasma showed an increase of trap density under the same annealing condition.     

Leakage suppression of gated diodes fabricated under low-temperature annealing with substitutional carbon Si/sub 1-y/C/sub y/ incorporation

We have demonstrated the fabrication of n/sup +/-p gated diodes using low-temperature annealing of 700/spl deg/C for 30 s with a significantly reduced junction leakage current. This is achieved with the incorporation of an epitaxially grown Si/sub 1-y/C/sub y/(y=0.0007) layer in the substrate located at the end-of-range (EOR) of arsenic implantations. The carbon devices show effectively suppressed EOR defects in the cross-sectional transmission electron microscopy images and leakage characteristics similar to the controlled silicon device fabricated under high-temperature annealing of 950/spl deg/C for 30 s. Arrhenius measurement of the leakage profiles has indicated identical leakage mechanism for both the pure silicon and carbon devices, thus signifying the substantial elimination of the secondary EOR defects resulted from the implantations despite the low-temperature annealing of the latter.     

Top-gate TFTs using 13.56 MHz PECVD microcrystalline silicon

Top-gate thin-film transistors (TFTs) with microcrystalline silicon (/spl mu/c-Si) channel layers deposited using standard 13.56 MHz plasma-enhanced chemical vapor deposition were fabricated at a maximum processing temperature of 250/spl deg/C. The TFTs employ amorphous silicon nitride (a-SiN) as the gate dielectric layer. The 80-nm-thick /spl mu/c-Si channel layer showed a dark conductivity of the order of 10/sup -7/ S/cm and a crystalline volume fraction of over 80%. The /spl mu/c-Si TFTs showed a field effect mobility of 0.85 cm/sup 2//V/spl middot/s, a threshold voltage of 4.8 V, a subthreshold slope of 1 V/dec, and an ON/OFF current ratio of /spl sim/10/sup 7/. More importantly, the TFTs were very stable under gate bias stress, offering promise for organic light-emitting display (OLED) applications.     

A high current gain 4H-SiC NPN power bipolar junction transistor

This work reports the development of high power 4H-SiC bipolar junction transistors (BJTs) by using reduced implantation dose for p+ base contact region and annealing in nitric oxide of base-to-emitter junction passivation oxide for 2 hours at 1150/spl deg/C. The transistor blocks larger than 480 V and conducts 2.1 A (J/sub c/=239 A/cm/sup 2/) at V/sub ce/=3.4 V, corresponding to a specific on-resistance (R/sub sp on/) of 14 m/spl Omega/cm/sup 2/, based on a drift layer design of 12 /spl mu/m doped to 6/spl times/10/sup 15/cm/sup -3/. Current gain /spl beta//spl ges/35 has been achieved for collector current densities ranging from J/sub c/=40 A/cm/sup 2/ to 239 A/cm/sup 2/ (I/sub c/=2.1 A) with a peak current gain of 38 at J/sub c/=114 A/cm/sup 2/.