RF CMOS transceivers for cellular telephony

This article describes system and circuit issues related to cellular transceivers, presenting design techniques that have provided high performance in CMOS technology. Following an overview of relevant GSM and WCDMA specifications, the article identifies four trends in RF design that have continued to improve the performance. Examples of CMOS transceivers, and circuit and device concepts are then described that meet the stringent requirements of cellular telephony.     

Low-power/low-voltage RF microsystems for wireless sensors networks

This paper presents radio-frequency (RF) microsystems (MSTs) composed by low-power devices for use in wireless sensors networks (WSNs). The RF CMOS transceiver is the main electronic system and its power consumption is a critical issue. Two RF CMOS transceivers with low-power and low-voltage supply were fabricated to operate in the 2.4 and 5.7 GHz ISM bands. The measurements made in the RF CMOS transceiver at 2.4 GHz, which showed a sensitivity of −60 dBm with a power consumption of 6.3 mW from 1.8 V supply. The measurements also showed that the transmitter delivers an output power of 0 dBm with a power consumption of 11.2 mW. The RF CMOS transceiver at 5.7 GHz has a total power consumption of 23 mW. The target application of these RF CMOS transceivers is for MSTs integration and for use as low-power nodes in WSNs to work during large periods of time without human operation, management and maintenance. These RF CMOS transceivers are also suitable for integration in thermoelectric energy scavenging MSTs.     

Design of Millimeter-Wave CMOS Radios: A Tutorial

This paper deals with the challenges in the design of millimeter-wave CMOS radios and describes circuit and architecture techniques that lead to compact, low-power transceivers. Candidate topologies for building blocks such as low-noise amplifiers, mixers, oscillators, and frequency dividers are presented. Also, a number of radio architectures that relax the generation, division, and distribution of the local oscillator signal are reviewed. Last, integration issues for transmit and receive paths and for multiple beamforming transceivers are addressed.      

Impact of intrinsic channel resistance on noise performance of CMOSLNA

Channel resistance cannot be neglected for CMOS circuits that operate at radio frequency (RF), especially for a low noise amplifier (LNA), which is a very important block in CMOS RF transceivers. The impact of channel resistance on the noise performance of an LNA is thoroughly studied and analyzed and new formulas are proposed systematically in this work. Furthermore, a revised noise figure optimization technique is discussed. Simulation results are also proposed. All of this work will be very instructive for the design of high-performance LNA     

CMOS mm-wave transceivers for Gbps wireless communication

The challenges in the design of CMOS millimeter-wave (mm-wave) transceiver for Gbps wireless communication are discussed. To support the Gbps data rate, the link bandwidth of the receiver/transmitter must be wide enough, which puts a lot of pressure on the mm-wave front-end as well as on the baseband circuit. This paper discusses the effects of the limited link bandwidth on the transceiver system performance and overviews the bandwidth expansion techniques for mm-wave amplifiers and IF programmable gain amplifier. Furthermore, dual-mode power amplifier (PA) and self-healing technique are introduced to improve the PA''s average efficiency and to deal with the process, voltage, and temperature variation issue, respectively. Several fully-integrated CMOS mm-wave transceivers are also presented to give a short overview on the state-of-the-art mm-wave transceivers.     

CMOS wireless transceivers: the new wave

A new generation of wireless transceivers is being intergrated into CMOS IC technology, which so far has been used mainly to realize digital and mixed analog-digital baseband circuits. This article reviews some of the RF CMOS circuit design techniques, and shows how an understanding of the strengths and weaknesses of these circuits influences choice of radio architecture. The CMOS approach to radio design calls for the elimination of discrete components in favor of high levels of on-chip integration which freely use translators and mix analog and digital functionality; in these respects, it departs from traditional RF circuit practices. Successful wireless devices of the future will require that radio system design evolve around these new trends in RF integration     

CMOS双带低噪声放大器

描述了基于CMOS工艺的双带低噪声放大器的设计,其目的是用单个低噪声放大器取代双带收发机(如符合IEEE 802.11a和802.11b/g标准的WLAN)中的两个单独的低噪声放大器.讨论了输入功率和噪声的双带同时匹配以及负载对增益的影响.芯片的加工工艺是0.25μm CMOS混合及射频工艺.并总结和分析了芯片的测试结果.     

Impact of technology scaling and process variations on RF CMOS devices

Inspired by the huge improvement in the RF properties of CMOS devices, RF designers are invading the wireless market with all-CMOS RF transceivers and system-on-chip implementations. In this work, the impact of technology scaling on the RF properties of CMOS; frequency properties, noise performance, linearity, stability, and non-quasi static effects is investigated to provide RF designers with an insight to the capabilities of future CMOS technologies. Moreover, the RF frequency performance of CMOS is investigated under the influence of process variations for different CMOS generations. Using the BSIM4 model, it is found that future CMOS technologies have high prospects in the RF industry and will continue challenging other technologies in the RF domain to be the dominant technology for RF transceivers and system-on-chip implementations.     

Generation of surrogate models of Pareto-optimal performance trade-offs of planar inductors

Systematic design methodologies for wireless transceivers require an efficient design of integrated inductors. Early availability of feasible trade-offs between inductance, quality factor, self-resonance frequency and area, is a key enabler towards the improvement of such design methodologies. This paper introduces such an approach in two steps. First, a Pareto-optimal performance front of integrated inductors is generated by embedding a performance evaluator into a multi-objective optimization tool. Then, starting from the optimal front samples, a surrogate model of the performance front is obtained. Experimental results in a 0.35-μm CMOS technology are provided.     

16.6- and 28-GHz Fully Integrated CMOS RF Switches With Improved Body Floating

This paper presents two fully integrated CMOS transmit/receive (T/R) switches with improved body-floating operations. The first design exploits an improved transistor layout with asymmetric drain-source region, which reduces the drain-source feed-through for body-floated RF switches. In the second design, a switched body-floating technique is proposed, which reconfigures the body-floating condition of a switch transistor in the ON and OFF states. Both designs are fabricated in a standard 0.13-mum triple-well CMOS process. With regard to 2-dB insertion loss, the switch with asymmetric drain-source achieves 28-GHz bandwidth, which is among the highest reported frequencies for CMOS T/R switches. The bandwidth of the switched body-floating design is 16.6 GHz. There is approximately 5 dB better isolation obtained in the switched body-floating design. With the resistive double-well body-floating technique, 26.5- and 25.5-dBm input 1-dB compression point (P_1dB) are obtained, respectively. Both designs consume only 150 mum times 100 mum die area. The demonstrated T/R switches are suitable for high-frequency and wideband transceivers.     

A resonant switch for LNA protection in watt-level CMOS transceivers

An integrated resonant switch designed to protect low-noise amplifier (LNA) circuits in CMOS transceivers is reported. The design implements the receive-path portion of a transmit/receive switch protecting 3-V-process transistors from 5 W (22-V peak) transmit signals while simultaneously helping to achieve a good LNA noise figure on receive and low power loss on transmit. Since the approach is to combine an LNA's matching network and switch functions, the design has no traditional insertion loss on receive. The effective loss to the transmitted signal is less than 0.5 dB using moderate quality inductors (Q>6) and 0.1 dB using Q=12 inductors achievable in most RF-aware CMOS silicon-on-insulator foundries at UHF through S-band frequencies.     

CMOS injection locked oscillators for quadrature generation at radio-frequency

The design of quadrature local oscillators for CMOS wireless transceivers is still one of the most challenging issues. This paper focuses the advantages of injection locking techniques to achieve high-performance quadrature generators. A synchronizing oscillator sets spectral purity while locked oscillators set quadrature accuracy and drive the mixer LO input capacitances. Two different architectures, realized in a 0.18 μm CMOS technology, are illustrated and compared. The first, using LC tank locked oscillators as frequency dividers, is tailored to UMTS and show high driving capability with low power. Simple and accurate equations for the design are reported. The second quadrature generator, employing coupled VCOs driven by an auxiliary VCO, is tailored to DCS1800 and achieves outstanding phase accuracy and phase noise. Experimental results compare favorably against previously published solutions.     

A 1.5 V 3.1 GHz–8 GHz CMOS Synthesizer for 9-Band MB-OFDM UWB Transceivers

This paper presents the design of a CMOS synthesizer for dual-conversion zero-IF2 Multi-Band OFDM (MB-OFDM) transceivers covering the first 9 frequency bands from 3.1GHz to 8.0GHz, each with a bandwidth of 528 MHz. A wideband single-sideband mixer with wideband inductive network loading is proposed. Moreover, a modified transformer-coupled quadrature VCO and interconnection-loading-insensitive layout technique are employed. Fabricated in TSMC 0.18-mum CMOS process and operated at 1.5V, the synthesizer measures phase noise of -127.4dBc/Hz at 10MHz offset, integrated phase noise of 4.43deg, sideband suppression of better than -22 dBc, and a switching time of less than 1ns while consuming 59 mA     

RF CMOS comes of age

All-CMOS radio transceivers and systems-on-a-chip are rapidly making inroads into a wireless market that for years was dominated by bipolar and BiCMOS solutions. It is not a matter of replacing bipolar transistors in known circuit topologies with FETs; the wave of RF CMOS brings with it new architectures and unprecedented levels of integration. What are its origins? What is the commercial impact? How will RF CMOS evolve in the future? This paper offers a retrospective and a perspective.     

集成CMOS锁相环中抑制参考杂散的设计方法

在分析锁相环中参考杂散产生原因的基础上,提出了在不影响其他主要指标的前提下,采用提高电荷泵Up/Down电流匹配,减少电荷注入和时钟馈通问题;匹配PFD的Up/Down支路的对称性;加强电路的隔离等抑制参考杂散的设计方法.通过两次TSMC 0.13μm,PCIExpress收发器中CMOS锁相环电路的成功流片验证了这些方法的有效性.     

Low-power radio-frequency ICs for portable communications

The contributions of integrated circuits to the RF front-end of wireless receivers and transmitters operating in broadcast and personal communications bands are surveyed. It is seen from this that when ICs enable a rethinking of the RF architecture, the wireless device can sometimes become significantly smaller, and consume much less power. Examples are taken from FM broadcast receivers, pagers, and cellular telephone handsets. Many semiconductor technologies are competing today to supply RF-ICs to cellular telephones. The various design styles and levels of integration are compared, with the conclusion that single-chip silicon transceivers, combined with architectures which substantially reduce off-chip passive components, will likely dominate digital cellular telephones in the near future. The survey also projects future trends for ICs for miniature spread-spectrum transceivers offering robust operation in the crowded spectrum. With sophistication in baseband digital signal processing, its increasing interaction with the RF sections, and with increasing experience in simplified radio architectures, all-CMOS radios appear promising in the 900 MHz to 2 GHz bands. A specific CMOS spread-spectrum transceiver project underway at the author's institution is discussed by way of example     

Finite-difference time-domain analysis of integrated ceramic ball grid array package antenna for highly integrated wireless transceivers

This paper presents a study of the integration of an antenna in a ceramic ball grid array package for highly integrated wireless transceivers. The study has been carried out on an 11/spl times/11.66 mm/sup 2/ small microstrip antenna in a thin 48-ball ceramic ball grid array package with the finite-difference time-domain (FDTD) method in C band. The impedance and radiation characteristics of the antenna are examined. More importantly, the loading effects of the complementary metal-oxide-semiconductor (CMOS) chip and bond wires on the performance of the antenna are investigated. It is found that the loading generally increases the impedance bandwidth but decreases the radiation efficiency of the antenna. To minimize detrimental loading, the shield of the antenna from the CMOS chip is considered. A new design has been realized. The new antenna achieves impedance bandwidth of 4.65%, radiation efficiency of 63%, and gain of 5.6 dBi at 5.52 GHz.     

A 64-tap CMOS echo canceller/decision feedback equalizer for 2B1QHDSL transceivers

A 60-MHz 64-tap adaptive finite-impulse-response (FIR) filter chip was fabricated in 1.2-μm CMOS. It can implement either an echo canceler or a decision feedback equalizer for 2B1Q high bit rate digital subscriber line (HDSL) transceivers. The 4.3×4.3 mm², 30000 transistor chip is a completely self-contained adaptive filter which incorporates the least mean square (LMS) algorithm for coefficient updating. The device can be cascaded to implement very long filter lengths, which are often required in high bit rate transceivers. At a 60-MHz clock rate, the echo canceler/decision feedback equalizer chip can accommodate symbol rates in excess of 800 kbaud     

CMOS dual-band variable-gain amplifier for 3G-WCDMA and WLAN dual-mode RF receivers

A dual-band variable-gain amplifier (DBVGA) is presented for integrated 2.2 GHz 3G-WCDMA and 5.2 GHz WLAN transceivers. DBVGA employs a DC-and-RF current steering technique for gain control, which can minimise variations of the noise, 1 dB gain compression point, and input/output impedance when the gain is tuned. The appropriate frequency operation band of DBVGA is jointly controlled by the switched-resonator load and the input stage gate bias, resulting in high cross-band isolation and out-of-band interference rejection. All circuits except the input stages are reused for both bands to have high component reuse. A fully-integrated 0.18 mum CMOS DBVGA has been implemented to verify the proposed design     

An On-Chip Loopback Block for RF Transceiver Built-In Test

This brief addresses the realization of an on-chip block for built-in testing of RF transceivers with the loopback method. Design issues and measurement results are discussed, giving practical insights into closing the signal path between transmitter (Tx) and receiver (Rx) sections. The circuit is intended for cost-efficient production testing of RF front-end blocks with on-chip power detectors and bit-error-rate analysis at baseband frequencies for integrated transceivers operating in the 1.9- to 2.4-GHz range. It can provide 40-200 MHz Tx-Rx frequency shifting and 26-42 dB continuous attenuation while consuming a 0.052-mm² die area in 0.13-mum CMOS technology and ~ 12 mW of power when activated in test mode.