A Novel Approach to Lossy Real-Time Image Compression: Hierarchical Data Reorganization on a Low-Cost Massively Parallel System

This paper discusses an innovative real-time oriented image compression system, based on a simple algorithm designed explicitly to be implemented on a low-cost SIMD computer architecture featuring a much lower power consumption than traditional DSPs or dedicated hardware. For this reason the considered approach is suitable to be integrated on portable systems, where power consumption is a critical design issue.The algorithm, based on a hierarchical decomposition of the input image, has been tested on a special purpose SIMD system, PAPRICA, exploiting its features such as its massive parallelism and its capability to operate on local data as well as to handle hierarchical data structures.According to the proposed approach, the quality of the decompressed image can be traded for a lower power consumption as well as a higher processing speed. A comparison between the discussed algorithm and the standard JPEG compression technique is also presented.     

An efficient hardware implementation of parallel EBCOT algorithm for JPEG 2000

With the augmentation in multimedia technology, demand for high-speed real-time image compression systems has also increased. JPEG 2000 still image compression standard is developed to accommodate such application requirements. Embedded block coding with optimal truncation (EBCOT) is an essential and computationally very demanding part of the compression process of JPEG 2000 image compression standard. Various applications, such as satellite imagery, medical imaging, digital cinema, and others, require high speed and performance EBCOT architecture. In JPEG 2000 standard, the context formation block of EBCOT tier-1 contains high complexity computation and also becomes the bottleneck in this system. In this paper, we propose a fast and efficient VLSI hardware architecture design of context formation for EBCOT tier-1. A high-speed parallel bit-plane coding (BPC) hardware architecture for the EBCOT module in JPEG 2000 is proposed and implemented. Experimental results show that our design outperforms well-known techniques with respect to the processing time. It can reach 70 % reduction when compared to bit plane sequential processing.     

High-speed implementation of fractal image compression in low cost FPGA

Fractal image compression (FIC) is a very popular coding technique use in image/video applications due to its simplicity and superior performance. The major drawback with FIC is that it is very time consuming algorithm, especially when a full search is attempted. Hence, it is very challenging to achieve a real-time operation if this algorithm is implemented on general processors. In this paper, a new parallel architecture with bit-width reduction scheme is implemented. The hardware is synthesized on Altera Cyclone II FPGA whose architecture is optimized at circuit level in order to achieve a real-time operation. The performance of the proposed architecture is evaluated in terms of runtime, peak-signal-to-noise-ratio (PSNR) and compression efficiency. On average the speedup of 3 was attainable through a bit-width reduction while the PSNR was maintained at acceptable level. Empirical results demonstrate that this firmware is competitive when compared to other existing hardware with PSNR averaging at 29.9 dB, 5.82% compression efficiency and a runtime equivalent to video speed of 101 frames per second (fps).     

Subsample-based image compression for capsule endoscopy

The key design challenge in capsule endoscopic system is to reduce the area and power consumption while maintaining acceptable video quality. In this paper, a subsample-based image compressor for such endoscopic application is presented. The algorithm is developed around some special features of endoscopic images. It consists of a differential pulse coded modulation followed by Golomb-rice coding. Based on the nature of endoscopic images, several subsampling schemes on the chrominance components are applied. This scheme is particularly suitable to work with any commercial low-power image sensors that outputs image pixels in a raster scan fashion, eliminating the need of memory buffer, as well as temporary storage (as needed in transform coding schemes). An image corner clipping algorithm is also presented. The reconstructed images have been verified by medical doctors for acceptability. The proposed algorithm has a very low complexity and is suitable for the VLSI implementation. Compared to other transform-based algorithms targeted to capsule endoscopy, the proposed raster-scan-based scheme performs very strongly with a compression ratio of 80% and a very high reconstruction PSNR (over 45 dB).     

基于混合分类和矩形划分的快速分形编码方法*

针对分形图像压缩中矩形划分计算量太大的问题,提出了一种混合分类方法并将其应用于图像的矩不变量,得到了一种基于矩形划分的快速分形编码方法.实验表明,该方法相对于全局搜索,在压缩比和解码质量略有下降的基础上,能极大地提高分形编码速度;与均匀分类方法相比,混合分类法可进一步提高分形编码速度并改善解码图像质量,可以在一定的条件下取得压缩比优势.     

VS1053B编解码器的VDR分布式声音采集卡设计

为了满足未来航行数据记录仪声音采集卡分布式、低成本、低功耗和高可靠性的要求,以STM32F103为核心控制器,结合VS1053B音频编解码芯片和W5300以太网通信芯片设计了一种采用OggVorbis声音编码算法的分布式声音采集卡,给出了声音采集卡的软硬件设计。在硬件设计上,采用了独立的可加载OggVorbis声音编码算法以及内置TCP/IP协议栈的嵌入式芯片,降低了系统的功耗和软件设计的复杂性,增强了系统的灵活性和可靠性。     

Low-complexity and energy efficient image compression scheme for wireless sensor networks

Currently most energy-constrained wireless sensor networks are designed with the object of minimizing the communication power at the cost of more computation. To achieve high compression efficiency, the main image compression algorithms used in wireless sensor networks are the high-complexity, state-of-the-art image compression standards, such as JPEG2000. These algorithms require complex hardware and make the energy consumption for computation comparable to communication energy dissipation. To reduce the hardware cost and the energy consumption of the sensor network, a low-complexity and energy efficient image compression scheme is proposed. The compression algorithm in the proposed scheme greatly lowers the computational complexity and reduces the required memory, while it still achieves required PSNR. The proposed implementation scheme of the image compression algorithm overcomes the computation and energy limitation of individual nodes by sharing the processing of tasks. And, it applies transmission range adjustment to save communication energy dissipation. Performance of the proposed scheme is investigated with respect to image quality and energy consumption. Simulation results show that it greatly prolongs the lifetime of the network under a specific image quality requirement.     

哈希编码结合空间金字塔的图像分类

目的 稀疏编码是当前广泛使用的一种图像表示方法,针对稀疏编码及其改进算法计算过程复杂、费时等问题,提出一种哈希编码结合空间金字塔的图像分类算法。方法 首先,提取图像的局部特征点,构成局部特征点描述集。其次,学习自编码哈希函数,将局部特征点表示为二进制哈希编码。然后,在二进制哈希编码的基础上进行K均值聚类生成二进制视觉词典。最后,结合空间金字塔模型,将图像表示为空间金字塔直方图向量,并应用于图像分类。结果 在常用的Caltech-101和Scene-15数据集上进行实验验证,并和目前与稀疏编码相关的算法进行实验对比。与稀疏编码相关的算法相比,本文算法词典学习时间缩短了50%,在线编码速度提高了1.3～12.4倍,分类正确率提高了1%～5%。结论 提出了一种哈希编码结合空间金字塔的图像分类算法,利用哈希编码代替稀疏编码对局部特征点进行编码,并结合空间金字塔模型用于图像分类。实验结果表明,本文算法词典学习时间更短、编码速度更快,适用于在线词典学习和应用。     

基于混合域的改进SPIHT图像编码算法

为使图像压缩编码算法同时具有较高的压缩比和较好的图像复原质量,提出了一种基于Contourlet与小波变换的混合域图像编码方案,并在分析SPIHT算法的基础上进一步改进,取消了SPIHT算法中对LIS表的分类,统一按照先子代后孙代的小波空间树顺序进行编码.仿真实验结果表明,提出的混合域图像压缩编码方案是一种高效的数字图像压缩算法,与SPIHT算法相比,该算法的重建图像具有更好的视觉效果,而且提高了编码速度.     

基于自适应分块的快速分形图象压缩

对Ｆｉｓｈｅｒ的自适应分块分形压缩方法进行了改进，提出了基于相对矩的三级分类方法和多分辨率相似匹配方法，并以此为基础实现了一种新的基于四叉树分块的分形编码算法。实验表明，在压缩比大致相同、信噪比略高的情况下，新算法的编码速度有明显提高。     

Full-frame cosine transform image compression for medical and industrial applications

Full-frame image compression capable of a 101 ratio or higher was developed for radiological applications where block artifacts are not acceptable. Applications in machine vision with similar stringencies can utilize the same principles and hardware design. Subsecond compression speed for image sizes up to 1K × 1K × 8 can be achieved by DMA and DSP designs using off-the-shelf components and customized bus architecture. Successions of completed hardware module design and proposed enhancements are reported with technical details. The possibility of 512 × 512 × 8 image compression in real time is also explored with design examples.     

基于Lagrange的H．264率失真编码优化算法

为了进一步提高编码速度，促进视频编码技术在多媒体通信领域的实际应用，本文对率失真视频编码的关键算法进行了深入的研究并提出了其优化方法，并从信息论理论出发，着重围绕图像压缩的理论，利用率失真特征数学模型、拉格朗日乘子法，对目前新一代的H．264视频标准进行编码算法模式选择，试图从最根本的理论角度探讨信源编码，以便得到更高的压缩比、更好的图像质量和更快的编码速度。最后，利用本文提出的编码模式优化算法，对H．264的JM61e（JUT Test Model）系统测试模型的性能进行全面测试。     

An ASIC implementation of Kohonen's map based colour image compression

This paper presents a new hardware design for a neural network based colour image compression. The compressed image consists of a colour palette containing few best colours and the coded image. Kohonen's map neural network is applied to construct the colour palette and the coded image, both forming the compressed image. The Kohonen's map based compression results in linear time complexity (in the size of the image). It is advantageous over traditional JPEG in colour quantization applications and compression of images with limited colours. The architecture of the hardware unit is based on single instruction multiple data methodology. The architecture has been implemented in an application specific integrated circuit and results show that the proposed design achieves high speed allowing inputs at a video rate for compression of images up to size of 512×512 with low area requirement.     

基于分形编码和LIC混沌系统的图像压缩加密算法

随着数字图像在网络中的广泛应用,其在安全、传输、存储等方面的问题亟待解决。提出的算法为分形编码提供了新型安全方案,分形图像编码具有压缩比高和重构质量高的特点,而混沌的不可预测性和初值敏感性适用于图像加密,将分形编码和混沌加密有效结合可以充分发挥两者的优势。此外,通过耦合增强构造新的混沌系统,改善了种子映射复杂度低、混沌范围有限等问题,并设计了置乱扩散同时进行的加密结构来提高算法效率。实验表明,提出的算法的密钥空间大、密钥敏感性强、相邻像素相关系数和信息熵都接近理想值,能够抵抗多种常见攻击,且加密速度更快,能满足实际应用的需要。压缩性能方面,在满足重构视觉质量的同时达到了较其他方案更高的压缩比。     

一种改进的无表SPIHT算法

SPIHT算法是一种基于小波变换,压缩编码效率很高的静止图像压缩编码算法,传统的SPIHT算法主要基于软件实现.本文提出一种改进的更易于硬件实现的无列表SPIHT算法：采用状态标示符取代动态链表操作来记录集合分割信息,进而把整个编码过程都简化为简单的逻辑运算.基于本算法设计出了SPIHT编码器FPGA的有效实现.实验表明,该算法易于实现、节约资源、效率高、运算速度快,为硬件实现高速图像压缩编码提供了一种新的有效的方法.     

基于自适应分类的快速分形编码方法

编码时间过长是目前分形图像压缩存在的主要问题,尽管对图像块进行分类是解决这一问题的一类重要方法,然而诸多分类方法中仍普遍存在着编码速度与解码质量之间的矛盾.针对这一问题,在给出衡量分类方法性能指标体系的基础上,首先提出了一种自适应分类方法,从而较好地解决了这一矛盾,然后将该方法运用于质心分类上,并结合满意匹配得到了一种快速的分形编码方法.实验表明,与原来的均匀分类方法相比,在取得相同压缩比的前提下,该方法可进一步提高分形编码的速度和改善解码图像质量.     

基于GEP的分形图像压缩并行算法

传统图像压缩算法存在图像压缩率不高、寻找最优分形图像压缩编码速度慢的不足。为此,提出一种基于基因表达式编程(GEP)的分形图像压缩并行算法。分析二值图像压缩变换的求解过程,给出分形图像基因和染色体的编码表示,设计适应度函数,研究GEP遗传进化操作的编码步骤。在PC机群上的实验结果表明,与串行算法相比,该算法的图像压缩率较高、运行速度较快,具有线性加速比。     

Machine Learning-Based Pruning Technique for Low Power Approximate Computing

Approximate Computing is a low power achieving technique that offers an additional degree of freedom to design digital circuits. Pruning is one of the types of approximate circuit design technique which removes logic gates or wires in the circuit to reduce power consumption with minimal insertion of error. In this work, a novel machine learning (ML) -based pruning technique is introduced to design digital circuits. The machine-learning algorithm of the random forest decision tree is used to prune nodes selectively based on their input pattern. In addition, an error compensation value is added to the original output to reduce an error rate. Experimental results proved the efficiency of the proposed technique in terms of area, power and error rate. Compared to conventional pruning, proposed ML pruning achieves 32% and 26% of the area and delay reductions in 8*8 multiplier implementation. Low power image processing algorithms are essential in various applications like image compression and enhancement algorithms. For real-time evaluation, proposed ML optimized pruning is applied in discrete cosine transform (DCT). It is a basic element of image and video processing applications. Experimental results on benchmark images show that proposed pruning achieves a very good peak signal-to-noise ratio (PSNR) value with a considerable amount of energy savings compared to other methods.     

Accelerating embedded image processing for real time: a case study

Many image processing applications need real-time performance, while having restrictions of size, weight and power consumption. Common solutions, including hardware/software co-designs, are based on Field Programmable Gate Arrays (FPGAs). Their main drawback is long development time. In this work, a co-design methodology for processor-centric embedded systems with hardware acceleration using FPGAs is proposed. The goal of this methodology is to achieve real-time embedded solutions, using hardware acceleration, but achieving development time similar to that of software projects. Well established methodologies, techniques and languages from the software domain—such as Object-Oriented Paradigm design, Unified Modelling Language, and multithreading programming—are applied; and semiautomatic C-to-HDL translation tools and methods are used and compared. The methodology is applied to achieve an embedded implementation of a global vision algorithm for the localization of multiple robots in an e-learning robotic laboratory. The algorithm is specifically developed to work reliably 24/7 and to detect the robot’s positions and headings even in the presence of partial occlusions and varying lighting conditions expectable in a normal classroom. The co-designed implementation of this algorithm processes 1,600 × 1,200 pixel images at a rate of 32 fps with an estimated energy consumption of 17 mJ per frame. It achieves a 16× acceleration and 92 % energy saving, which compares favorably with the most optimized embedded software solutions. This case study shows the usefulness of the proposed methodology for embedded real-time image processing applications.     

基于三维块特征分类的彩色图像编码

将彩色图像的R、G、B三帧作为整体考虑，并利用三维离散余弦变换（3D-DCT）进行压缩编码是彩色图像编码的新方法。为了进一步提高基于该方法的彩色图像编码效率，该文提出了基于三维块特征分类的彩色图像编码算法。实验结果表明，该方法同传统彩色图像编码方法相比，在保证相同的恢复图像效果时，将压缩比提高了约22%，也能够进一步提高基于3D-DCT的彩色图像压缩编码的性能。