A 300 GHz quasioptical schottky frequency doubler

A monolithically integrated frequency multiplier based on a planar antenna providing impedance matching has been realized and measured at 300 GHz. Each of the two circuits comprises a Schottky varactor, slot antenna, MIM-capacitor and microstrip bias feed. The theoretical design aspects, the technological approach and the RF performance are addressed.     

140 GHz二倍频器的研制

太赫兹通信中本振链输出功率无法满足实际需求,因此提出一种基于肖特基变容二极管的宽带、高效率140 GHz 二倍频器设计方案。该倍频器结构基于波导腔体石英基片微带电路的混合集成方式实现。采用三维有限元与非线性谐波平衡联合仿真方法,实现了倍频器的最优化设计。根据仿真结果,完成了140 GHz二倍频器的加工、制作与测试工作。实测结果表明,在20 dBm的驱动功率下,倍频器的输出功率最高达6.6 mW,倍频效率7.15%;输入功率23 dBm对应的最大输出功率可达11.2 mW。该器件的成功研制使得实现太赫兹通信中的本振链成为可能。     

A frequency doubler for 200 GHz with a planar Schottky varactor

A frequency doubler for 200 GHz utilising a planar surface channel Schottky varactor was designed, constructed and tested. The doubler employes novel split-waveguide mount design with two sliding backshorts at both input and output waveguides. The theoretical maximum efficiency of the doubler is 44.0 % with input power level of 32 mW and the maximum output power is 16.5 mW with input power level of 50 mW. The measured maximum efficiency of the doubler was 7.1 % and the maximum output power was 2.6 mW     

150 GHz大功率二倍频器

基于六阳极结反向串联型砷化镓平面肖特基容性二极管,采用平衡式二倍频器结构,成功研制出一种大功率150 GHz二倍频器。使用三维电磁场与非线性谐波平衡联合仿真方法,提高了仿真结果和实际的吻合度,并根据设计结果完成倍频器的加工、装配和测试。倍频器在输出频率为146~158 GHz下的倍频效率达到7%以上;在输出频率为154 GHz时,倍频效率达到12%,输出功率达到71 mW。     

基于平面肖特基二极管的220 GHz二倍频器

介绍了一个基于平面肖特基二极管的220 GHz倍频器。该倍频器工作在室温下,结构简单。为了实现倍频,将一个具有4个反向串联肖特基结的变容二极管安置在石英基片上,直流偏置通过一个石英微带构成的低通滤波器加到二极管上。所有的石英电路基片都用导电胶粘接在波导腔体上,波导腔体是E面剖分的,表面镀金。220 GHz倍频器的测试结果表明,在选择合适的偏置电阻时,该倍频器具有15 mW的输出功率和5%的效率。在213~230 GHz频段,二倍频器的输出功率均在10 mW以上,且带内的功率波动非常小。     

多阳极220GHz倍频器单片设计

介绍了一款基于GaAs肖特基二极管单片工艺的220 GHz倍频器的设计过程以及测试结果。为提高输出功率,倍频器采用多阳极结构,8个二极管在波导呈镜像对称排列,形成平衡式倍频器结构。采用差异式结电容设计解决了多阳极结构端口散射参数不一致问题,提高了倍频器的转换效率和工作带宽。对设计的倍频器进行流片、装配和测试,测试结果显示：倍频器在204～234 GHz频率范围内,转化效率大于15%;226 GHz峰值频率下实现最大输出功率为90.5 mW,转换效率为22.6%。设计的220 GHz倍频器输出功率高,转化效率高,工作带宽大。     

23GHz 0.2μm PHEMT倍频器

应用异或逻辑运算，对输入信号进行非线性变换，产生偶次高阶谐波分量，实现二倍频功能。改进的异或门中，利用LC谐振回路作为异或门的负载，提取出希望得到的频率分量。利用三阶巴特沃斯低通滤波器，解决了芯片输入、输出接口问题。选用微带线和衬底接地的共面波导等不同结构的电感实现形式，充分利用了芯片面积。测试表明，芯片可以在22．62～23．24GHz频率范围内实现二倍频输出。     

A high efficiency 46 to 92 GHz all microstrip frequency doubler

Using packaged GaAs varactor diodes, a high efficiency 46 to 92 GHz frequency doubler has been developed. Microstrip circuits have been used to match the input and output impedances presented by the diode. A conversion loss of 8 to 10 dB was measured. This doubler circuit is useful for W-band (75 to 110 GHz) integrated circuit receivers and transceivers. The use of microstrip circuit can drastically reduce the fabrication cost in addition to size and weight.     

高功率110 GHz平衡式肖特基二极管频率倍频器

高频段的太赫兹信号通常是由多个倍频器级联输出的,因此要求倍频链路的前级必须具备高输出功率的能力。为了提升太赫兹倍频器的功率容量和效率,结合高频特性下肖特基二极管有源区电气模型建模方法,采用高热导率的陶瓷基片,利用对称边界条件,在HFSS和ADS中实现对倍频器电路的分析和优化,研制出了高功率110 GHz平衡式倍频器。最终测试结果表明,驱动功率为28 dBm左右时,该倍频器在102~114.2 GHz的工作带宽内的最高输出功率和效率分别为108 mW和17.6%,为链路后续的二倍频和三倍频提供足够的驱动功率。     

440 GHz串联式宽带二倍频器设计

研究了基于平面肖特基变容二极管的440 GHz串联式宽带二倍频器。在基波功率20 mW驱动下,仿真显示在400~480 GHz变频损耗小于10 dB,输出功率大于2 mW,相对带宽18%。整个倍频器制作在一块30 μm厚的石英基片上,无机械调谐结构,结构简单,便于加工。     

A broadband 800 GHz Schottky balanced doubler

A broadband planar Schottky balanced doubler at 800 GHz has been designed and built. The design utilizes two Schottky diodes in a balanced configuration on a 12 μm thick gallium arsenide (GaAs) substrate as a supporting frame. This broadband doubler (designed for 735 GHz to 850 GHz) uses a split waveguide block and has a relatively simple, fast, and robust assembly procedure. The doubler achieved ≈10% efficiency at 765 GHz, giving 1.1 mW of peak output power when pumped with about 9 mW of input power at room temperature     

基于分离式二极管的220GHz 高效率倍频器

在分离式二极管的基础上,实现了220 GHz高效率的二倍频器结构。该倍频器的电路在450 μm宽,2.7 mm长的50 μm石英基片上实现。测试结果表明,在室温下当驱动功率在46.4~164 mW时,在214~226 GHz的频段内能够实现大于16%的倍频效率。另外,当驱动功率在161 mW时,倍频器在218 GHz频点能够输出最高功率32 mW,并且在多个频点拥有高于20%的倍频效率。实验证明,所实现的二倍频器能够作为660 GHz倍频链路的驱动前级使用。     

GaAs monolithic 1.5 to 2.8 GHz tunable ring oscillator withaccurate quadrature outputs

The design, fabrication and characteristics of a 1.5 to 2.8 GHz tunable ring oscillator with two quadrature outputs are described. Tuning range is 1.3 GHz or 60.5% bandwidth. The phase difference between the two outputs is proved to be 90°. The oscillator phase noise is -81.27 dBc/Hz at 100 kHz offset from the carrier at 2.736 GHz     

一种用于IR-UWB收发器的4GHz正交输出小数频率综合器

本文针对工作于3.1GHz到5GHz频段的IR-UWB收发器,设计了一种4GHz小数频率综合器。该频率综合器采用0.18μm混合&射频CMOS工艺实现,其输出频率范围为3.74GHz到4.44GHz。通过使用多比特量化的∑-△调制器,该频率综合器在参考频率为20MHz时的输出频率分辨率达到15Hz。测试结果表明,该频率综合器的正交信号输出幅度失配和相位误差分别低于0.1dB和0.8º。该频率综合器的输出相位噪声达到-116dBc/Hz@3MHz,频谱杂散低于-60dBc。在1.8V电源电压下,该频率综合器的核心电路功耗仅为38.2mW。     

High accuracy frequency offset correction with adjustable acquisition range in OFDM systems

A new carrier frequency offset estimation scheme in orthogonal frequency-division multiplexing (OFDM) systems is proposed in this paper. Both the carrier frequency offset acquisition and tracking are based on a fixed-length training-symbol-block, which consists of multiple small identical training symbols. When each training symbol is shortened, the number of training symbols in the training-symbol-block should be increased accordingly to keep the total training-symbol-block length fixed. The proposed scheme extends Moose's estimator, where the estimation error is only dependent on total training symbol energy and cannot be reduced any more, once the total training symbol energy is determined. The proposed scheme can shorten each training symbol in a training-symbol block and select an appropriate estimator simultaneously, which can lead to further reduction of estimation error and increase of acquisition range, even with the total training-symbol-block energy being fixed. Performance analyzes for the proposed scheme in both the additive white Gaussian noise channel (AWGN) and the multipath channel are also presented in this paper. All estimators in the proposed scheme are conditionally unbiased, and simulation results demonstrate that they can work well both in the multipath channel and in the AWGN channel.     

A GaAs monolithic 6 GHz low-noise amplifier for satellite receivers

A design approach and accurate modeling techniques developed to realize a GaAs monolithic, 6-GHz, two-stage, low-noise amplifier (LNA) with a measured 1.7 dB noise figure and associated 21 dB gain are discussed. This self-biased LNA design, with chip dimensions of 80 mil×135 mil, utilizes an ion-implantation FET model which predicts measured in-band amplifier gain to within 0.5 dB and peak frequency response to within 4%. The derived noise parameter estimation process, which uses a Gaussian elimination technique to predict the measured noise figure to within 0.2 dB, reduces a set of complex, binomial equations to simple relationships which are easily programmable. A deep-recessed gate realization of this LNA design demonstrates that LNA low-noise performance is achievable under FET saturated drain current conditions     

One-chip GaAs monolithic frequency converter operable to 4 GHz

The frequency converter combines a feedback amplifier, a differential amplifier, a double-balanced mixer, a voltage-controlled oscillator, and an IF amplifier on a 1-mm² GaAs chip. The FET circuits were matched by digital IC design rather than by the distributed element network technique, to use the substrate more effectively. Self-aligned WSi/Au gates 1.5 μm long were used, and the resistance in conventional WSi gates was reduced to enhance microwave characteristics. At 4 GHz, the conversion gain is 18 dB, the double-sideband noise is 11.8 dB and the output power is 5.6 dBm     

W-band monolithic frequency doubler using vertical GaAs varactor diode with n/sup +/ buried layer

A W-band monolithic frequency doubler was designed and fabricated using a vertical GaAs varactor diode that has an n/sup +/ buried layer and uses a mesa isolation process. An output power of 30 mW was obtained from this chip at 93 GHz with a conversation efficiency of 12%. This is believed to be the first reported W-band monolithic varactor diode frequency doubler.<>     

A minaturized broad-band MMIC frequency doubler

A miniaturized broadband balanced MMIC (monolithic microwave integrated circuit) frequency double, composed of a common-gate FET and a common-source FET directly connected to each drain electrode, has been proposed and demonstrated. The doubler is designed and fabricated as a miniaturized function module using a conventional two-gate FET configuration, active trapping, and active impedance matching. The doubler design has been performed through phase error estimation, gate width optimization, and gate-source voltage optimization. The phase error estimation in a nonlinear condition has eliminated phase error compensation circuits. The fabricated chip size is only 0.5 mm×0.5 mm, which is about 1/10 the area of previously reported doublers. A conversion loss of 8-10 dB, a fundamental frequency suppression better than 17 dB, and an input return loss better than 8 dB are obtained in the output frequency range from 6 to 16 GHz. The broadband doubler as a miniaturized MMIC function module can be applicable to small-size oscillator MMICs and multifunction MMICs     

A D-band frequency doubler with GaAs Schottky varistor diodes

A D-band hybrid frequency doubler is developed with varistor diodes. The multiplier circuit substrate is RT/duroid 5880 with a thickness of 0.127 mm. In the circuit, the improved waveguide to unilateral finline transition is implemented with lower transition loss by cutting off high-order modes, and the reliability of the mounted circuit is enhanced with increased mounting groove depth. The D-band doubler exhibits the highest efficiency of 2% at 150.2 GHz; the typical efficiency is 1.9% from 150 to 150.5 GHz. The experimental and simulated results are in good agreement.