数字阵列模块老炼系统的研制

数字阵列模块的筛选是剔除早期失效、提高产品使用可靠性的重要手段,而电老炼是其中重要的环节.针对数字阵列模块筛选的具体需求,提出了研究实用化的电老炼系统并详细阐述了系统设计方案,以达到提高产品可靠性的目的.     

△Vbe测试条件的确定方法

△Vbe是晶体管的一个重要参数,它与晶体管的热阻有一个定量的关系,它反映了管子的功耗能力,对晶体管的封装工艺及失效分析有着重要的指导意义.一直以来我公司在测试△Vbe时都是参考其它公司的测试条件,以下章节介绍了如何确定△Vbe的测试条件.以我公司的TO-220封装的某器件为例来进行试验.     

双极晶体管△Vbe瞬态热阻测试法精度修正

对双极型晶体管△VBE瞬态热阻测试法中晶体管壳温波动和测量延迟时间的误差进行了分析,提出了提高测试精度的误差修正方法.以3DK457(F0金属封装)双极晶体管为实验对象进行了研究,结果表明:晶体管瞬态热阻△VBE修正测试方法与红外扫描热像法和标准电学法相比较在保持较高测量精度的前提下,测试成本低,测量效率高.     

双极晶体管ΔV_(be)瞬态热阻测试法精度修正

对双极型晶体管ΔVBE瞬态热阻测试法中晶体管壳温波动和测量延迟时间的误差进行了分析,提出了提高测试精度的误差修正方法.以3DK457(F0金属封装)双极晶体管为实验对象进行了研究,结果表明:晶体管瞬态热阻ΔVBE修正测试方法与红外扫描热像法和标准电学法相比较在保持较高测量精度的前提下,测试成本低,测量效率高.     

双极晶体管△Vbe瞬态热阻测试法精度修正

对双极型晶体管△VBE瞬态热阻测试法中晶体管壳温波动和测量延迟时间的误差进行了分析,提出了提高测试精度的误差修正方法.以3DK457(F0金属封装)双极晶体管为实验对象进行了研究,结果表明:晶体管瞬态热阻△VBE修正测试方法与红外扫描热像法和标准电学法相比较在保持较高测量精度的前提下,测试成本低,测量效率高.     

双极晶体管ΔVbe瞬态热阻测试法精度修正

对双极型晶体管ΔVBE瞬态热阻测试法中晶体管壳温波动和测量延迟时间的误差进行了分析，提出了提高测试精度的误差修正方法．以3DK457(F0金属封装)双极晶体管为实验对象进行了研究，结果表明：晶体管瞬态热阻ΔVBE修正测试方法与红外扫描热像法和标准电学法相比较在保持较高测量精度的前提下，测试成本低，测量效率高．     

晶体管阵列老炼时结温测量方法研究

对PNP晶体管阵列采用矩阵热阻法和温度敏感参数法(TSP)两种结温测量的方法进行对比分析研究,并采用红外热像进行试验验证。结果表明,采用矩阵热阻法可以综合考虑各芯片之间的耦合作用,但由于矩阵热阻法试验程序较为复杂,且需要多次换算,从而较容易引入误差。而温度敏感参数法操作简单,测量准确,可以实现实时监测阵列管工作状态下的结温。     

一种可重构算子阵列结构的功耗评估方法

介绍了一种面向新型FPGA结构—可重构算子阵列的功耗评估方法。分析了可重构算子阵列结构的功耗构成,同现有的功耗评估方法进行对比,提出基于最大功耗的评估策略。可重构算子和互连单元采用自动测试矢量生成(ATPG)方法计算最大功耗,互连线段的功耗则通过RC等效模型得到。将所有被使用的资源功耗相加,得到该设计所对应的最大功耗值,作为结构探索和在实际应用中阵列规模选取、布局布线优化的指导。     

基于单电子晶体管图像信号处理应用研究

研究了单电子晶体管的特性，文章提出一种基于单电子晶体管阵列的传输特性实现CNN方法，设计构成CNN。仿真结果表明，所设计的硬件电路具有结构简单、功耗低、频率特性好．将其应用于图像处理具有一定的灵活性和通用性。     

固态组件冷板热扩展体性能分析

固态技术和相控阵雷达是雷达领域研究的重要课题,固态末级功放组件、T／R组件内晶体管等大功耗、高热流密度器件在冷板上会形成局部热障,产生扩展热阻。文中对扩展热阻特性进行研究,探讨了影响扩展热阻的三个参数：厚度、对流换热系数和导热系数,并分析得出提高热扩展体的等效导热系数是减小扩展热阻、强化传热最有效的技术途径之一,最后在此基础上利用数值模拟方法对铜块、热管及蒸发室等三种热扩展体的散热性能进行了分析和比较。     

Forward body bias for microprocessors in 130-nm technology generation and beyond

Device and test chip measurements show that forward body bias (FBB) can be used effectively to improve performance and reduce complexity of a 130-nm dual-V/sub T/ technology, reduce leakage power during burn-in and standby, improve circuit delay and robustness, and reduce active power. FBB allows performance advantages of low-temperature operation to be realized fully without requiring transistor redesign, and also improves V/sub T/ variations, mismatch, and saturation transconductance and output resistance product (g/sub m//spl times/r/sub o/).     

Non-linear thermal modeling of DMOS transistor and validation using electrical measurements and FEM simulations

The relevance of thermally non-linear silicon material models for transient thermal FEM simulations of smart power switches (SPS) is proved by a power silicon test device consisting of two power transistors and eleven integrated temperature sensors distributed over the silicon die. The test device is heated up by turning on an integrated power transistor in short-circuit for several milliseconds at two different initial temperatures. These thermal events correspond to a real situation that can occur in the application. The power dissipation in the power transistor is calculated from the measured source current and drain-source voltage, and subsequently used as an input to the FEM simulation. The temperature change on the test chip is measured by the integrated temperature sensors. An FEM model of the test chip encapsulated in a plastic package has been built in the FlexPDE simulator. The emphasis is put on the macroscopic modeling of the power transistor where an electro-thermal approach is reduced to a purely thermal one. Finally, the thermal events are simulated using FEM and compared to the temperature measurements. The results have shown that our modeling approach including non-linear properties of silicon can be used to investigate the thermal transients in SPS devices with high accuracy.     

Thermal properties of very fast transistors

Recent predictions that thermal effects will limit future transistor speed improvement motivated an interest in predicting and measuring these effects. A mathematical model of the three-dimensional transient heat flow problem is presented which takes into account the physical structure of the device and the actual region of power dissipation. At any point within the device, the model predicts the time-dependent temperature response to a change in power dissipation. A new method of measuring the local time-dependent thermal behavior of small bipolar transistors is described and used to verify the model. It was found that the thermal spreading resistance becomes important in silicon transistors when the emitter stripe dimensions approach 1 µ. Furthermore, the thermal response is much slower than the electrical response. Also, it was confirmed that adjacent devices in integrated circuits are essentially thermally isolated as far as thermal spreading resistance is concerned.     

Measurement of junction temperature of an AlGaAs/GaAsheterojunction bipolar transistor operating at large powerdensities

An electrical method to determine the junction temperature of a power bipolar transistor is presented. The success of this method does not rely on the constancy of thermal resistance over the wide range of operating temperatures. It is hence suitable for transistors operating at high power densities where conventional measurement techniques would not apply. Using this method, we establish that the junction temperature can be 40°C higher than the product of the low temperature thermal resistance and the power dissipation     

Modeling thermal effects on MOS I-V characteristics

The temperature distribution in a MOS transistor caused by power dissipation within the device has been calculated by solving the heat diffusion equation. Using this temperature distribution, IV characteristics of a MOS device as modified by thermal effects are calculated. The predicted behavior matches reported experimental observations; in particular, the negative dynamic resistance seen in the saturation region of devices operating at elevated power densities.     

照明用大功率LED散热研究

大功率LED体积小、工作电流大,输入功率中大部分转化为热能,散热是需要解决的关键技术.文章介绍了大功率LED热设计的方法,针对大功率LED的封装结构,建立了热传导模型;对某照明用大功率LED阵列进行了散热设计,通过仿真分析和热评估试验验证了所采用的散热方法和设计的散热器满足LED阵列的散热要求.     

Effect of collector voltage and collector current on junction temperature

Experiments have been carried out on the 2N929 transistor to investigate the effect of collector voltage and collector current on junction temperature. The results indicate that at constant power dissipation increasing the collector voltage will increase the junction temperature and give the apparent effect of a higher thermal resistance.     

微波功率晶体管的热失效分析

微波功率晶体管是微波功率放大器中的核心器件,其热性能在很大程度上决定于封装管芯的管壳.针对某型号的微波功率晶体管在进行生产筛选的功率老化试验时出现的热失效问题进行分析与讨论,最终确定器件管壳内用于烧结管芯的氧化铍(BeO)上的多层金属化层存在质量缺陷,使管芯到BeO的热阻增大,因此出现了老化时部分器件失效现象.提出了预防措施,既可避免损失,也能保证微波功率晶体管在使用中的可靠性.     

The effects of BJT self-heating on circuit behavior

This study demonstrates the circuit and device conditions under which self-heating can significantly affect bipolar junction transistor (BJT) circuit behavior. Simple quantitative measures are supplied that allow estimation of thermally induced errors in BJT small-signal parameters, based on knowledge of the transistor geometry and its Early voltage. It is shown that errors in output admittance and reverse transadmittance can be significant without much power dissipation, especially when the base and emitter driving impedances are small. Other small-signal parameters are less affected unless the power dissipation becomes significant. Thermal effects in large-signal DC analysis can be significant in precision analog circuits that depend on close transistor matching; such circuits can also exhibit long settling-time tails due to long thermal time constants. ECL (emitter-coupled logic) delay is shown to be insensitive to self-heating. These effects are demonstrated through simulations of a variety of circuits using versions of SPICE modified to include physics-based models for thermal impedance     

Implications of thermal instability on HBT power amplifier reliability

Thermal stability is one of several important performance requirements for RF power amplifier modules used for cellular applications. In this work, the conditions for thermal instability in an HBT array for shared and individual ballast configurations are evaluated using experimental results from RF biased life test (RFHTOL) and ADS simulations. The instability is modest under nominal operating conditions, but becomes more severe at elevated temperatures which are frequently used in accelerated reliability tests such as RFHTOL. Thermally unstable power cells exhibit current crowding where one or two cells hog most of the current, resulting in localized hot spots from increased power dissipation density. This paper discusses the link between reliability failures during RFHTOL reliability testing and the thermal stability of HBT arrays used in a power amplifier. Shared ballast arrays are shown to be less thermally stable than individually ballasted arrays and thus have more failures during RFHTOL testing. Electro-thermal results indicate the layout aspects of power amplifier module also play an important role in determining junction temperatures for various stages.