倒装焊中复合SnPb焊点形态模拟

本文给出了倒装焊(flip-chip)焊点形态的能量控制方程,采用Surface Evolver软件模拟了倒装焊复合SnPb焊点(高Pb焊料凸点,共晶SnPb焊料焊点)的三维形态.利用焊点形态模拟的数据,分析了芯片和基板之间SnPb焊点的高度与焊点设计和焊接工艺参数的关系.研究表明:共晶SnPb焊料量存在临界值,当共晶SnPb焊料量小于临界值时,焊点的高度等于芯片上高Pb焊料凸点的半径值;当共晶SnPb焊料量大于临界值时,焊点的高度随共晶SnPb焊料量的增加而增加.另外,采用无量纲的形式给出了焊点高度与共晶焊料量、焊盘尺寸、芯片凸点的尺寸,芯片重量之间的关系模型,研究结果对倒装焊焊点形态的控制、工艺参数的优化和提高焊点可靠性具有指导意义.     

模板对倒装焊焊点形态的影响及其可靠性研究

本文通过用于焊点形态预测软件SURFACE EVOLVER的输入数据文件,得到倒装焊焊点形态.参考模板开口指导说明(IPC-7525),拟定模板开口方案,得到相应的焊点形态.通过建立有限元模型,运用ANSYS软件对含铅焊点在热循环加载条件下的应力应变和疲劳寿命进行分析.根据预测得到的热疲劳寿命,找出了适合本文模型的模板结构参数,同时分析了其它设计与工艺参数和焊点可靠性之间的关系.     

倒装焊封装中无铅焊点在封装工艺中的热机械力学分析

采用粘塑性Garofalo—Arrhenius模型描述无铅焊料的蠕变行为，确定了96．5Sn3.5Ag焊点材料的模型参数。采用与固化过程相关的粘弹性力学模型描述倒装焊底充胶的力学行为。利用有限元法模拟了无铅板上倒装焊在封装工艺及热循环条件下的应力应变行为。结果表明由于无铅技术在封装中的引入，封装工艺对倒装焊器件的影响更为重要。     

热循环对通孔插装SnCuTi焊点导电性能的影响

研究了热循环条件下无铅钎料Sn-0.7Cu-0.008Ti/Cu基板形成的通孔插装焊点的导通电阻的变化规律。结果表明:随着热循环次数的增加,焊点电阻增加,高温时的电阻大于低温时的电阻;在相同热循环条件下,随着通孔间隙的增加,焊点电阻降低。热循环过程中焊点电阻增加的原因是由于焊点出现裂纹所致。当热循环次数达到1 000次时,焊点的电阻增加仍不明显,表明通孔插装的Sn-0.7Cu-0.008Ti/Cu焊点有较高的导电可靠性。     

倒装焊结构对太赫兹对数周期天线的影响

设计了一种倒装焊结构,用于340GHz的肖特基二极管探测器。探测单元是基于砷化镓（GaAs）工艺设计的。薄膜陶瓷支撑层旨在为太赫兹检测单元提供封装。通常,导电胶用作天线和输出电路之间的附接。分别对倒装焊结构和无倒装焊结构（类引线键合结构）模型对太赫兹接收天线性能的影响进行研究。为了比较的目的,使用相同的测试系统表征FC结构模型和无FC结构模型（引线键合结构）。通过引线键合与倒装焊测试增益的结果比较,表明倒装焊结构可以作为大规模太赫兹检测阵列封装的低成本解决方案。     

倒装焊SnPb焊点热循环失效和底充胶的影响

采用实验方法 ,确定了倒装焊 Sn Pb焊点的热循环寿命 .采用粘塑性和粘弹性材料模式描述了 Sn Pb焊料和底充胶的力学行为 ,用有限元方法模拟了 Sn Pb焊点在热循环条件下的应力应变过程 .基于计算的塑性应变范围和实验的热循环寿命 ,确定了倒装焊 Sn Pb焊点热循环失效 Coffin- Manson经验方程的材料参数 .研究表明 ,有底充胶倒装焊 Sn Pb焊点的塑性应变范围比无底充胶时明显减小 ,热循环寿命可提高约 2 0倍 ,充胶后的焊点高度对可靠性的影响变得不明显     

倒装焊陶瓷封装失效模式分析及失效机理研究

随着封装技术的发展,倒装焊技术得到广泛的应用,倒装焊的研究也越来越广泛深入。文章阐述了倒装焊封装的失效模式,主要有焊点疲劳失效、填充胶分层开裂失效、电迁移失效、腐蚀失效、机械应力失效等。并分析了陶瓷基板倒装焊温度循环试验后的失效模式,陶瓷倒装焊封装失效的机理主要是倒装芯片焊点与UBM界面金属间化合物应力开裂失效。根据失效机理分析,进行陶瓷倒装焊工艺优化改进,试验达到了JESD22-A104C标准规定的温度循环:-65℃～+150℃、500次循环、3只样品无失效的要求。     

倒装焊SnPb焊点热循环失效和底充胶的影响

采用实验方法,确定了倒装焊SnPb焊点的热循环寿命．采用粘塑性和粘弹性材料模式描述了SnPb焊料和底充胶的力学行为,用有限元方法模拟了SnPb焊点在热循环条件下的应力应变过程．基于计算的塑性应变范围和实验的热循环寿命,确定了倒装焊SnPb焊点热循环失效Coffin-Manson经验方程的材料参数．研究表明,有底充胶倒装焊SnPb焊点的塑性应变范围比无底充胶时明显减小,热循环寿命可提高约20倍,充胶后的焊点高度对可靠性的影响变得不明显．     

倒装焊结构的大规模集成电路焊点失效机理研究

在倒装焊结构的球栅阵列（BGA）封装大规模集成电路（LSIC）的服役过程中,由于BGA焊球、基板材料和PCB材料的热膨胀系数不同,焊点失效成为倒装焊结构LSIC的主要失效模式。焊点失效与焊料性质、焊接时间和温度、制造中的缺陷等密切相关。结合焊点失效的常见形貌及实例,研究倒装焊结构的LSIC的焊点失效模式及失效机理。针对可能引发失效的因素,提出从工艺到应用的一系列预防措施,对提升该类型电路的可靠性具有指导意义。     

倒装焊结构对太赫兹对数周期天线的影响（英文）

设计了一种倒装焊结构,用于340 GHz的肖特基二极管探测器.探测单元是基于砷化镓(GaA s)工艺设计的.薄膜陶瓷支撑层旨在为太赫兹检测单元提供封装.通常,导电胶用作天线和输出电路之间的附接.分别对倒装焊结构和无倒装焊结构(类引线键合结构)模型对太赫兹接收天线性能的影响进行研究.为了比较的目的,使用相同的测试系统表征FC结构模型和无FC结构模型(引线键合结构).通过引线键合与倒装焊测试增益的结果比较,表明倒装焊结构可以作为大规模太赫兹检测阵列封装的低成本解决方案.     

RFID芯片超声倒装封装技术研究

超声倒装是近年来芯片封装领域中快速发展的一种倒装技术,具有连接强度高、接触电阻低、可靠性高、低温下短时完成和成本低的优势,特别适合较少凸点的RFID芯片封装。在镀Ni/Au铜基板上进行了RFID芯片超声倒装焊接实验,金凸点与镀Ni/Au铜基板之间实现了冶金结合,获得了良好的力学与电气性能,满足射频要求。     

Microwave preheating of anisotropic conductive adhesive films for high-speed flip chip on flex bonding

Anisotropic conductive adhesive film (ACF) can be preheated by microwave (MW) radiation in order to reduce the bonding time for flip-chip technology. Due to sluggish and nonuniform curing kinetics at the beginning of the curing reaction, thermal curing of epoxy is more time consuming. Therefore, MW radiation may be more effective, due to its uniform heating rate during the cycle. In this paper, MW preheating (for 1–4 sec) of ACF prior to final bonding has been applied to determine the electrical and mechanical performance of the bond. Powers of 80 and 240 W MW were used to study the effect of the MW preheating. A final bonding time of 6–7 sec can be used for flip chip on flex bonding instead of 10–15 sec (standard time for flip chip bonding) for MW preheating time and power used in this study. The contact resistance (as low as 0.01) is low in these samples, whereas the standard resistance is 0.017 ohm (bonded at 180°C for 10 sec without prior MW preheating). The shear forces at breakage were satisfactory (0.167–0.183 KN) for the samples bonded for 6–7 sec with MW preheating. This is very close and even higher than the standard sample (0.173 KN). For MW preheating power of 80 W and sweeping time of 2 sec, final bonding at 6 sec can also be used because of its low contact resistance (0.019 ohm). Scanning electron microscope (SEM) investigation of microjoints and fracture surface shows uneven distribution of conductive particles and thick bond lines in samples bonded for 5 sec (with MW preheating). Samples treated with MW radiation (80 W and 2–3 sec time) serve as evidence that well-distributed particles along with thin bond lines cause low contact resistance and high joint strength.     

芯片封装互连新工艺热超声倒装焊的发展现状

介绍了一种芯片封装互连新工艺热超声倒装芯片连接工艺.在比较当前多种芯片封装方式的基础上,总结了这一工艺的特点及优越性,并详细论述了当前这一工艺的技术进展与理论研究状况,指出该工艺是芯片封装领域中具有发展潜力的新工艺.     

Characterization of flip chip bonded structure with Cu ABL power bumps

Power distribution in both 2D and 3D integrated circuit (IC) devices becomes one of the key challenges in device scaling, because the on-chip power dissipation becomes significantly severe and causes thermal reliability issues. In this study, the process solution to resolve the on-chip power dissipation by improving power distribution was investigated through newly designed power bumps called ABL (advanced bump layer) bumps. Rectangular-shaped Cu ABL bumps were fabricated and bonded on Si substrate using flip chip bonding process. The bump height difference in signal and ABL power bumps, bonding interface, and electrical resistivity of flip chip bonded structure were evaluated. The lowest electrical resistivity of Cu ABL bump system was estimated to be 3.3E−8 Ω m. The process feasibility of flip chip bonded structure with Cu ABL bumps has been demonstrated.     

倒装焊接在压力敏感芯片封装工艺中的研究

胶粘引丝无法实现硅压力敏感芯片的小型化封装,无引线封装可以解决该问题。倒装焊接具有高密度、无引线和可靠的优点,通过对传统倒装焊接工艺进行适当的更改,倒装焊接可应用于压力敏感芯片的小型化封装。采用静电封接工艺在普通硅压力敏感芯片上制作保护支撑硅基片,在硅压力敏感芯片的焊盘上制作金凸点,调整倒装焊接的工艺顺序和工艺参数,实现了绝压型硅压力敏感芯片的无引线封装,为压力传感器小型化开辟了一条新路。试验结果表明该封装方式可靠性高,寿命长,具有耐恶劣环境的特点。     

The application of flip-chip bonding interconnection technique on the module assembly of 10 Gbps laser diode

Flip chip bonding technique using Pb/In solder bumps was applied to packaging of a 10 Gbps laser diode (LD) submodule for high speed optical communication systems. The effect of the flip-chip bonding interconnection technique instead of conventional wire bonding was investigated for high speed broad band devices. The broad band performance of 10 Gbps LD submodule was simulated using SPICE S/W and compared with experimental results. In this simulation, the 10 Gbps LD was modeled in a parallel RC circuit. The values of R and C used for the equivalent circuit were 5ω and 1 pF, respectively. The LD was placed in series with a 18ω thin film resistor to prevent the impedance mismatch between the LD and a 25ω transmission line. The dependence of parasitic parameters on the small signal modulation bandwidth and the scattering parameters of the LD submodule was investigated and analyzed up to 20 GHz. A small signal modulation bandwidth of 14 GHz at 10 mA dc bias current and the clean modulation response up to 20 GHz were found for the flip-chip bonded submodule. The bandwidth of flip-chip bonded 10 Gbps LD submodule is wider than that of the wire-bonded LD submodule by a difference of 3.8 GHz.     

热超声倒装焊在制作大功率GaN基LED中的应用

设计了适合于倒装的大功率GaN基LED芯片结构,在倒装基板硅片上制作了金凸点,采用热超声倒装焊接(FCB)技术将芯片倒装在基板上.测试结果表明获得的大面积金凸点连接的剪切力最高达53.93 g/bump,焊接后的GaN基绿光LED在350 mA工作电流下正向电压为3.0 V.将热超声倒装焊接技术用于制作大功率GaN基LED器件,能起到良好的机械互连和电气互连.     

倒装焊器件封装结构设计

倒装焊是今后高集成度半导体的主要发展方向之一。倒装焊器件封装结构主要由外壳、芯片、引脚(焊球、焊柱、针)、盖板(气密性封装)或散热片(非气密性封装)等组成。文章分别介绍外壳材料、倒装焊区、频率、气密性、功率等方面对倒装焊封装结构的影响。低温共烧陶瓷(LTCC)适合于高频、大面积的倒装焊芯片。大功率倒装焊散热结构主要跟功率、导热界面材料、散热材料及气密性等有关系。倒装焊器件气密性封装主要有平行缝焊或低温合金熔封工艺。     

Increasing the bonding strength of chips on flex substrates using thermosonic flip-chip bonding process with nonconductive paste

Thermosonic flip-chip bonding process with a nonconductive paste (NCP) was employed to improve the processability and bonding strength of the flip-chip onto flex substrates (FCOF). A non-conductive paste was deposited on the surface of the copper electrodes over the flex substrate, and a chip with eight gold bumps bonded onto the copper electrodes by the thermosonic flip-chip bonding process.For the chips and flex substrates assembly, ultrasonic power is important in the removal of some of the non-conductive paste on the surface of copper electrodes during thermosonic bonding. Accordingly, gold stud bumps in this study were directly bonded onto copper electrodes to form successful electrical paths between chips and the flex substrate. A particular ultrasonic power resulted in some metallurgical bonding between the gold bumps and the copper electrodes, increasing the bonding strength. The ultrasonic power was not only to remove the NCP from the copper electrodes, but also formed metallurgical bonds during the thermosonic flip-chip bonding process with NCP.In this study, the parameters of the bonding of chips onto flex substrates using thermosonic flip-chip bonding process with NCP were a bonding force of 4.9 N, a curing time of 40 s, a curing temperature of 140 °C and an ultrasonic power of 14.46 W. The processability and bonding strength of flip-chips on flex substrates using thermosonic bonding process with NCP was verified in this study. This process has great potential to be applied to the packaging of consumed electronic products.     

Flux-free direct chip attachment of solder-bump flip chip by Ar + H2 plasma treatment

The flux-free flip-chip bonding process using plasma treatment was investigated. The effect of plasma-process parameters on Sn oxide-etching characteristics was evaluated by Auger depth-profile analysis. The die-shear test was performed to evaluate the adhesion strength of an Sn-37mass%Pb and Sn-3.5mass%Ag solder-bump flip chip that was bonded after plasma treatment. The Ar + H₂ plasma treatment reduced the thickness of the oxide layer on the Sn surface. The addition of H₂ to the Ar plasma improved the oxide-etching characteristics. A low chamber pressure was more effective in oxide etching. The die-shear strength of the plasma-treated Sn-Pb and Sn-Ag solder flip chip was higher than that of the nontreated chip but lower than that of the fluxed chip. The difference in the die-shear strength between the plasma-treated specimen and the nontreated specimen increased with increasing bonding temperature. The plasma-treated flip chip fractured at the solder/top-surface metallurgy (TSM) interface at low bonding temperature, but at the solder/under-bump metallurgy (UBM) interface at high bonding temperature.