A 1.8 V CMOS fourth-order Gm-C bandpass sigma-delta modulator dedicated to front-end ultrasonic receivers

A 4th order bandpass sigma-delta modulator for ultrasound applications is presented. By cascading two second-order identical Gm-C bandpass filters, a 4th-order modulator was designed with high power-efficiency, stability, tunability and programmability. The modulator is dedicated for application with intermediate frequency of 3 MHz and bandwidth of 200 kHz. Implemented in a standard 0.18 μm CMOS technology, the post-layout simulation of the modulator gives a dynamic range of 78 dB. Chip measurements are reported after successfully tuning the modulator to operate at four-time of its folded specifications. The final SNR achieves 58 dB at 0.75 MHz with 50 kHz bandwidth. The modulator consumes 2.5 mW from 1.8 V power supply. Moreover, a programming method is introduced and corresponding circuit is designed to change the central frequency of the modulator between 3 and 20 MHz for scanning different regions of the body. However the 200 kHz bandwidth limits the modulator only for Dobbler mode applications, the effective facilities of programmability are valuable property to expand this application to other wide band applications in future. Lisheng Qin received the B.Sc. degree in electrical engineering from Tianjin University, China in 1992. He was with Polystim Neurotechnologies Laboratory from 2001 to 2005 and received the M.Sc. degree in electronics engineering from Ecole Polytechnique de Montreal, Canada in 2005. He is now with Apexone Microelectronics Inc. as Analog/Mixed-Signal Design Engineer. Kamal El-Sankary received the B.Sc. degree in electrical engineering from the Lebanese University, Lebanon in 1997 and the M.Sc. degree in electronics engineering from University of Quebec in Trois Rivieres, Canada, in 2001. He is currently pursuing the Ph.D. degree in microelectronics at Ecole Polytechnique de Montreal, Canada. His research interests include analog/mixed-signal circuits design and signal processing. Mohamad Sawan received the B.Sc. degree in electrical engineering from Université Laval, Canada in 1984, the M.Sc. and Ph.D. degrees, both in electrical engineering, from Université de Sherbrooke, Canada, in 1986 and 1990 respectively, and postdoctorate training from McGill University, Canada in 1991. He joined Ecole Polytechnique de Montréal in 1991 where he is currently a Professor in Microelectronics. His scientific interests are the design and test of mixed-signal (analog, digital and RF) circuits and systems, the digital and analog signal processing, the modeling, design, integration, assembly and validation of advanced wirelessly powered and controlled monitoring and measurement techniques. These topics are oriented toward the biomedical implantable devices and telecommunications applications. Dr. Sawan is a holder of a Canadian Research Chair in Smart Medical Devices. He is leading the Microelectronics Strategic Alliance of Quebec (Regroupement stratégique en microélectronique du Québec - ReSMiQ). He is founder of the Eastern Canadian IEEE-Solid State Circuits Society Chapter, the International IEEE-NEWCAS conference, and Polystim neurotechnologies laboratory at the Ecole Polytechnique de Montreal. He is cofounder of the International Functional Electrical Stimulation Society (IFESS), and the IEEE International conference on Electronics, Circuits and Systems (ICECS). Dr. Sawan is involved in the committees of many national and international conferences and other scientific events. He published more than 300 papers in peer reviewed journals and conference proceedings and is awarded 6 patents. He is editor of the Springer Mixed-signal Letters, Distinguished Lecturer for the IEEE CAS Society, President of the biomedical circuits and systems (BioCAS) technical committee of the IEEE CAS Society, and he is representative of IEEE-CAS in the International Biotechnology council. He received the Barbara Turnbull 2003 award for spinal cord research, the Medal of Merit from Lebanon, and the Bombardier Medal from the French Association for the advancement of sciences. Dr. Sawan is Fellow of the Canadian Academy of Engineering, and Fellow of the IEEE.     

A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices

This paper extends the timing test model in [5] to be more realistic by including the effects of the test fixtures between a device under test and a tester. The paper enables analyzing the trade-offs that arise between the predicted yield and the required overall test environment timing accuracy (OTETA) which involves the tester overall timing accuracy (OTA) and the test fixtures' impacts. We specifically focus on the application of the extended model to predict the test yield of standard high-speed interconnects, such as PCI Express, Parallel/Serial RapidIO, and HyperTransport. The extended model reveals that achieving an actual yield of 80% with a test escape of 300 DPM (Defects Per Million) requires an equivalent OTETA that is about half the acceptable absolute limit of the tested parameter. Baosheng Wang received his B.S. degree from Beijing University of Aeronautics and Astronautics (BUAA), Beijing, P.R. China, in 1997 and M.S. degree from Precision Instrument & Mechanical Engineering from the Tsinghua University, Beijing, P. R. China in 2000. In 2005, he received his Ph.D. degree in Electrical Engineering from the University of British Columbia (UBC), Vancouver, BC, Canada. During his Master study, he was doing MEMS, Micro Sensors and Digital Signal processing. From 2000 to 2001, he worked in Beijing Gaohong Telecommunications Company as a hardware engineer in ATM technology. Currently, he is a Design-for-Test (DFT) engineer at ATI Technologies Inc., Markham, Ontario, Canada. He publishes widely at international conferences and journals. His primary research interests are time-driven or timing-oriented testing methodologies for System on-a-Chip (SoC). These fields include test time reduction for SRAMs, accelerated reliability test for non-volatile memories, yield analysis for SoC timing tests, SoC path delay timing characterization and embedded timing measurements. Andy Kuo is currently a Ph.D student of System on a Chip (SoC) Research Lab at the Department of Electrical and Computer Engineering, University of British Columbia. He received his M.A.Sc. and B.A.Sc in electrical and computer engineering from University of British Columbia and University of Toronto in 2004 and 2002 respectively. His research interests include high-speed signal integrity issues, jitter measurement, serial communications. Touraj Farahmand received the B.Sc. degree in Electrical Engineering from Esfahan University of Technology, Esfahan, Iran in 1989 and the M.Sc. in Control Engineering from Sharif university of Technology, Tehran, Iran in 1992. After graduation, he joined the Electrical and Computer Research center of Esfahan University of Technology where he was involved in the DSP algorithm development and design and implementation of the control and automation systems. Since October 2001, he has been working in the area of high-speed signal timing measurement at SoC (System-on-a-Chip) lab of UBC (University of British Columbia) as a research engineer. His research interests are signal processing, jitter measurement, serial communication and control. André Ivanov is Professor in the Department of Electrical and Computer Engineering, at the University of British Columbia. Prior to joining UBC in 1989, he received his B.Eng. (Hon.), M. Eng., and Ph.D. degrees in Electrical Engineering from McGill University. In 1995–96, he spent a sabbatical leave at PMC-Sierra, Vancouver, BC. He has held invited Professor positions at the University of Montpellier II, the University of Bordeaux I, and Edith Cowan University, in Perth, Australia. His primary research interests lie in the area of integrated circuit testing, design for testability and built-in self-test, for digital, analog and mixed-signal circuits, and systems on a chip (SoCs). He has published widely in these areas and holds several patents in IC design and test. Besides testing, Ivanov has interests in the design and design methodologies of large and complex integrated circuits and SoCs. Dr. Ivanov has served and continues to serve on numerous national and international steering, program, and/or organization committees in various capacities. Recently, he was the Program Chair of the 2002 VLSI Test Symposium (VTS'02) and the General Chair for VTS'03 and VTS'04. In 2001, Ivanov co-founded Vector 12, a semiconductor IP company. He has published over 100 papers in conference and journals and holds 4 US patents. Ivanov serves on the Editorial Board of the IEEE Design and Test Magazine, and Kluwer's Journal of Electronic Testing: Theory and Applications. Ivanov is currently the Chair of the IEEE Computer Society's Test Technology Technical Council (TTTC). He is a Golden Core Member of the IEEE Computer Society, a Senior Member of the IEEE, a Fellow of the British Columbia Advanced Systems Institute and a Professional Engineer of British Columbia. Yong Cho received the B.S. degree from Kyung Pook National Unviersity, Korea, in 1981 and the M.S. degree from in electrical and computer engineering from the University of South Carolina, Columbia, S.C., in 1988 and the Ph.D. degree in electrical engineering and applied physics from Case Western Reserve University, Cleveland, OH, in 1992. He is currently a Professor with the Department of Electronics Engineering, Konkuk University, Seoul, Korea. His recent research interests include SoC Design and Verification, H/W and S/W co-design, and embedded programming on SoC. Sassan Tabatabaei received his PHD in Electrical Engineering from the University of British Columbia, Vancouver, Canada in 2000. Since then, he has held several senior technical positions at Vector12 Corp, Guide Technology, and Virage Logic. His professional and research interests include mixed-signal design and test, and signal integrity and jitter test methodologies for high-speed circuits and multi-Gbps serial interfaces. He has published several papers and holds a US patent in the area of timing and jitter measurement. Currently, he holds the position of the director for embedded test at Virage Logic Corporation.     

Implementation of a chaotic oscillator by designing Chua’s diode with CMOS CFOAs

The implementation of a chaotic oscillator which is based on Chua’s circuit, is presented. Chua’s diode is realized by using current feedback operational amplifiers (CFOAs). Furthermore, it is shown that a CMOS compatible CFOA can be designed by connecting two voltage followers sandwiched between two current mirrors. The proposed implementation is biased at ±1.2 V, and simulated by using SPICE and standard CMOS technology of 0.35 μm. Finally, simulation results are presented to show the sequence of chaotic behaviours for increasing values of the linear resistance. Esteban Tlelo-Cuautle received the B.Sc. degree in electronics engineering from the Technologic Institute of Puebla (ITP) México, in 1993, the M.Sc. and Ph.D. degrees from the National Institute for Astrophysics, Optics and Electronics (INAOE) México, in 1995 and 2000, respectively. In 1995 he joined the Department of Electronics at the ITP. Since 2001 he has been with the Department of Electronics at INAOE, where he is currently a Researcher. He has been member of reviewer-committees for the IEEE Trans. on CAS-I, IEEE Trans. on Education, IEEE Latin-America, Información Tecnológica, SCI Journal, IASTED, and IEEE ISCAS. He is member of IEICE, Senior Member of the IEEE, and his research interest include electronic design automation, modeling and simulation, symbolic analysis, circuit synthesis, and analog and mixed-signal CAD tools. Aarón Gaona-Hernández was born in Puebla, México in 1980. He received his B.Sc. degree from the Faculty of Sciences for Electronics at the Autonomous University of Puebla (BUAP-FCE), in 2005. His research interest include analog IC design and chaotic systems. Joel García-Delgado is with the BUAP-FCE México.     

A new CMOS multimode digital pixel sensor dedicated to an implantable visual cortical stimulator

We describe in this paper a new CMOS multimode image pixel sensor (MIPS) dedicated to an implantable visual cortical stimulator. Each 16 μm × 16 μm pixel area contains a photodiode, with a fill factor of 22%, a comparator used to convert the pixel level from analog to digital (A/D) values and an 8-bit DRAM, resulting in a total of 44 transistors per pixel. The A/D conversions use one common digital to analog converter to deliver the voltage reference needed to determine the pixel voltage. Three selectable operation modes are combined in the proposed MIPS: A high dynamic range logarithmic mode, a linear integration mode, and a novel differential mode between two consecutive images. This last mode that allows 3D information is required for a visual cortical stimulator. A test chip has been fabricated in CMOS 0.18 μm technology and tested to validate the full operation of the different proposed modes. Mohamad Sawan received the B.Sc. degree in electrical engineering from Université Laval, Canada in 1984, the M.Sc. and Ph.D. degrees, both in electrical engineering, from Université de Sherbrooke, Canada, in 1986 and 1990 respectively, and postdoctorate training from McGill University, Canada in 1991. He joined Ecole Polytechnique de Montréal in 1991 where he is currently a Professor in Microelectronics. His scientific interests are the design and test of mixed-signal (analog, digital and RF) circuits and systems, the digital and analog signal processing, the modeling, design, integration, assembly and validation of advanced wirelessly powered and controlled monitoring and measurement techniques. These topics are oriented toward the biomedical implantable devices and telecommunications applications. Dr. Sawan is a holder of a Canadian Research Chair in Smart Medical Devices. He is leading the Microelectronics Strategic Alliance of Quebec (Regroupement stratégique en microélectronique du Québec – ReSMiQ). He is founder of the Eastern Canadian IEEE-Solid State Circuits Society Chapter, the International IEEE-NEWCAS conference, and Polystim neurotechnologies laboratory at the Ecole Polytechnique de Montreal. He is cofounder of the International Functional Electrical Stimulation Society (IFESS), and the IEEE International Conference on Electronics, Circuits and Systems (ICECS). Dr. Sawan is involved in the committees of many national and international conferences and other scientific events. He published more than 350 papers in peer reviewed journals and conference proceedings and is awarded 6 patents. He is editor of the Springer Mixed-signal Letters, Distinguished Lecturer for the IEEE CAS Society, President of the biomedical circuits and systems (BioCAS) technical committee of the IEEE CAS Society, and he is representative of IEEE-CAS in the International Biotechnology council. He received the Barbara Turnbull 2003 award for spinal cord research, the Medal of Merit from Lebanon, and the Bombardier Medal from the French Association for the advancement of sciences. Dr. Sawan is Fellow of the Canadian Academy of Engineering, and Fellow of the IEEE. Annie Trépanier received her Bachelor of Engineering Degree in Electrical Engineering in 2002 and her Master of Applied Sciences Degree in Microelectronics in 2005 from the Ecole Polytechnique de Montreal as a member of the Cortivision team in the Polystim Neurotechnologies Laboratory. She held a summer job at Nortel Networks and trained at Mindready. She is currently employed at Matrox, Montreal. Jean-Luc Trépanier received his Bachelor of Engineering Degree in Electrical Engineering in 2000 and his Master of Applied Sciences Degree in Microelectronics in 2003 from the Ecole Polytechnique de Montreal where he was a member of the Cortivision team in the Polystim Neurotechnologies Laboratory. He started his first company, Olyxia inc., where he developed the soon to be released Cute Spider VoIP Network. He is also the founder and CEO of Nexyrius inc. which develops a new generation of embedded systems. Yves Audet received his M.Sc. degree from a joint program between the University of Sherbrooke, QC, Canada and Université Joseph Fourier in Grenoble, France. He completed his Ph.D. at Simon Fraser University, BC, Canada. He has been working for three years in Research and Development with Mitel Corporation before being hired as assistant professor at école Polytechnique of Montreal, QC, Canada, in 2001. His research interests are CMOS sensor arrays and mixed signal circuits. Roula Ghannoum received her Bachelor of Engineering Degree in Computer and Communications Engineering from the Lebanese American University, Byblos—Lebanon, in July 2005. She is currently pursuing her Master of Applied Sciences in Microelectronics at the Ecole Polytechnique de Montreal as a member of the Cortivision team in the Polystim Neurotechnologies Laboratory working on image sensors as part of a global project that aims at restoring sight to the visually incapacitated.     

An Integrated Power Recovery Module Dedicated to Implantable Electronic Devices

This paper concerns the design and implementation of an inductively coupled RF telemetry for both power and data transferring to implantable microelectronic devices. The major shortcomings of available inductive powering designs are their low power-transfer efficiency and large size of the implantable unit. Therefore, there is a need to fully integrate interfacing module of the implantable unit. The presented power recovery module is dedicated to the biotelemetry application of cortical/nerve stimulation. The proposed strategy allows providing dual regulated output voltages 3.3 V/1.8 V to the electrodes driver and other implantable circuitry, respectively. Its low dropout voltage makes high power efficiency attainable. Fabricated integrated prototype in a CMOS 0.18 m technology has demonstrated its feasibility, providing a load current driving ability of 5 mA for each one of the two supply voltages.Yamu Hu received the B.S. degree in electrical engineering from Huazhong University of Science & Technology (HUST), Wuhan, P. R. China, in 1993, and the M.S. degree in electronics engineering from Ecole Polytechnique of Montreal, Canada, in 2000. He is currently working toward the Ph.D degree in electronics engineering at the same university. His research interest includes low-noise, low-power Analog/Mixed-Signal ICs for biomedical applications, RF front-end for wireless communications.Mohamad Sawan received the B.Sc. degree in electrical engineering from Université Laval, Canada in 1984, the M.Sc. and Ph.D. degrees, both in electrical engineering, from Université de Sherbrooke, Canada, in 1986 and 1990 respectively, and postdoctorate training from McGill University, Canada in 1991. He joined Ecole Polytechnique de Montréal in 1991 where he is currently a Professor in Microelectronics.His scientific interests are the design and test of mixed-signal (analog, digital and RF) circuits and systems, the digital and analog signal processing, the modeling, design, integration, assembly and validation of advanced wirelessly powered and controlled monitoring and measurement techniques. These topics are oriented toward the biomedical implantable devices and telecommunications applications. Dr. Sawan is a holder of a Canadian Research Chair in Smart Medical Devices. He is leading the ReSMiQ (Microelectronics Strategic Alliance of Quebec) research center. He is founder of the Eastern Canadian IEEE-Solid State Circuits Society Chapter and the IEEE-Northeastern workshop on Circuits and Systems (NewCAS). Also, he is cofounder of the International Functional Electrical Stimulation Society, and founder of PolySTIM neurotechnology laboratory at the Ecole Polytechnique de Montreal.He published more than 250 papers in peer reviewed journals and conference proceedings and was awarded 6 patents. He is editor of the Springer Mixed-signal Letters, Distinguished Lecturer for the IEEE CAS Society. He received the Barbara Turnbull 2003 award for spinal cord research. He is Fellow of the Canadian Academy of Engineering, and Fellow of the IEEE.Mourad El-Gamal received the B.Sc. degree with Honours from Ain-Shams University, Cairo, Egypt, in 1987, the M.Sc. degree from Vanderbilt University, Nashville, TN, in 1993, and the Ph.D. degree from McGill University, Montré al, Canada, in 1998, all in electrical engineering.He is currently an Associate Professor and William Dawson Scholar at McGill University. His research interests include integrated circuits and MEMS for communications applications, on which he has published many papers, and most recently contributed to a chapter on low voltage 5-GHz RFIC front-ends, published by the IEE in 2003. He has received several teaching awards and recognitions, and holds one patent. He was on leave of absence from McGill in 2002 to assume the role of Director of Engineering, then Vice President, of the Wireless Business Unit of MEMSCAP, headquartered in France—a 165 employee, publicly trading company specializing in MEMS. He oversaw all the business and technical aspects in different sites around the world related to RF-MEMS devices, RFICs, and millimeter-wave passive circuits. Earlier, he worked for the French telecommunications company ALCATEL and was a Member of the Technical Staff at IBM. He regularly serves as a consultant for leading microelectronics companies in North America and in Europe.Dr. El-Gamal is a member of the Analog Signal Processing Technical Committee of the IEEE Circuits and Systems (CAS) Society, and is a member of the Technical Committee of the Bipolar/BiCMOS Circuits and Technology Meeting (BCTM). He was a Guest Editor for the October 2004 issue of the Journal of Solid-State Circuits. He is the co-recipient of several research awards, the most recent being the 2003 Myril B. Reed Best Paper Award of the IEEE International Midwest Symposium on Circuits and Systems for work on frequency synthesizer covering the lower and upper bands of 5 GHz WLANs.     

Efficient synthesis methodology for optimal inverter-based transimpedance amplifiers

In this paper, we present a new synthesis methodology that facilitates the design automation of maximum bandwidth transimpedance amplifier (TIA) for optical communications under the constraint of a specific bit error rate. Our synthesis methodology is based on newly developed models that characterize the input referred noise and bandwidth. Our technique provides the optimal parameters of the transimpedance amplifier for maximizing the bandwidth. These optimal parameters are mapped to equivalent circuit parameters to achieve the optimal sizing of the TIA. Our methodology is characterized by its very fast design convergence as well as better results compared to conventional design techniques. We applied our synthesis methodology in designing a TIA for optical interconnect systems using the 0.25μm and 0.18μm CMOS technologies. Mohamed Elnozahi is a PhD student in the Rice Automated Nanoscale Design Group at the department of Electrical and Computer Engineering, Rice University. His research interests include the design and design automation of analog and mixed-signal circuits. Yehia Massoud received the B.Sc. and M.Sc. degrees (with honors) from Cairo University, Egypt. He received the PhD degree in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology, MIT, Cambridge, in 1999. He is the founding director of the Rice Automated Nanoscale Design Group at Rice University, where he is currently an Assistant Professor in the departments of Electrical and Computer Engineering and Computer Science at Rice University, Houston, Texas, USA. Before joining Rice University in 2003, he was a member of the Technical Staff at the Advanced Technology Group at Synopsys Inc., Mountain View, California, USA, from 1999 to 2003. His research interests include the modeling and design automation of mixedsignal integrated systems as well as alternatives for on-chip and chip-to-chip communication in future nanoscale systems. He is a recipient of the National Science Foundation CAREER Award for 2004.     

An RF CMOS Q-Enhanced LC Resonator

This paper investigates a Q-enhanced LC resonator implemented with a Q-enhancement circuit based on both active and reactive components. An analytical expression is presented for the Q-enhancement circuit and simulations are compared with measurements on a differential Q-enhanced LC tank operating at 1779–1870 MHz. Sensitive circuits and inaccurate models leads to inaccurate simulations. To improve the accuracy of simulations, S-parameter measurements of components and sub-circuits are included in the simulations whereby an accuracy of 3 MHz in the estimate of the resonator center frequency results. Per Madsenreceived his M.Sc.E.E degree in 1997 from Aalborg University, Denmark. In 2005 he received his Industrial PhD degree, also from Aalborg University. He is currently working with development of reference designs for GSM and UMTS at Texas Instruments Denmark A/S. Jan Hvolgaard Mikkelsenreceived his M.Sc.E.E. degree in 1995 from Aalborg University, Denmark. In 2005 he received his PhD degree, also from Aalborg University. He is currently employed as an Assistant Professor at Aalborg University where he is working as an IC design manager for the large scale RF IC design efforts at Aalborg University. His research interests include both RF and LF CMOS design as well as transceiver architectures. Jens Christian Lindofreceived his M.Sc.E.E. degree in electrical engineering in 1991 from Aalborg University, Denmark, in 1991. He is currently R&D Director at Texas Instruments Denmark A/S, where he is responsible for all HW and SW developed for Texas Instrument's cellular reference designs for GSM, GPRS, EDGE and UMTS. Torben Larsenreceived his M.Sc.E.E. degree in electrical engineering from Aalborg University, Denmark, in 1988, and the Dr. Techn. degree from Aalborg University in 1998. He has been employed as full Professor at Aalborg University since 2001. Dr. Larsen serves as reviewer for IEE, IEEE and Wiley. Areas of specialized research interests include noise theory, nonlinear analysis techniques, RF techniques, RF CMOS technology, and digital modulation techniques.     

Single DDCC Biquads with High Input Impedance and Minimum Number of Passive Elements

Two new configurations for the design of biquad filters with high input impedance are presented. The first configuration can synthesize low-pass and high-pass filter functions according to the passive components used. The second one can synthesize a band-pass filter function. The proposed configurations employ only one differential difference current conveyor (DDCC) as active elements and minimum number of passive elements, namely two resistors and two capacitors. Another filter topology based on DDCC is presented that allows modifying the quality factor without changing its natural frequency. All the filters enjoy low sensitivities. SPICE simulation results are given to confirm the validity of the analysis and to point out the high performance of the filters.Muhammed A. Ibrahim was born in Erbil, Iraq in 1969. He obtained his B.Sc. and M.Sc. degrees from Salahaddin University, Erbil, Iraq and Istanbul Technical University, Istanbul, Turkey in 1990 and 1999, respectively, all in electronics and communication engineering. Between 1992 and 1996 he worked as Research Assistant at Salahaddin University where he was later appointed as Assistant Lecturer in 1999. Since 2000 he has been studying for his Ph.D. degree in Electronics and Communication Engineering Program at Istanbul Technical University. His main research interests are CMOS circuit design, current-mode circuits and analog signal processing applications. He has more than 20 international journal and conference papers in scientific review.H. Hakan Kuntman received his B.Sc., M.Sc. and Ph.D. degrees from Istanbul Technical University in 1974, 1977 and 1982, respectively. In 1974 he joined the Electronics and Communication Engineering Department of Istanbul Technical University. Since 1993 he is a professor of electronics in the same department. His research interest include design of electronic circuits, modeling of electron devices and electronic systems, active filters, design of analog IC topologies. Dr. Kuntman has authored many publications on modelling and simulation of electron devices and electronic circuits for computer-aided design, analog VLSI design and active circuit design. He is the author or the coauthor of 76 journal papers published or accepted for publishing in international journals, 91 conference papers presented or accepted for presentation in international conferences, 99 turkish conference papers presented in national conferences and 10 books related to the above mentioned areas. Furthermore he advised and completed the work of 7 Ph.D. students and 31 M.Sc. students. Currently, he acts as the head of the Electronics and Communication Engineering Department in Istanbul Technical University. Dr. Kuntman is a member of the Chamber of Turkish Electrical Engineers (EMO).Oguzhan Cicekoglu received the B.Sc. and M.Sc. degrees from Bogazici University and the Ph.D. degree from Istanbul Technical University all in Electrical and Electronics Engineering in 1985, 1988 and 1996 respectively. He served as lecturer at the School of Advanced Vocational Studies Electronics Prog. of Bogazici University where he held various administrative positions between 1993 and 1999. He served also as part time lecturer at various institutions. He was with the Biomedical Engineering Institute of the Bogazici University between 1999 and 2001. He is currently Associate Professor at the Electrical and Electronics Engineering Department of the same University.His current research interests include analog circuits, active filters, analog signal processing applications and current-mode circuits. Oguzhan Cicekoglu is the author or co-author of 62 journal papers and about 90 international or local conference papers published or accepted for publishing in journals or conference proceedings.He served as the committee member in various scientific conferences and as reviewer in numerous journals including Analog Integrated Circuits and Signal Processing, IEEE CAS-I, IEEE CAS-II, International Journal of Electronics, Microelectronics Journal, Solid State Electronics and IEE Proceedings Pt.G.Oguzhan Cicekoglu is a member of the IEEE.     

A new pipelined analog-to-digital converter using current conveyors

A new pipelined analog-to-digital converter (ADC) using second-generation current conveyor (CCII) is presented. Two main building blocks of the pipelined ADC, sample-and-hold (S/H) circuit and multiplying digital-to-analog converter (MDAC) are constructed of CCII instead of operational amplifier (OA). Experimental results show that the proposed CCII-based pipelined ADC can work at 12.5 MHz with a 7.3-bit resolution. The DNL is within −0.4 LSB and 0.4 LSB and INL is within −0.8 LSB and 0.8 LSB, respectively. The pipelined ADC is realized in TSMC 0.35 μm CMOS technology and consumes 29 mW under a 3.3 V power supply. The core size is 0.85×0.85 mm². Sing-Yen Wu received the M.S. degree in the Department of Electronic Engineering from National Taipei University of Technology, Taipei, Taiwan, in 2005. His current research interests include CMOS pipelined analog-to-digital converters and mixed-signal integrated circuit. Lu-Po Liao received the M.S. degree in the Department of Electronic Engineering from National Taipei University of Technology, Taipei, Taiwan, in 2003. His current research interests include analog integrated circuit design and mixed-signal integrated circuit design. Chia-Chun Tsai received the Ph.D. degrees in Electrical Engineering from National Taiwan University, Taipei, Taiwan, 1991. From 1989 to 2005, he served at the Department of Electronic Engineering, National Taipei University of Technology, Taipei, Taiwan. Since 2005 he has been with the Department of Computer Science and Information Engineering, Nanhua University, Chiayi, Taiwan, where he is a Full Professor. His current research interests include VLSI design automation and mixed-signal IC designs.     

Baseband Digital Predistorter with Quadrature Error Correction

In this article simulation and measurement results of a FPGA implementation of a baseband digital complex gain predistorter with a quadrature modulator and demodulation error correction circuits are presented. Four different methods for finding the quadrature error correction values are compared and the effect of quadrature errors to predistortion is discussed. A 50 dB three stage power amplifier chain with an analog quadrature modulator and demodulator was used in the measurements as the device to be predistorted. The signal used in the measurements and simulations was a 30 dBm 18 kHz 16-QAM signal at 400 MHz carrier frequency. In the measurements 15 dB reduction in 3rd order nonlinearity was achieved. The usage of quadrature error correction reduced the adjacent channel power by 9 dB. Ilari Teikari was born in Tampere, Finland, in 1978. He received the M.Sc. (tech.) degree from Helsinki University of Technology (HUT), Helsinki, Finland, in 2002. He is currently working toward D.Sc. (tech) degree in the electronic circuit design laboratory, HUT. His current research intrests are in the area of power amplifier linearization methods and digital circuit design. Jouko Vankka was born in Helsinki, Finland, in 1965. He received the M.S. and Ph.D. degrees in electrical engineering from Helsinki University of Technology (HUT) in 1991 and 2000, respectively. Since 1995, he has been with the Electronic Circuit Design Laboratory, HUT. His research interests include VLSI architectures and mixed-signal integrated circuits for communication applications. Kari A. I. Halonen was born in Helsinki, Finland, on May 23, 1958. He received the M.Sc. degree in electrical engineering from Helsinki University of Technology, Finland, in 1982, and the Ph.D. degree in electrical engineering from the Katholieke Universiteit Leuven, in Heverlee, Belgium, in 1987. From 1982 to 1984 he was employed as assistant at Helsinki University of Technology and as research assistant at the Technical Research Center of Finland. From 1984 to 1987 he was a research assistant at the E.S.A.T. Laboratory of the Katholieke Universiteit Leuven, enjoying also a temporary grant of the Academy of Finland. Since 1988 he has been with the Electronic Circuit Design Laboratory, Helsinki University of Technology, as senior assistant (1988–1990), and the director of the Integrated Circuit Design Unit of the Microelectronics Center (1990–1993). He was on leave of absence the academic year 1992–1993, acting as R&D manager in Fincitec Inc., Finland. From 1993 to 1996 he has been an associate professor, and since 1997 a full professor at the Faculty of Electrical Engineering and Telecommunications, Helsinki University of Technology. He became the Head of Electronic Circuit Design Laboratory year 1998. From 1997 to 1999 he was an associate editor of IEEE Transactions on Circuits and Systems I. He has been a guest editor for IEEE Journal of Solid-State Circuits and the Technical Program Committee Chairman for European Solid-State Circuits Conference year 2000. He has been awarded the Beatrice Winner Award in ISSCC'02 Conference year 2002. He specializes in CMOS and BiCMOS analog integrated circuits, particularly for telecommunication applications. He is author or co-author over a hundred and fifty international and national conference and journal publications on analog integrated circuits. He has several patents on analog integrated circuits.     

A low-cost programmable clock generator for switched-capacitor circuit applications

This paper presents two improved circuit techniques that allow the design of a low-cost programmable clock generator using a ring oscillator for low-frequency switched-capacitor applications. The first technique aims at reducing the frequency of the oscillator with small capacitors by proposing a Miller current-starved inverter ring oscillator. For identical values of integrated components in implementation, the proposed ring oscillator reduces the oscillation frequency by 5 times over the conventional ring oscillator and 3 times over the conventional current-starved inverter ring oscillator. This benefits the relaxation of PSRR requirement and the reduction of substrate noise coupling in mixed-signal circuits. The second technique aims at enhancing the reliability of the programmed data by proposing orthogonal fusible link trimming circuit. The experimental results have verified that the programming range of 56 kHz to 1.042 MHz is achieved using discrete-step tuning on small capacitor values from 0.375 pF to 5.625 pF together with frequency division by four divider stages, whilst the jitter is less than 300 ps at ±10% variation in a 5 V supply in the entire tuning range. Wing Foon Lee was born in Singapore. He had worked as an application engineer for more than two years. He received his B.Eng., M.Eng. and Ph.D. degrees in Electrical & Electronic Engineering from Nanyang Technological University, Singapore in 1996, 1999 and 2005 respectively. His research interest is on low power analog circuit design, high precision readout circuits and signal-conditioning circuits for sensor applications. P. K. Chan was born in Hong Kong. He received the B.Sc. (Hons) degree from the University of Essex, Colchester, U.K., in 1987, the M.Sc. degree from the University of Manchester, Institute of Science and Technology (U.M.I.S.T.), Manchester, U.K., in 1988, and the PhD degree from the University of Plymouth, U.K. in 1992. From 1989 to 1992, he was a Research Assistant with the University of Plymouth, working in the area of MOS continuous-time filters. In 1993, he joined the Institute of Microelectronics (IME) as a Member Technical Staff, where he designed CMOS sensor interfaces for industrial applications. In 1996, He was a Staff Engineer with Motorola, Singapore where he developed the magnetic write channel for Motorola 1st generation hard-disk preamplifier. He joined Nanyang Technological University (NTU), Singapore in 1997, where he is currently an Associate Professor in the School of Electrical and Electronic Engineering and Program Director [analog/mixed-signal IC and applications] for the Center for Integrated Circuits and Systems (CICS). He holds four patents and is an IC Design Consultant to local and multi-national companies in Singapore. He has also conducted numerous IC design short courses to the industrial companies and design centers. His research interests include circuit theory, amplifier frequency compensation techniques, sensing interfaces for integrated sensors, biomedical circuits and systems, integrated filters and data converters.     

Explaining and eliminating latchup in a classical Wien oscillator via nonlinear design

A classical Wien-type sinusoidal oscillator is analyzed to explain the origin of its latchup behavior. Only when a correct nonlinear model of the oscillator is derived and the stability of all equilibrium points associated with each region of operation of the fundamentally nonlinear amplifier characteristics is studied can this phenomena be predicted. It is further shown how latchup can be eliminated. Ahmed S. Elwakil was born in Cairo, Egypt. He received his B.Sc. and M.Sc. degrees from Cairo University and his Ph.D. from the National University of Ireland, all in Electrical and Electronic Engineering. His main research interests are in the area of analog electronic circuit design with particular emphasis on nonlinear circuit analysis and design techniques, nonlinear dynamics and chaos theory. He is author and co-author of more than 70 publications in these areas. Dr. Elwakil is a senior member of IEEE, a member of the IEEE technical committee on nonlinear circuits and systems, a member of IEE, an associate member at the centre for chaos control at the City University of Hong Kong and an associate member at the International centre for Theoretical Physics. He has held several academic visiting positions and has acted as an instructor for two courses on VLSI organized by the United Nations University. He has served as a scientific committee member for many conferences and as a reviewer for numerous journals and conferences. Dr. Elwakil received the Government of Egypt first class medal for achievement in engineering sciences in 2003.     

Cell-Site Diversity Against Co-Channel Interference in LMDS Networks

LMDS networks are fixed radio systems providing advanced telecommunication services to a variety of users. Millimeter wave frequencies above 20 GHz have been allocated to LMDS systems by ITU-R and CEPT. The design of LMDS systems must take into account how interference affects performance considering the dominant propagation impairments in these frequencies. In the present paper, cell-site diversity, an effective fade mitigation countermeasure for LMDS systems, is considered for the reduction of intersystem interference on downstream LMDS channels. The intersystem cochannel interference may originate from adjacent LMDS networks or from point-to-point links operating at the same frequencies. A physical propagation model for the calculation of carrier-to-interference ratio diversity gain for the downstream channel is presented. Numerical results focus on the impact of frequency of operation, the subscriber's service availability and the climatic conditions on the interference analysis of LMDS networks either using or not cell site diversity. Athanasios D. Panagopoulos was born in Athens, Greece on January 26, 1975. He received the Diploma Degree in Electrical and Computer Engineering (summa cum laude) and the Dr. Engineering Degree from National Technical University of Athens (NTUA) in July 1997 and inAprilxcan l 2002. From May 2002 to July 2003, he had served the Technical Corps of Hellenic Army. In September 2003, he joined School of Pedagogical and Technological Education, as Assistant Professor. He is also Research Assistant in the Wireless & Satellite Communications Group of NTUA. He has published more than eighty papers in international journals and conference proceedings. He is the recipient of URSI General AssemblyYoung ScientistAward in 2002 and 2005 respectively. His research interests include radio communication systems design, wireless and satellite communications networks and the propagation effects on multiple access systems and on communication protocols. He is member of IEEE and member of Technical Chamber of Greece. Konstantinos P. Liolis was born in Athens, Greece in 1981. He received the Diploma degree in electrical and computer engineering from the National Technical University of Athens (NTUA) and the M.Sc. degree in electrical engineering from the University of California, San Diego (UCSD) in July 2004 and December 2005, respectively. He is currently working towards his Ph.D. degree in electrical engineering at NTUA. From September 2004 to December 2005, he was research assistant in the California Institute for Telecommunications and Information Technology (Cal-IT2) within UCSD. Since June 2006, he has been with the European Space Agency Research and Technology Centre (ESA/ESTEC), Noordwijk, The Netherlands. His research interests are in the areas of multiple antenna (MIMO) and multicarrier (OFDM) transmission techniques and their application to broadband fixed wireless access and satellite communication networks. He is student member of the IEEE and member of the Technical Chamber of Greece (TEE). He received the 3rd Best Student Paper Award in the 2006 IEEE Radio and Wireless Symposium. Panayotis G. Cottis was born in Thessaloniki, Greece, in 1956. He received the Dipl. (mechanical and electrical engineering) and Dr.Eng. degrees from the National Technical University of Athens (NTUA), Greece, in 1979 and 1984, respectively, and the M.Sc. degree from the University of Manchester, (UMIST), Manchester, U.K., in 1980. In 1986, he joined the Department of Electrical and Computer Engineering, National Technical University of Athens (NTUA), Greece, where he is currently a Professor. He has published more than seventy papers in international journals and transactions. His research interests include microwave theory and applications, wave propagation in anisotropic media, electromagnetic scattering, wireless and satellite communications. Since September 2003, he is the Vice Rector of NTUA.     

A New Efficient Block-Matching Algorithm for Motion Estimation

This paper presents a new full-search block-matching algorithm: Multi-stage Interval-based Motion Estimation algorithm (MIME). The proposed algorithm is a block based motion estimation algorithm that utilizes successive elimination technique. We define two approximate functions, as the upper and lower boundaries of the interval that includes the Conventional distortion metric SAD. Each stage in the proposed algorithm; except for the last stage; incorporates low resolution pixels for the boundary functions calculations. The final stage is a full resolution block matching stage. MIME has a high probability of finding the optimal motion vector at any stage of the algorithm. The proposed algorithm reduces the computational complexity by successively eliminating non-candidate blocks from the search window at each stage. This computational reduction leads to enhanced performance in terms of low power consumption and fast motion vector estimation. A low power VLSI implementation of the algorithm is also presented in this paper. Simulation results on benchmark video sequences shows that MIME algorithm eliminates almost 88% of the candidate blocks after only two interval based stages. Hanan Ahmed Hosny Mahmoud obtained the B.Sc. of Computer Science from Faculty of Engineering, University of Alexandria in 1986. She obtained her M.Sc. in Computer Science from Faculty of Engineering, University of Alexandria in 1991. She obtained the M.Sc. in Computer Engineering from University of Louisiana at Lafayette in 1999 and the Ph.D. in Computer Engineering from University of Louisiana at Lafayette in 2001. Currently, she is working as an Assistant Professor in the Faculty of Engineering, University of Alexandria. Sumeer Goel received the B. Tech degree in electronics and communications engineering from Punjab Technical University, Punjab, India, in 2001. He received the M.S. degree in computer engineering from University of Louisiana at Lafayette, Lafayette, LA, in 2003 where he is continuing his education towards Ph.D. degree in computer engineering. His research interests are low-power and high noise tolerance VLSI circuit and architecture design for digital signal processing applications. Mohsen Shaaban received his B.S. degree in electrical engineering and communications from the University of Alexandria, Egypt, in 1998. In 2001, he joined the University of Louisiana at Lafayette (ULL) as a teaching and research assistant at the Center For Advanced Computer Studies (CACS), the VLSI Research Lab. He received his M.S. degree in the field computer engineering from ULL in 2003. Currently, he is pursing his Ph.D. degree in the same field. His research interests include Digital VLSI circuit design, CAD tools and Video processing applications. Magdy A. Bayoumi received the B.Sc. and M.Sc. degrees in electrical engineering from Cairo University, Cairo, Egypt, in 1973 and 1977, the M.Sc. degree in computer engineering from Washington University in St. Louis, MO, in 1981, and the Ph.D. degree in electrical engineering from the University of Windsor, Windsor, ON, Canada, in 1984. Currently, he is the Director of the Center for Advanced Computer Studies (CACS), Department Head of the Computer Science Department, the Edmiston Professor of Computer Engineering, and the Lamson Professor of Computer Science at The Center for Advanced Computer Studies, University of Louisiana at Lafayette, where he has been a faculty member since 1985. He has edited and co-edited three books in the area of VLSI Signal Processing. He was an Associate Editor of the Circuits and Devices Magazine and is currently an Associate Editor of Integration, the VLSI Journal, and the Journal of VLSI Signal Processing Systems. He is a Regional Editor for the VLSI Design Journal and on the Advisory Board of the Journal on Microelectronics Systems Integration. He has one patent pending. His research interests include VLSI design methods and architectures, low power circuits and systems, digital signal processing architectures, parallel algorithm design, computer arithmetic, image and video signal processing, neural networks, and wideband network architectures. Dr. Bayoumi received the University of Louisiana at Lafayette 1988 Researcher of the Year Award and the 1993 Distinguished Professor Award. He was an Associate Editor of the IEEE CIRCUITS AND DEVICES MAGAZINE, the IEEE TRANSACTIONS ON VLSI SYSTEMS, the IEEE TRANSACTIONS ON NEURAL NETWORKS, and the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING. From 1991 to 1994, he served on the Distinguished Visitors Program for the IEEE Computer Society, and he is on the Distinguished Lecture Program of the Circuits and Systems Society. He was the Vice President for the technical activities of the IEEE Circuits and Systems Society. He was the Co-chairman of the Workshop on Computer Architecture for Machine Perception in 1993, and is a member of the Steering Committee of this workshop. He was the General Chairman of the 1994 MWSCAS and is a member of the Steering Committee of this symposium. He was the General Chairman for the 8th Great Lake Symposium on VLSI in 1998. He has been on the Technical Program Committee for ISCAS for several years and he was the Publication Chair for ISCAS'99. He was also the General Chairman of the 2000 Workshop on Signal Processing Design and Implementation. He was a founding member of the VLSI Systems and Applications Technical Committee and was its Chairman. He is currently the Chairman of the Technical Committee on Circuits and Systems for Communication and the Technical Committee on Signal Processing Design and Implementation. He is a member of the Neural Network and the Multimedia Technology Technical Committees. Currently, he is the faculty advisor for the IEEE Computer Student Chapter at the University of Louisiana at Lafayette.     

DAWL: A Delayed-ACK Scheme for MAC-Level Performance Enhancement of Wireless LANs

The IEEE 802.11 MAC protocol provides a reliable link layer using Stop & Wait ARQ. The cost for high reliability is the overhead due to acknowledgement packets in the direction opposite to the actual data flow. In this paper, the design of a new protocol as an enhancement of IEEE 802.11 is proposed, with the aim of reducing supplementary traffic overhead and increasing the bandwidth available for actual data transmission. The performance of the proposed protocol is evaluated through comparison with IEEE 802.11 as well as with a SSCOP-based protocol. Results underline significant advantages of the proposed protocol against existing ones, thus confirming the value and potentiality of the approach.Dzmitry Kliazovich received his Masters degree in telecommunication science from Belarusian State University of Informatics and Radioelectronics in 2002. He is currently working towards the Ph.D. degree in University of Trento, Italy. His main research interest lies in wireless networking field with a focus on performance optimization and cross-layer design.Fabrizio Granelli was born in Genoa in 1972. He received the “Laurea” (M.Sc.) degree in Electronic Engineering from the University of Genoa, Italy, in 1997, with a thesis on video coding, awarded with the TELECOM Italy prize, and the Ph.D. degree in Electronic Engineering and Computer Science from the same university in 2001. Since 2000 he is carrying on his teaching activity as Assistant Professor at the Dept. of Information and Communication Technologies (DIT) of the University of Trento (Italy) within the B.Sc. and M.Sc. Degrees in Telecommunications Engineering.The research interests of Dr. Granelli are mainly focused on networking, with particular attention to network modeling and performance evaluation, wireless networks, access control, and next-generation telecommunication networks.He is author of more than 30 refereed papers, published in several international journals and conferences.Dr. Granelli is member of the IEEE Committee on “Communication Systems Integration and Modeling” (CSIM) and of the Technical Programme Committee of the “QoS and Performance Evaluation Symposium” of the International Conference on Communications (ICC 2003 and ICC 2004).     

Signal threshold adaptation for vertical handoff in heterogeneous wireless networks

The convergence of heterogeneous wireless access technologies has been envisioned to characterize the next generation wireless networks. In such converged systems, the seamless and efficient handoff between different access technologies (vertical handoff) is essential and remains a challenging problem. The heterogeneous co-existence of access technologies with largely different characteristics results in handoff asymmetry that differs from the traditional intra-network handoff (horizontal handoff) problem. In the case where one network is preferred, the vertical handoff decision should be carefully executed, based on the wireless channel state, network layer characteristics, as well as application requirements. In this paper, we study the performance of vertical handoff using the integration of 3G cellular and wireless local area networks as an example. In particular, we investigate the effect of an application-based signal strength threshold on an adaptive preferred-network lifetime-based handoff strategy, in terms of the signalling load, available bandwidth, and packet delay for an inter-network roaming mobile. We present an analytical framework to evaluate the converged system performance, which is validated by computer simulation. We show how the proposed analytical model can be used to provide design guidelines for the optimization of vertical handoff in the next generation integrated wireless networks. This article is the extended version of a paper presented in IFIP Networking 2005 Ahmed H. Zahran is a Ph.D. candidate at the Department of Electrical and Computer Engineering, University of Toronto. He received both his M.Sc. and B.Sc. in Electrical Engineering from Electronics and Electrical Communication Department in the Faculty of Engineering, Cairo University in 2002 and 2000 respectively, where he was holding teaching and research positions. Since September 2003, he has been working as a research assistant in the Department of Electrical and Computer Engineering, University of Toronto under the supervision of Professor Ben Liang. His research interest is wireless communication and networking with an emphasis on the design and analysis of networking protocols and algorithms. Ben Liang received honors simultaneous B.Sc. (valedictorian) and M.Sc. degrees in Electrical Engineering from Polytechnic University in Brooklyn, New York, in 1997 and the PhD degree in Electrical Engineering with Computer Science minor from Cornell University in Ithaca, New York, in 2001. In the 2001–2002 academic year, he was a visiting lecturer and post-doctoral research associate at Cornell University. He joined the Department of Electrical and Computer Engineering at the University of Toronto as an Assistant Professor in 2002. His current research interests are in the areas of mobile networking and wireless multimedia systems. He is a member of Tau Beta Pi, IEEE, and ACM and serves on the organization and technical program committees of a number of major conferences each year. Aladdin Saleh earned his Ph.D. degree in Electrical Engineering from London University, England. Since March 1998, Dr. Saleh has been working in the Wireless Technology Department of Bell Canada, the largest service provider of wireless, wire-line, and Internet in Canada. He worked as a senior application architect in the wireless data group working on several projects among them the wireless application protocol (WAP) and the location-based services. Later, he led the work on several key projects in the broadband wireless network access planning group including planning of the IEEE 802.16/ Wimax, the IEEE 802.11/ WiFi, and the integration of these technologies with the 3G cellular network including Mobile IP (MIP) deployment. Dr. Saleh also holds the position of Adjunct Full Professor at the Department of Electrical and Computer Engineering of Waterloo University, Canada since January 2004. He is currently conducting several joint research projects with the University of Waterloo and the University of Toronto on IEEE 802.16-Wimax, MIMO technology, interworking of IEEE 802.11 WLAN and 3G cellular networks, and next generation wireless networks. Prior to joining Bell Canada, Dr. Saleh worked as a faculty member at different universities and was Dean and Chairman of Department for several years. Dr. Saleh is a Fellow of IEE and a Senior Member of IEEE.     

A low-power, second-order Δ/Σ modulator using a single class-AB op-amp for voice-band applications

The design of a power-efficient second-order Δ/Σ modulator for voice-band is presented. At system level, a new single-loop, single-stage modulator is proposed. The modulator employs only one class-AB op-amp to realize a second-order noise shaping for voice-band applications. The modulator is designed in a 0.25μm standard CMOS process, and exhibits 86 dB dynamic range (DR) for a 4 kHz voice-bandwidth. The proposed modulator consumes 125μW from a 2.5 V supply. Aminghasem Safarian received the B.S. and M.S. degrees in electrical engineering from the Sharif University of Technology, in 2000, 2002, respectively. Since 2003 he is a research assistant at University of California, Irvine, working toward his Ph.D. degree in electrical engineering emphasizing on RF IC design for wireless communication systems. During the summer of 2005, he was with Broadcom Corporation, Irvine, CA, where he developed integrated receivers for RFID and WCDMA applications. Farzad Sahandiesfanjani was born in Tabriz, Iran in 1976. He received the B.S. and M.S. degrees in electronics from Sharif University of Technology, Tehran, Iran, in 1998 and 2000, respectively. The subject of his thesis was the design of 4th order cascade delta-sigma modulator for ADSL Analog Front End. From 1998 to 2003, he was with Emad Semicon Co., Tehran, Iran, where he designed circuits for voice application such as CODEC and SLIC chip. He also designed a 3rd order single loop class-D delta-sigma modulator for audio application. He joined Tripath Technology Inc., San Jose, CA, in 2003 and has been working on the design of analog and mixed-signal circuits for class-T audio power amplifier. He is also author of one patent for inductor-less switching audio power amplifier and also co-author of 3 more pending patents and 4 papers. Payam Heydari (S'98–M'00) received the B.S. and M.S. degrees (with honors) in electrical engineering from the Sharif University of Technology, in 1992, 1995, respectively. He received the Ph.D. degree in electrical engineering from the University of Southern California, in 2001. During the summer of 1997, he was with Bell-Labs, Lucent Technologies, Murray Hill, NJ, where he worked on noise analysis in deep submicron very large-scale integrated (VLSI) circuits. During the summer of 1998, he was with IBM T. J. Watson Research Center, Yorktown Heights, NY, where he worked on gradient-based optimization and sensitivity analysis of custom-integrated circuits. Since August 2001, he has been an Assistant Professor of Electrical Engineering at the University of California, Irvine, where his research interest is the design of high-speed analog, radio-frequency (RF), and mixed-signal integrated circuits. Dr. Heydari has received the 2005 National Science Foundation (NSF) CAREER Award, the 2005 IEEE Circuits and Systems Society Darlington Award, the 2005 Henry Samueli School of Engineering Teaching Excellence Award, the Best Paper Award at the 2000 IEEE International Conference on Computer Design (ICCD), the 2000 Honorable Award from the Department of EE-Systems at the University of Southern California, and the 2001 Technical Excellence Award in the area of Electrical Engineering from the Association of Professors and Scholars of Iranian Heritage (APSIH). He was recognized as the 2004 Outstanding Faculty at the EECS Department of the University of California, Irvine. His name was included in the 2006 Who's Who in America. Dr. Heydari is an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—part I. He currently serves on the Technical Program Committees of Custom Integrated Circuits Conference (CICC), International Symposium on Low-Power Electronics and Design (ISLPED), International Symposium on Quality Electronic Design (ISQED), and the Local Arrangement Chair of the ISLPED conference. He was the Student Design Contest Judge for the DAC/ISSCC Design Contest Award in 2003, the Technical Program Committee member of the IEEE Design and Test in Europe (DATE) from 2003 to 2004, and International Symposium on Physical Design (ISPD) in 2003. Mojtaba Atarodi received his Ph.D degree from USC (the University of Southern California, Los Angeles), in electrical engineering Electro-physics in 1993, his M.S from University of California at Irvine, and his B.SEE from the Tehran Polytechnic University with first Grade honor. Following his Ph.D completion, he was with Linear Technology Corporation from 1993 to 1996 as an analog design engineer. He has been with Sharif University of Technology as an Assistant and Visiting Professor since 1997. The Author of more than 50 technical journal and conference papers an a book on Analog CMOS IC Design, Dr Atarodi’s main research interests are analog and RF IC system, circuit, and signal processing design as well as analog synthesis tools. Having held several management and consulting positions during the last 15 years in the US industry, he holds one US patent in analog highly linear tunable Operational Transconductance Amplifiers and has applied for 5 more US patents as well.     

A dual complex pole-zero cancellation frequency compensation with gain-enhanced stage for three-stage amplifier

A dual complex pole-zero cancellation (DCPC) frequency compensation technique with gain enhanced stage (GES) for three-stage amplifier is proposed in this paper. It uses one pair of complex zeros to cancel one pair of complex poles, resulting in feature that the frequency response of three-stage amplifier exhibits that of a single-pole system. Meanwhile, the effective transconductance of output stage can be greatly increased by several times which are equal to gain of GES, and the power dissipation can be decreased when a GES is introduced. Thus the gain-bandwidth (GBW) is expected to be increased about 10 times compared to the conventional nested miller compensation (NMC) approach. Moreover, this technique requires only one very small compensation capacitor even when driving a large load capacitor. A GBW of 1.23 MHz, DC gain of 111 dB, PM of 86° and power dissipation of 0.29 mW can be achieved for a load capacitor of 500 pF with a single Miller compensation capacitor of 14 pF at a ± 1 V supply in a standard 0.6-μm CMOS technology. Qiang Li received the B.S. degree and the M.Sc. degree in College of Microelectronics and Solid-state Electronics from University of Electronic and Technology Science of China (UESTC), in 2002 and 2005, respectively. His main research interest is low-voltage low-power analog ICs and power switch management ICs. From 2005, he joined the o2micro as an analog IC designer. Jun Yi un Yi received the B.S. degree and the M.Sc. degree, both in Microelectronics, from University of Electronic Science and Technology of China, Chengdu, China, in 2001 and 2004, respectively. He is currently working toward the Ph.D. degree at The Hong Kong University of Science and Technology, Hong Kong, China. His research interests include low-voltage low-power analog and mixed-signal integrated circuits, low-power power management system, with current emphasis on ultra-low-power power management and signal processing integrated circuits for micro-sensor, RFID, and biomedical applications. Bo Zhang was born in Chongqing, China, on May 26, 1964. He received his B. Tech. degree in electronic engineering from Beijing Institute of Technology, China in 1985, the M. Tech. degree from the University of Electronic Science and Technology of China in 1988. From 1988 to 1996, he worked on power semiconductor devices research and development at the University of Electronic Science and Technology of China. From 1996 to 1999, he was a Visiting Professor at Virginia Polytechnic Institute and State University, Blacksburg, U.S.A., where his research activities include device simulations, power semiconductor cryogenics, SiC power devices, and other Si-based power semiconductor devices. Since returning to the University of Electronic Science and Technology, China, in Nov. 1999, he has worked on power devices and smart power ICs. He is currently a Professor and has published more than 100 papers in the international conferences and journals. Zhaoji Li, professor, the director of IC design center of University of Electronic Science and Technology of China (UESTC).     

A Low Voltage 14-Bit Self-Calibrated CMOS DAC with Enhanced Dynamic Linearity

A 1-V CMOS current steering digital to analog converter with enhanced static and dynamic linearity is presented. The 14-bit static linearity is achieved by a background analog self calibration technique which is suitable for low voltage applications and does not require error measurement and correction circuits. To improve dynamic linearity at high frequencies, a track/attenuate output stage is used at the DAC output. Integral and differential nonlinearities of the proposed DAC corresponding to 14-bit specification are less than 0.35 and 0.25 LSB, respectively. The DAC is functional up to 400MS/s with SFDR better than 71 dB in the Nyquist band. The circuit has been designed and simulated in a standard 0.18 u CMOS technology. Saeed Saeedi was born in Tehran, Iran, in 1979. He received the B.Sc. and M.Sc. degrees in electrical engineering from Sharif University of Technology, Tehran, Iran in 2001 and 2003, respectively. Since 2002, he has been working with Iran Microelectronics Research Center, IMRC. He is currently working toward the Ph.D. degree. His research interests include analog and digital integrated circuits for communication systems and high performance data converters. Saeid Mehrmanesh was born in Arak, Iran in 1976. He received the B.Sc. and M.Sc. degrees in electrical engineering from Sharif University of Technology, Tehran, Iran, in 1999 and 2002. From 2000, he has been working with Iran Microelectronics Research Center as an analog and mixed-mode and RF-IC design engineer. Since 2004, he has been a Ph.D. student at the University of Tehran. His research interests include analog to digital and digital to analog data converters, low voltage and low power CMOS circuits, telecommunication circuits, high speed serial links and RF circuits. Mojtaba Atarodi received the B.S.E.E. from Amir Kabir University of Technology (Tehran Polytechnic) in 1985, and M.Sc. degree in electrical engineering from the University of California, Irvine, in 1987. He received the Ph.D. degree from the University of Southern California (USC) on the subject of analog IC design in 1993.From 1993 to 1996 he worked with Linear Technology Corporation as a senior analog design engineer. Since then, he has been consulting with different IC companies. He is currently a visiting professor at Sharif University of Technology. He has published more than 30 technical papers in the area of analog and mixed-signal integrated circuit design as well as analog CAD tools.This revised version was published online in May 2005 with corrections to the authors affiliations.     

New layout strategies with improved matching performance

In this paper, the systematic mismatch error in integrated circuits due to gradient effects is modeled and analyzed. Three layout strategies with improved matching performance are reviewed and summarized. The hexagonal tessellation pattern can cancel quadratic gradient errors with only 3 units for each device and has high area-efficiency when extended. Both the Nth-order circular symmetry patterns and Nth-order central symmetry patterns can cancel up to Nth-order gradient effects between two devices using 2^N unit cells for each one. Among these three techniques, the central symmetry patterns have the best-reported matching performance for Manhattan structures; the circular-symmetry patterns have the best theoretical matching performance; and the hexagonal tessellation pattern has high density and high structural stability. The Nth-order central symmetry technique is compatible to all IC fabrication processes requiring no special design rules. Simulation results of these proposed techniques show better matching characteristics than other existing layout techniques under nonlinear gradient effects. Specifically, two pairs of P-poly resistors using 2nd and 3rd-order central symmetry patterns were fabricated and tested. Less than 0.04% mismatch and less than 0.002% mismatch were achieved for the 2nd and the 3rd-order structures, respectively. Chengming He was born in YiWu, China in 1976. He received his B.S. in 1999 in Electronic Engineering department and his M.S. degree in the institute of Microelectronics in 2001 at Tsinghua University, Beijing. He started to work toward his PhD in Iowa State University since August 2001. Since June 2004 he started to work as a design engineer in Silicon Laboratories, Inc., Austin, TX. He studied and designed LNA, band-pass filter and on-chip power management blocks as well as matching-enhanced layout patterns. He is interested in designing high gain low voltage amplifier, high speed power-efficient ADC and high speed high linear DAC as well as other mixed-signal circuits. He is also interested in the application of nonlinear system dynamical theory in mixed-signal design and yield-enhancement by improving layout matching. He has published more than 10 technical papers. He was a student member of IEEE from 01--04 and now is a member. He is a member of Tau Beta Pi. Xin Dai was born in Shanghai, China on March 11, 1981. She received the B.Eng. in 2003 from Shanghai Jiao Tong University, Shanghai, China. She is currently a graduate student in Department of Electrical and Computer Engineering at Iowa State University, Ames, IA. Her research has been connected to data converter design and calibrations, layout techniques and build-in-self-test. Xin Dai is now taking a summer-intern in Broadcom Corp., CA. Hanqing Xing was born in Dalian, China, in 1978. He received the B.S. and M.S. degrees with honors in Electronic Engineering from Tsinghua University, Beijing, China, in 2000 and 2003, respectively. He is currently a PhD student at Iowa State University working in analog and mixed signal design group. His research interests include analog, mixed-signal, and data-conversion integrated circuits design and test. Degang Chen received his B.S. degree in 1984 in Instrumentation and Automation from Tsinghua University, Beijing, China and his M.S. and Ph.D. degrees in 1988 and 1992, respectively, both in Electrical and Computer Engineering, from the University of California, Santa Barbara. From 1984 to 1986, he was with the Beijing Institute of Control Engineering, a space industry R/D institute. From March 1992 to August 1992, he was the John R. Pierce Instructor of Electrical Engineering at California Institute of Technology. After that, he joined Iowa State University where he is currently an Associate Professor. He was with the Boeing Company in summer of 1999 and was with Dallas Semiconductor-Maxim in summer of 2001. His research experience include particulate contamination in microelectronic processing systems, vacuum robotics in microelectronics, adaptive and nonlinear control of electromechanical systems, and dynamics and control of atomic force microscopes. His current teaching and research interests are in the area of analog and mixed-signal VLSI integrated circuit design and testing. In particular, he is interested in low-cost high-accuracy testing and built-in-self-test of analog and mixed-signal and RF circuits, and in self-calibration and adaptive reconfiguration/repair strategies for performance and yield enhancement. Dr. Chen is the recipient of the Best Paper Award at the 1990 IEEE Conference on Decision and Control and the Best Transaction Paper Award from the ASME Journal of Dynamic Systems, Measurement, and Control in 1995. He was selected an A.D. Welliver Faculty Fellow with the Boeing Company in 1999.