共查询到19条相似文献,搜索用时 156 毫秒
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一种全景图像浏览器的设计与实现 总被引:1,自引:0,他引:1
全景图像存在几何畸变,全景图像浏览器的作用就是根据用户的视线方向以及观察焦距,对全景图像进行实时的畸变校正,提供给用户符合视觉习惯的局部图像.本文对现有的球面全景图像畸变校正算法进行了研究和改进,采用双线性插值、查询线性表等方法设计实现了一个高实时性、高精度的全景图像浏览器PanoViewer. 相似文献
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针对鱼眼图像校正中水平方向畸变以及边缘缺失的问题,通过引入可控参数控制边缘部分的校正范围,同时融合三角计算以及参数变换,获取校正关系,使映射面与鱼眼图像达到最佳匹配结果.获取校正关系后运用双线性插值算法对校正图像进行插值运算以填充图像.实验表明,算法对视图主要区域和边缘部分畸变的校正取得较好效果,边缘部分信息流失较少,主视图区域畸变角度明显减小,校正后图像与未畸变源图像相比结构相似性高,尽可能大的保留鱼眼图像信息,算法效率提高,算法运行时间缩短近50%.该鱼眼图像校正算法在校正效率以及校正效果上都有显著提高,具有可行性和有效性. 相似文献
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为了校正广角图像的非线性畸变,提出一种新的数字校正方法来消除畸变。首先利用网格模板校正的方法,根据畸变图与理想图对应像素点的映射关系,得到畸变图像点在x轴和y轴方向上的偏移量。然后采用三次B插值函数对曲面插值,得到畸变像素点的偏移量曲面,由偏移量曲面和畸变点的坐标实现各像素点的坐标变换。最后通过双线性插值法完成灰度重建得到无畸变的图像,从而实现对广角图像的校正。为了测试该算法的速度性能和可靠性等指标,在DSP平台上运行此算法。实验结果表明该算法能够对广角畸变图像进行快速有效的校正。 相似文献
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新的桶形畸变的点阵样板校正方法 总被引:1,自引:0,他引:1
为了校正广角镜头的桶形畸变,提出一种新的桶形畸变数字校正方法。它使用点阵样板校正的方法,根据畸变图和理想图中圆点的位置关系,得出畸变图像素在X轴和Y轴方向上的偏移量曲面,采用三次B插值函数对曲面插值;由曲面插值获取像素点的偏移量,对各像素进行坐标转换得到校正图像;然后对图像进行了双线性插值的灰度重建。仿真结果表明,该方法使图像的坐标位置和灰度都得到很好的校正。 相似文献
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为校正航空相机大视场角镜头的畸变,基于Matlab的calib_toolbox工具箱,对拍摄的多幅不同角度和距离的模板进行摄像机标定,得出摄像机的内部参数和畸变系数,建立正确的畸变校正数学模型,通过后续编程处理,改进了Bouguet方法,可实现航空相机彩色图像的畸变校正,并提出一种新的有效的逆推重建图形比对法对图像的畸变率进行分析,量化畸变程度。仿真结果显示,该方法得到的彩色图像的畸变率校正后平均降低了大约10%。实验结果表明,该方法简单高效,且便于后续硬件移植,可实现实时畸变校正处理。 相似文献
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一种基于斜率的摄像机畸变校正方法 总被引:8,自引:0,他引:8
普通 CCD摄像机在成像时都存在畸变成像误差 ,在机器人视觉检测及自动装配中 ,有效地进行误差校正对准确确定物体的位置具有重要的意义 .本文采用带有一阶径向畸变的小孔摄像机模型 ,提出一种基于线段斜率的方法 ,对摄像机镜头的径向畸变进行校正 ,不必标定太多的摄像机的外参数 ,方法简洁 ,适合于视觉系统中对摄像机畸变的实时校正 ,或对摄像机捕获的图像进行几何校正 .实验表明 ,具有很强的鲁棒性和较高的校正精度 相似文献
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《计算机应用与软件》2015,(9)
大视场镜头因其可得到较大视场的图像而获得广泛应用,但由于镜头的原因,导致成像的桶形畸变,在直接使用从镜头获取的图像时,会影响对图像的后期处理和分析。针对这种情况,在分析畸变产生原因的基础上,提出一种改进的桶形畸变校正方法。根据畸变与焦距、成像高度之间对应的变化规律提出一种改进的半球形畸变校正模型,并计算近似畸变率,以进行反向映射及双线性插值来得到校正后的图像,设置可调整的参数,给出参数的确定方法和选择范围。最后,利用畸变的对称性降低了校正的计算复杂度和时间。实验结果表明,该算法对广角镜头产生的桶形畸变获得了较好的校正结果,降低了平均畸变率误差。该算法能够准确地校正畸变图像,不需要特定模板和标定参数,计算简单容易实现。 相似文献
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《Real》1999,5(3):155-165
In this paper we describe a video compression system developed for remotely controlled vehicles. Unlike most video compression systems, the component algorithms here are designed to match the informational properties of human color and contrast channels. The algorithms have been implemented on a four-processor real-time compression hardware system. The implemented system significantly reduces the bandwidth of video transmission but still keeps the important images features constructable in high accuracy. 相似文献
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This paper describes an efficient hardware architecture of 2D-Scan-based-Wavelet watermarking for image and video. The potential application for this architecture includes broadcast monitoring of video sequences for High Definition Television (HDTV) and DVD protection and access control. The proposed 2D design allows even distribution of the processing load onto a set of filters, with each set performing the calculation for one dimension according to the scan-based process. The video protection is achieved by the insertion of watermarks bank within the middle frequency of wavelet coefficients related to video frames by their selective quantization. The 2-D DWT is applied for both video stream and watermark in order to make the watermarking scheme robust and perceptually invisible. The proposed architecture has a very simple control part, since the data are operated in a row-column-slice fashion. This organization reduces the requirement of on-chip memory. In addition, the control unit selects which coefficient to pass to the low-pass and high-pass filters. The on-chip memory will be small as compared to the input size since it depends solely on the filter sizes. Due to the pipelining, all filters are utilized for 100% of the time except during the start-up and wind-down times. The major contribution of this research is towards the selection of appropriate real time watermarking scheme and performing a trade-off between the algorithmic aspects of our proposed watermarking scheme and the hardware implementation technique. The hardware architecture is designed, as a watermarking based IP core with the Avalon interface related to NIOS embedded processor, and tested in order to evaluate the performance of our proposed watermarking algorithm. This architecture has been implemented on the Altera Stratix-II Field Programmable Gate Array (FPGA) prototyping board. Experimental results are presented to demonstrate the capability of the proposed watermarking system for real time applications and its robustness against malicious attacks. 相似文献
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We present a multimodal registration algorithm between images in the visible, short-wave infrared and long-wave infrared spectra. The algorithm works with two reference-objective image pairs and operates in two stages: (1) A calibration phase between static frames to estimate the transformation parameters using histogram of oriented gradients and the Chi-square distance; (2) a frame-by-frame mapping with these parameters using a projective transformation and a bilinear interpolation to map the objective video stream to the coordinate system of the reference video stream. We present a distributed heterogeneous architecture that combines a programmable processor core and a custom hardware accelerator for each node. The software performs the calibration phase, whereas the hardware computes the frame-by-frame mapping. We implemented our design using a Xilinx Zynq XC7Z020 system-on-a-chip for each node. The prototype uses 2.38W of power, 25% of the logic resources and 65% of the available on-chip memory per node. Running at 100MHz, the core can register 640 × 512-pixel frames in 4ms after initial calibration, which allows our module to operate at up to 250 frames per second. 相似文献
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基于视频阵列处理器高效视频编码HEVC实现中,HEVC灵活的编码块增加了率失真优化算法硬件实现的难度,难以实现阵列规模和不同块的灵活切换.针对这一问题,提出一种动态可重构的率失真优化实现方法.基于上下文切换的动态重构机制,完成不同规模、不同块大小算法之间的灵活切换,并以率失真优化算法作为帧内模式选择的判别依据,实现帧内... 相似文献