杂质分凝技术对肖特基势垒高度的调制

为降低金属或金属硅化物源漏与沟道的肖特基势垒高度以改善肖特基势垒源漏场效应晶体管(SBSD-MOSFET)的开关电流比(Ion/Ioff),采用硅化诱发杂质分凝技术(SIDS)调节NiSi/n-Si肖特基二极管(NiSi/n-Si SJD)的肖特基势垒高度,系统地研究了SIDS工艺条件如杂质注入剂量、注入能量和硅化物形成工艺对肖特基势垒高度调节的影响。实验结果表明,适当增加BF2杂质的注入剂量或能量均能显著提高有效电子势垒高度(φBn,eff),也即降低了有效空穴势垒高度(φBp,eff),从而减小反向偏置漏电流。同时,与传统的一步退火工艺相比,采用两步退火工艺形成NiSi也有利于提高有效电子势垒高度,减小反向漏电流。最后,提出了一种优化的调制肖特基势垒高度的SIDS工艺条件。     

Analysis of Schottky Barrier Height in Small Contacts Using a Thermionic‐Field Emission Model

This paper reports on estimating the Schottky barrier height of small contacts using a thermionic‐field emission model. Our results indicate that the logarithmic plot of the current as a function of bias voltage across the Schottky diode gives a linear relationship, while the plot as a function of the total applied voltage across a metal‐silicon contact gives a parabolic relationship. The Schottky barrier height is extracted from the slope of the linear line resulting from the logarithmic plot of current versus bias voltage across the Schottky diode. The result reveals that the barrier height decreases from 0.6 eV to 0.49 eV when the thickness of the barrier metal is increased from 500 Å to 900 Å. The extracted impurity concentration at the contact interface changes slightly with different Ti thicknesses with its maximum value at about 2.9×10²⁰ cm^?3, which agrees well with the results from secondary ion mass spectroscopy (SIMS) measurements.     

High-Quality Schottky Contacts for Limiting Leakage Currents in Ge-Based Schottky Barrier MOSFETs

Schottky barrier (SB) Ge channel MOSFETs suffer from high drain-body leakage at the required elevated substrate doping concentrations to suppress source–drain leakage. Here, we show that electrodeposited Ni–Ge and NiGe/Ge Schottky diodes on highly doped Ge show low off current, which might make them suitable for SB p-MOSFETs. The Schottky diodes showed rectification of up to five orders of magnitude. At low forward biases, the overlap of the forward current density curves for the as-deposited Ni/n-Ge and NiGe/n-Ge Schottky diodes indicates Fermi-level pinning in the Ge bandgap. The SB height for electrons remains virtually constant at 0.52 eV (indicating a hole barrier height of 0.14 eV) under various annealing temperatures. The series resistance decreases with increasing annealing temperature in agreement with four-point probe measurements indicating the lower specific resistance of NiGe as compared to Ni, which is crucial for high drive current in SB p-MOSFETs. We show by numerical simulation that by incorporating such high-quality Schottky diodes in the source/drain of a Ge channel PMOS, a highly doped substrate could be used to minimize the source-to-drain subthreshold leakage current.      

Enhancement of the Schottky Barrier Height using a Nitrogen-Rich Tungsten Nitride Thin Film for the Schottky Contacts on AlGaN/GaN Heterostructures

Tungsten, stoichiometric W₂N, and nitrogen-rich W₂N films were used as Schottky contacts on AlGaN/GaN heterostructures. The nitrogen content in the film was controlled by varying the nitrogen-to-argon gas flow ratio during the reactive sputter deposition. The diode with the nitrogen-rich film exhibited a higher Schottky barrier height and the leakage current was comparable to that of the Ni/Au Schottky contact. Analysis suggested that this was due to the increase of the tungsten nitride work function as the result of higher nitrogen incorporation. Furthermore, after 600°C thermal annealing, the diode was stable and showed no change in the leakage current.     

Accurate Extraction of Schottky Barrier Height and Universality of Fermi Level De-Pinning of van der Waals Contacts

Due to Fermi level pinning (FLP), metal-semiconductor contact interfaces result in a Schottky barrier height (SBH), which is usually difficult to tune. This makes it challenging to efficiently inject both electrons and holes using the same metal—an essential requirement for several applications, including light-emitting devices and complementary logic. Interestingly, modulating the SBH in the Schottky–Mott limit of de-pinned van der Waals (vdW) contacts becomes possible. However, accurate extraction of the SBH is essential to exploit such contacts to their full potential. In this study a simple technique is proposed to accurately estimate the SBH at the vdW contact interfaces by circumventing several ambiguities associated with SBH extraction. Using this technique on several vdW contacts, including metallic 2H-TaSe₂, semi-metallic graphene, and degenerately doped semiconducting SnSe₂, it is demonstrated that vdW contacts exhibit a universal de-pinned nature. Superior ambipolar carrier injection properties of vdW contacts are demonstrated (with Au contact as a reference) in two applications, namely, a) pulsed electroluminescence from monolayer WS₂ using few-layer graphene (FLG) contact, and b) efficient carrier injection to WS₂ and WSe₂ channels in both n-type and p-type field effect transistor modes using 2H-TaSe₂ contact.     

金属-半导体接触势垒高度的理论计算

采用平均键能作为参考能级计算了十种金属 -半导体接触势垒高度 ,其计算结果与实验值的符合程度不亚于 Tersoff和 M o¨ nch所采用的电中性能级方法 ,计算结果表明平均键能方法和 Tersoff提出的电中性能级方法一样 ,可作为金属 -半导体接触势垒高度的一种理论计算方法     

Evaluation of the Schottky Barrier Parameters in the Micron-Size Metal-Semiconductor Contacts

We show that under certain conditions the submillimeter wave detector response of a Schottky barrier diode is a linear function of applied bias and allows evaluation of the barrier height and the near-surface doping level of semiconductor in the micron-size Schottky barrier contacts.     

Defect Analysis of Barrier Height Inhomogeneity in Titanium 4H-SiC Schottky Barrier Diodes

Over 350 4H-SiC Schottky barrier diodes (SBDs) of varying size are characterized using current–voltage (I–V) measurements, with some also measured as a function of temperature. Devices display either a characteristic single-barrier height or atypical dual-barrier heights. Device yields are shown to decrease as device area increases. Molten KOH etching is used to highlight defects for analysis by optical microscopy and atomic force microscopy. The I–V characteristics are compared against the defect density. A positive correlation between effective barrier height and effective electrically active area of the SBDs is found. No correlation is found between threading dislocations and ideality factor or barrier height.     

Effective Schottky Barrier Height Reduction Using Sulfur or Selenium at the NiSi/n-Si (100) Interface for Low Resistance Contacts

We explore a novel integration approach that introduces valence-mending adsorbates such as sulfur (S) or selenium (Se) by ion implantation and prior to nickel silicidation for the effective reduction of contact resistance and Schottky barrier (SB) height at the NiSi/n-Si interface. While a low SB height of ~0.12 eV can be obtained for NiSi formed on S-implanted n-Si, the insertion of a 1000degC anneal prior to silicidation leads to S out-diffusion and loss of SB modulation effects. We demonstrate that Se-implanted Si does not suffer from Se outdiffusion even after a 1000degC anneal, and subsequent Ni silicidation formed an excellent ohmic contact with a low SB height of 0.13 eV. Se segregation at the NiSi/n-Si (100) interface occurred. Implantation of Se and its segregation at the NiSi/n-Si interface is a simple and promising approach for achieving reduced SB height and contact resistance in future high-performance n-channel field-effect transistors.     

Increase in Reverse Operation Limit by Barrier Height Control of Diamond Schottky Barrier Diode

Diamond is a promising material for high-power and low-loss semiconductor devices. However, the reported reverse blocking electric field of diamond-based power devices is as low as 2 MV/cm, and their performance is worse than ideal. We have developed reach-through-type Schottky barrier diodes (SBDs) with various Schottky barrier heights (SBHs) by changing metals. SBDs with high SBH show low leakage current and high operation limit of 3.1 MV/cm. This indicates that the reverse operation limit of diamond SBDs is determined not by leakage through defects but by carrier transport through the barrier. Reduction of specific on-resistance increases Baliga's figure of merit to 51 $hbox{MW/cm}^{2}$, which is tenfold higher than the Si limit.      

Schottky Barrier Infra-Red Sensors Sensitive to Radiation of Quantum Energy Higher Than the Potential Barrier Height

The technology to obtain a silicide Pt/Ir mixture and Pt/Ir–Si photosensitive structures with a Schottky barrier in the middle IR area is developed. It is found that the main way to detect Pt/IrSi–р–Si structures is through the photoemission of Pt/IrSi holes into silicon. Moreover, the maximal photosensitivity is observed when the Pt/IrSi is not thicker than the free path length of the holes (less than 460 Å). The energy band diagram of the Schottky barrier structures based on the Pt/IrSi–Si contact is plotted. It is determined that the electron affinity of Pt/IrSi varies within 4.7–5.26 eV depending on the operational conditions of its formation.     

Schottky Barrier Characteristics of Cobalt–Nickel Silicide/n-Si Junctions for Scaled-Si CMOS Applications

Ternary cobalt–nickel silicide/n-Si Schottky diodes have been fabricated by sputtering using an equiatomic cobalt–nickel alloy target. A minimum sheet resistivity of the ternary silicide is found to be 5–7 $Omega / hbox{sq}$. Grazing-incidence X-ray diffraction shows the formation of ternary silicide phases. Cross-sectional TEM micrograph shows a fairly uniform diffusion of metals into Si with the formation of fully silicided film. Selected-area electron diffraction pattern exhibits the crystalline nature of the silicide layer. Temperature-dependent electrical current–voltage measurements have been used to characterize an optimized Schottky diode formed by annealing at 450 $^{circ}hbox{C}$. The room-temperature barrier height and ideality factor are found to be 0.656 eV and 1.6, respectively, from the $I$ –$V$ characteristics. The series resistance of the diode has been calculated and is found to be 1–11.8 $hbox{k}Omega$ . The variation of barrier height has been attributed to the inhomogeneity in Schottky junction.      

Dark-Current Suppression in Metal–Germanium–Metal Photodetectors Through Dopant-Segregation in NiGe—Schottky Barrier

We demonstrate, for the first time, the application of dopant-segregation (DS) technique in metal-germanium- metal photodetectors for dark-current suppression and high-speed performance. Low defect density and surface smooth epi-Ge (~300 nm) layer was selectively grown on patterned Si substrate using two-step epi-growth at 400degC/600degC combined with a thin (~10 nm) low-temperature Si/Si_0.8 Ge_0.2 buffer layer. NiGe with DS effectively modulates the Schottky barrier height and suppresses dark current to ~10 ^-7 A at -1 V bias (width/spacing: 30/2.5 mum). Under normal incidence illumination at 1.55 mum, the devices show photoresponsivity of 0.12 A/W. The 3 dB bandwidth under - 1 V bias is up to 6 GHz.     

Tuning of the Platinum Silicide Schottky Barrier Height on n-Type Silicon by Sulfur Segregation

The Schottky barrier height $Phi_{B}$ of platinum silicide (PtSi) contacts on n-type silicon was tuned by sulfur segregation at the PtSi/Si interface. Sulfur was implanted prior to Pt deposition and segregated at the interface during PtSi formation. It was observed that the barrier height could be tuned by changing the sulfur dose. A minimum barrier height of 0.12 eV was obtained on n-type (100) Si substrates. Since PtSi naturally provides a small $Phi_{B}$ of 0.2 eV on p-type Si, it carries the potential to serve as the single metal source/drain contact metal in a CMOS integrated circuit with $Phi_{B}$ tuning on n-channel transistors.      

Tuning of the Nickel Silicide Schottky Barrier Height on p-Type Silicon by Indium Implantation

In this letter, indium (In) implantation is introduced as a method to tune the Schottky barrier height of nickel silicide (NiSi) contacts formed on p-type silicon. Indium implantation is performed prior to NiSi formation and the implant conditions are chosen such that the implanted region is entirely consumed by the silicide. During silicide formation, some of the indium segregates at the NiSi–Si interface and can have a significant impact on the Schottky barrier height. It is shown that the barrier height decreases almost linearly with the In dose from 0.37 eV on p-type Si to 0.16 eV with an In dose of $hbox{1} times hbox{10}^{14} hbox{cm}^{-2}$ on p-type Si.      

Electrical Characteristics of 10-kV 4H-SiC MPS Rectifiers with High Schottky Barrier Height

This paper reports the study of the fabrication and characterization results of 10-kilo-volt (kV) 4H-SiC merged PiN/Schottky rectifiers. A metal contact process was developed to make the Schottky contact on n-type SiC and ohmic contact on p-type SiC at the same time. The diodes with different Schottky contact width were fabricated and characterized for comparison. With the improvement quality of the Schottky contact and the passivation layer, the devices show low leakage current up to 10 kV. The on-state characteristics from room temperature to elevated temperature (423 K) were demonstrated and compared between structures with different Schottky contact width.     

n-CdTe Schottky势垒薄膜太阳能电池中嵌入p型层对其势垒高度影响的计算机模拟

通过求解Ｐｏｉｓｓｏｎ方程，对热平衡态金属：ｐ－ｎ－ＣｄＴｅＳｃｈｏｔｋｙ势垒薄膜太阳能电池进行计算机数值模拟。嵌入的ｐ型层增大传统金属：ｎ－ＣｄＴｅ结的有效Ｓｃｈｏｔｋｙ势垒高度与ｐ型层厚度、掺杂浓度以及ｎ－ＣｄＴｅ本底电阻率有依赖关系。最后讨论嵌入ｐ型层增强ＣｄＴｅＳｃｈｏｔｋｙ势垒太阳能电池对光生载流子的收集作用。     

6H-SiC Schottky二极管的正向特性

提出了一种考虑Schottky结势垒不均匀性和界面层作用的Si C Schottky二极管( SBD)正向特性模型,势垒的不均匀性来自于Si C外延层上的各种缺陷,而界面层上的压降会使正向Schottky结的有效势垒增高.该模型能够对不同温度下Si C Schottky结正向特性很好地进行模拟,模拟结果和测量数据相符.它更适用于考虑器件温度变化的场合,从机理上说明了理想因子、有效势垒和温度的关系.     

Large‐Area Schottky Barrier Transistors Based on Vertically Stacked Graphene–Metal Oxide Heterostructures

The fabrication of all‐transparent flexible vertical Schottky barrier (SB) transistors and logic gates based on graphene–metal oxide–metal heterostructures and ion gel gate dielectrics is demonstrated. The vertical SB transistor structure is formed by (i) vertically sandwiching a solution‐processed indium‐gallium‐zinc‐oxide (IGZO) semiconductor layer between graphene (source) and metallic (drain) electrodes and (ii) employing a separate coplanar gate electrode bridged with a vertical channel through an ion gel. The channel current is modulated by tuning the Schottky barrier height across the graphene–IGZO junction under an applied external gate bias. The ion gel gate dielectric with high specific capacitance enables modulation of the Schottky barrier height at the graphene–IGZO junction over 0.87 eV using a voltage below 2 V. The resulting vertical devices show high current densities (18.9 A cm^?2) and on–off current ratios (>10⁴) at low voltages. The simple structure of the unit transistor enables the successful fabrication of low‐power logic gates based on device assemblies, such as the NOT, NAND, and NOR gates, prepared on a flexible substrate. The facile, large‐area, and room‐temperature deposition of both semiconducting metal oxide and gate insulators integrates with transparent and flexible graphene opens up new opportunities for realizing graphene‐based future electronics.     

6H-SiC Schottky二极管的正向特性

提出了一种考虑Schottky结势垒不均匀性和界面层作用的SiC Schottky二极管(SBD)正向特性模型,势垒的不均匀性来自于SiC外延层上的各种缺陷,而界面层上的压降会使正向Schottky结的有效势垒增高.该模型能够对不同温度下SiC Schottky结正向特性很好地进行模拟,模拟结果和测量数据相符.它更适用于考虑器件温度变化的场合,从机理上说明了理想因子、有效势垒和温度的关系.