A methodology for measuring the gate-drain capacitance of CMOSdevices

In this paper, the author presents a new methodology for measuring the gate drain capacitance of CMOS devices using an accelerated dc measurement scheme. The gate-drain capacitance was measured using a floating gate MOS transistor, i.e., an MOS transistor with an additional capacitor placed in series with the gate oxide capacitance. This was implemented within a standard p-well CMOS process using two matched transistors. The top capacitance couples charge onto the gate oxide capacitor and the gate-drain capacitor. The amount of coupling is determined by the ratio of these two capacitors     

Resonant converter controlled by variable capacitance devices

A new device called the variable capacitance device is proposed, and its application to the output voltage regulation of resonant converters is discussed. The new device has an independent input terminal for controlling its capacitance. The converters used are the well-known Schwarz circuit and the buck-type current-resonant converter with a resonant switch. By applying the devices to the capacitors in LC resonant tanks, the resonant converters can be regulated with the switching frequency fixed     

Metallized polymer film capacitors ageing law based on capacitance degradation

Passive components, particularly capacitors, are very used devices in power electronics applications providing key function on board. Nevertheless, capacitors breakdowns can have catastrophic consequences on the financial and human scale; a good acquaintance of their deterioration over time would contribute in the improvement of the availability of the whole system by performing a predictive maintenance on the component. This operation requires the knowledge of the capacitor ageing law and their failure mechanisms associated to the application. Capacitance loss can be mainly attributed to the self-healing process occurring in metallized film capacitors when used under high steady electrical and thermal stresses. In this paper, a capacitance ageing law is proposed based on the identification of voltage and temperature degradation kinetics from three experimental floating ageing tests performed at different voltage and temperature constraints. A total of 34 capacitors provided from different manufacturers using polyester film as dielectric have been studied and compared to validate the proposed law.     

利用半导体pn结结电容构成的沟道式电容器

为满足对电子系统中元器件性能提升、面积减小、成本降低等需求,利用感应耦合等离子体刻蚀技术(ICP),对低阻p型硅采用刻蚀、扩散、磁控溅射Al电极等工艺,使之形成凹槽状三维结构,制造出一种特殊的具有高密度电容量的硅基电容器。其特点是结构简单,电容量大(电容密度可达2.2×10–9F/mm2),容值可调,与现有微电子工艺兼容,可用于200MHz至数GHz的退耦或其他场合。同时由于半导体pn结固有的特性,该电容器可取代传统的贴片电容广泛用于电子系统中的退耦、滤波、匹配、静电和电涌防护等场合。     

ESR and capacitance monitoring of a dc-link capacitor used in a three-phase PWM inverter with a front-end diode rectifier

Condition monitoring plays an important role in estimating health condition of capacitors because the ageing of the capacitors is usually accompanied by an increase in equivalent series resistance (ESR) and a decrease in capacitance. Either capacitance or ESR cannot be a unique indicator of the lifetime of capacitors in some cases. This paper presents a condition monitoring method of a dc-link capacitor used in a three-phase PWM inverter with a front-end diode rectifier intended for motor drives. The monitoring method extracts both the ESR and capacitance of a capacitor under test from the actual ripple current and voltage without disconnecting the capacitor nor injecting an additional current. The monitoring method, therefore, can be implemented online. Experimental results verify that the monitoring method independently obtains the ESR and capacitance changes of the capacitor under test. This contributes to accurate lifetime estimation of dc-link capacitors.     

Limitations of the MOS capacitance method for the determination of semiconductor surface properties

For the use of the MOS capacitance method in the study of surface properties, various approximations and assumptions, of a purely conceptual and of an experimental nature, are usually made. These are not always justified. In this paper the applicability of this capacitance method for surface studies is examined critically. It is shown that this method is limited in its applicability and accuracy, and that, in most cases, it yields only the gross features of the surface states. If there are traps distributed spatially throughout the oxide, only an effective surface state distribution can be found, and this effective distribution may be interpreted ambiguously as due either to traps right at the interface, throughout the oxide, or both. Because the MOS capacitance consists essentially of the oxide capacitance in series with the semiconductor capacitances there is a practical lower limit on the magnitude of the semiconductor capacitance which can be measured. Together with difficulties in interpreting measurements in the inversion layer regime, this leads to a restriction on that portion of the forbidden gap in which states may be investigated. MOS capacitors, produced by thermal oxidation of silicon in either wet or dry oxygen, were examined by this method. It was found that, within experimental accuracy, and within the range of surface potential that can be covered by these measurements, the total number of occupied traps usually varies linearly with surface potential if it is assumed that all the traps are located right at the interface. However, these results can also be explained if it is assumed that the oxide contains a high density of low lying trap sites which are essentially uniformly distributed spatially throughout the oxide. In some specimens a monoenergetic trap level 0.7 eV below the conduction band and located at the interface was found.     

Switched-capacitor delay circuit that is insensitive to capacitor mismatch and stray capacitance

A new switched-capacitor delay circuit which uses only a single amplifier and is insensitive to capacitor mismatch and stray capacitance is proposed. The insensitivity to capacitor mismatch permits the use of very small-valued capacitors so that the chip area can be reduced by device scaling as the feature sizes are reduced due to improvements in technology. Tapped analogue delay lines using such delay elements would be ideal for realising programmable and adaptive filters and equalisers in analogue LSI.     

Low-frequency capacitance measurements

The letter proposes a technique for the fast determination at extremely low frequencies of the capacitance and leakage components of capacitors. The proposed method permits the measurement of C and G in only a few cycles. An apparatus is described employing this technique for the automatic measurement of m.o.s. capacitance as a function of frequency and bias voltage.     

An approximation algorithm to improve capacitance matching in the design of SC filters

A critical issue in the design of switched-capacitor (SC) filters is the capacitance matching, because the filter coefficients depend on capacitance ratios. The most successful design method to achieve an accurate capacitance matching employs a parallel arrangement of identical unit capacitors to implement each filter capacitor. However, this procedure can be directly applied only if the filter coefficients can be written as rational numbers, since each capacitor is implemented as an integer number of unit capacitors in parallel. This paper presents a systematic procedure, with low computational effort, to approximate the filter coefficients by integer ratios causing acceptable errors in the filter frequency response, whereas keeping the total number of unit capacitors small, in order to save die area. This procedure was applied in the design of a sixth-order SC band-pass filter, which has been fabricated in a 0.35 μm CMOS technology. The fabricated filter occupies an area of 0.913 mm², exhibits low sensitivity to fabrication process deviations and has an output dynamic range of 79.2 dB.     

金属化薄膜电容器电容量衰减的解决方案

针对抑制电磁干扰和降压用金属化薄膜电容器工作一段时间后容量不正常衰减的问题,通过样品解剖和理论分析,收集不同试验条件下的数据,发现金属化薄膜层间空气和封装方式导致容量不正常衰减.将热聚合温度从85℃提高到120℃,选用高温环氧树脂封装,可使所制金属化薄膜电容器在使用过程中电容量衰减小于1％,保证了电子产品在寿命周期内的...     

老练电压对铝电解电容器容量和漏电流的影响

老练电压对铝电解电容器的容量和漏电流有一定影响,对于低压（≤１６Ｖ）产品要确保老练电压的准确性;对高压（≤１００Ｖ）小容量产品,若容量偏差过大,可适当加高老练电压使其降低。老练后漏电流大的产品,加高老练电压也有良好效果。     

Gate capacitance attenuation in MOS devices with thin gatedielectrics

As gate oxides become thinner, in conjunction with scaling of MOS technologies, a discrepancy arises between the gate oxide capacitance and the total gate capacitance, due to the increasing importance of the carrier distributions in the silicon and polysilicon electrodes. For the first time, we quantitatively explore the combined impact of degenerate carrier statistics, quantum effects, and the semiconducting nature of the gate electrode on gate capacitance. Only by including all of these effects can we successfully model the capacitance-voltage behavior of sub-10 nm MOS capacitors. For typical devices, we find the gate capacitance to be 10% less than the oxide capacitance, but it can be attenuated by 25% or more for 4 nm oxides with polysilicon gates doped to less than 10²⁰ cm^-3     

MOS flat-band capacitance method at low temperatures

The expression C_FB=C_ox×(ϵ_si /L_D)/[C_ox+(ϵ_si /L_D)] (where L_D is the Debye length), commonly used for the flatband capacitance of the MOS structure, is invalid in the temperature range below 100 K. Consequently, significant error may be encountered when the flatband capacitance method is used to extract the flatband voltage, V _FB, which is of considerable interest for both the modeling and characterization of MOS devices. To extend this method to low-temperature CMOS applications one has to use a more general model that can be obtained by applying Fermi-Dirac statistics and taking into account the impurity freeze-out effect. It is shown that when the temperature dependence of V_FB is extracted using this approach, the experimental data for n⁺ polysilicon gate MOS capacitors are in good agreement with a simple method     

Analog capacitance ROM with IGFET bucket-brigade shift register

A new type of monolithic analog read-out memory is described. It consists of a memory element and associated on-chip readout circuitry. The memory can be used for storing sample values of time-varying analog signals. The memory element is a matrix of MOS capacitors, preprogrammed in size by a special mask. The readout element is a bucket-brigade shift register with parallel input and serial output. A test circuit that permits investigation of different principles of information transfer from capacitance matrix to shift register has been developed.     

Effect of etch holes on the capacitance and pull-in voltage in MEMS tunable capacitors

Microelectromechanical systems (MEMS) tunable capacitors, switches or actuators are widely applied in wireless communication systems. In the fabrication process etch holes are used to release the sacrificial layer with relatively large structures, which obviously affects the performance of devices. However, most researchers neglect this effect during their designing of the capacitors, switches or actuators. This article presents the theoretical calculation of the capacitance of tunable capacitors with etch holes, and analyses the deviation of the capacitance and pull-in voltage with different parameters such as the length of the plates w, the length of the etch holes w _h, the air gap between the two plates d, and the number of the etch holes. To validate the theory in this article, a tunable capacitor was fabricated by surface micromachined technology. The theoretical results compare well with the experimental results.     

有互感和电源的电容耦合电路的量子涨落

通过正则变换和幺正变换的方法研究了有互感和电源存在的情况下的介观电容耦合电路的量子涨落。结果表明电荷和电流的量子涨落与电源无关。当电路元件确定时，如果L1／L2的值很大或很小，耦合对涨落的影响很大。互感从有到无的过程中，回路1中电流的涨落和回路中2中电荷的涨落有明显的变化。换句话说，互感的有无对涨落的大小起着举足轻重的作用。     

Surface states at the nGaAsSiO2 interface from conductance and capacitance measurements

Conductance and capacitance measurements have been used to investigate the interface properties of MOS capacitors formed by depositing an insulating layer of SiO₂ on n-type GaAs. The surface potential as a function of applied bias is evaluated using results of high and low frequency capacitance measurements and the two methods are found to yield roughly similar results. The interface state density evaluated from the conductance and capacitance measurements is found to peak near the center of the band gap and also near the conduction band edge. Plots of conductance vs frequency indicate the presence of both fast and slow interface states in these materials.     

Power-bus decoupling with embedded capacitance in printed circuit board design

This paper experimentally investigates the effectiveness of embedded capacitance for reducing power-bus noise in high-speed printed circuit board designs. Boards with embedded capacitance employ closely spaced power-return plane pairs separated by a thin layer of dielectric material. In this paper, test boards with four embedded capacitance materials are evaluated. Power-bus input impedance measurements and power-bus noise measurements are presented for boards with various dimensions and layer stack ups. Unlike discrete decoupling capacitors, whose effective frequency range is generally limited to a few hundred megahertz due to interconnect inductance, embedded capacitance was found to efficiently reduce power-bus noise over the entire frequency range evaluated (up to 5 GHz).     

Impact of the surface roughness on the electrical capacitance

A new hybrid approach consists to use the advantages of both systems namely the high geometric aspects of the electrodes of the ultracapacitor and the high dielectric strength of polymer materials used in dielectric capacitors. The surface roughness of the electrodes of the ultracapacitor is manufactured with nano-porous materials; activated carbon and carbon nanotubes (CNTs).Many compositions of both carbonaceous materials are tested with different insulating materials (liquid and solid) to constitute the hybrid capacitor. It appears that the capacitance increases with the carbonaceous composition: An increasing from 15 to 40% is observed as compared to a plane capacitor, it can be twice with a 100 wt% of CNTs content. But, the impregnation of the insulating material in the surface roughness remains the key point of the realization of the hybrid capacitor. The roughness accessibility is a major property to optimize in order to improve the impregnation of the insulating material to increase the electrical capacitance.     

Offset-compensated switched-capacitor delay circuit that is insensitive to stray capacitance and to capacitor mismatch

A switched-capacitor delay circuit that is offset-compensated and insensitive to stray capacitance and to capacitor mismatch is proposed. It uses a four-phase clock and contains a single operational amplifier, two capacitors and seven switches. A delay line composed of such building blocks requires only two operational amplifiers per three delay sections and two clock phases per sample.<>