基于SystemC和Verilog软硬件协同验证

针对当前专用数字集成电路设计中的验证瓶颈,为了在更高的抽象级别对设计对象进行描述和验证,提出一种软硬件协同验证方法.该方法基于SystemC的交易级处理器内核模型和基于Verilog的内核之外的硬件模型.该方法被应用到东南大学研发的微处理器芯片GIV的具体验证中.实验数据表明,由于采用软硬件协同验证模型在芯片生产之前对系统功能、结构设计等进行验证,缩短了开发周期,降低了开发成本,提高了验证可靠性.     

基于SystemC的UART设计

随着集成电路设计规模的不断扩大,SOC设计的时代已经到来。SystemC作为一种新兴的SOC设计语言,它本质上是在C++的基础上添加的硬件扩展库和仿真核,这使得SystemC可以建模不同抽象级别的包括软件和硬件的复杂电子系统。在C++环境中,它支持软件、硬件和接口描述。利用SystemC的这些特性实现了对UART的建模,并用波形图验证了仿真结果。     

基于SystemC的片上系统设计

文章提出了基于SystemC的片上系统设计方法.本设计方法引入SystemC,消除了一直存在于系统级设计和硬件设计之间的语言隔阂,基于SystemC进行的系统功能定义能够方便有效地映射为硬件实现部分和软件实现部分,大大地提高了SOC时代集成电路设计效率.     

基于SystemC的系统级芯片设计方法研究

在分析当前系统级芯片设计方法的基础上，提出了目前新型系统级IC设计语言SystemC及其平台的设计思想及设计流程，并以具体项目RS编码器来实现和验证。实验结果表明，SystemC是一种很好的软硬件联合设计语言，它不仅可以帮助设计人员完成一个复杂的系统设计，还可以避免传统设计中的各种弊端，并提高设计效率。当然，如何更好地利用SystemC设计也将是EDA领域当前探索的一个重要方向。     

AVS解码器基于SystemC的实现

介绍了AVS视频编解码标准的关键技术和新一代硬件设计语言SystemC的特点以及利用SystemC进行软硬件协同设计的方法，并在此基础上介绍了AVS视频解码器基于SystemC的设计和实现。     

一种基于SystemC的D触发器验证平台研究

当今复杂电子系统更倾向于在更高抽象级进行建模一种基于C/C＋＋的硬件描述语言,SystemC语言变得非常重要,在此介绍了SystemC语言的验证库,以及验证库的顶层设计,接口设计。文章在最后的阶段对D触发器进行了基于SystemC的验证平台搭建,进而展现了SystemC在验证上的优势。     

使用SystemC设计片上自演化系统

提出片上自演化系统的概念和基于SystemC的片上自演化系统设计方法,给出片上自演化系统的总体结构,使用SystemC建模搭建自演化系统实验平台.以典型低通切比雪夫滤波器为例,验证了实验平台的有效性.使用SystemC设计自演化系统既可在较高的抽象水平搭建自演化系统模型,加速验证、性能分析和探索系统结构,又可方便地进行软硬件协同设计,并最终达到硬件实现.     

一种基于SystemC属性检查的验证方法

当今复杂电子系统倾向于在更高抽象级进行建模,一种基于C/C++的硬件描述语言,SystemC语言变得非常重要.在此探讨了一种基于SystemC属性检查的仿真验证方法.针对电路系统的线性时态逻辑属性,定义了属性表达的基本形式,并用SystemC代码描述系统属性,在仿真中检查系统属性从而达到验证目的.首先介绍SystemC语言及一种基于SystemC的属性检查方法,讨论了现有方法的不足之处,并给出了两种改进方案,最后通过实验证实该方案的有效性,同时实验表明该改进方案在仿真性能上有很大的提高.     

应用SystemC的AMBA总线系统级模型的设计与实现

对SystemC进行系统级通信结构建模的语言元素进行了深入的研究,并以一个基于AMBA总线的典型SoC为例进行了通信结构的建模.从设计的顶层开始,应用SystemC语言提供的建模能力,采用通信结构细化方法对系统级总线模块进行了细化,针对设计流程中需要将系统级模型转换为可综合的RTL级模型的问题,给出了将系统级总线通信模块转换为SystemCRTL模型的解决方法.由此,建立了完整的应用SystemC的系统级通信结构的建模方法.     

集成ISS的SystemC内核的协同验证环境设计

文章通过对Summit设计公司的Visual Elite ESC中使用的多语言协同验证工具V-CPU的分析,介绍了传统的协同验证方法的构造思想。在此基础上，应用SystemC建模语言作为统一的硬软件建模工具，通过GDB调试工具，设计了集成ISS的SystemC内核的协同验证环境的构造方法。     

基于SystemC的可配置多通道DMA控制器的设计与实现

随着集成电路技术的快速发展。处理器的速度越来越快，存储器的性能越来越好，单芯片上集成的功能部件越来越多．但是处理器跟存储器之间以及存储器跟外设之间的瓶颈却越来越严重。直接存储器存取（Direct Memory Access，DMA）方式是大多数处理器中普遍采用的提高数据传输速率的方法之一。在分析了多种高性能处理器中DMA控制器工作原理的基础上．采用系统级设计语言SystemC，设计并实现了一个多功能的可配置多通道DMA控制器。     

集成加密方案ECIES的设计与验证

椭圆曲线密码（ECC,elliptic curve cryptograph）是密码学的重要分支之一,它可以用来加密数据,进行数字签名或者在安全通信的开始阶段进行密钥交换。在加密方面,基于ECC最有名的就是综合加密方案（ECIES,elliptic curve integrate encrypt scheme）。ECIES是Certi-com公司提出的公钥加密方案,可以抵挡选择明文攻击和选择密文攻击。ECIES各个步骤的实现可以用不同的算法,在软件中是可以配置的。而它实现的多样性也验证了它的灵活性以及可靠性。     

高频异质结晶体管直流和交流模型及其验证

针对漂移扩散方程和能量平衡方程的解建立了SiGe HBT的直流和交流理论模型,综合考虑了速度饱和效应、基区和发射区的禁带变窄效应和复合效应,并与台面型SiGe HBT实验结果进行了比较,截止频率为10.5 GHz,电流增益为45,与理论结果基本符合.     

MPARM: Exploring the Multi-Processor SoC Design Space with SystemC

Technology is making the integration of a large number of processors on the same silicon die technically feasible. These multi-processor systems-on-chip (MP-SoC) can provide a high degree of flexibility and represent the most efficient architectural solution for supporting multimedia applications, characterized by the request for highly parallel computation. As a consequence, tools for the simulation of these systems are needed for the design stage, with the distinctive requirement of simulation speed, accuracy and capability to support design space exploration. We developed a complete simulation platform for a MP-SoC called MP-ARM, based on SystemC as modelling and simulation environment, and including models for processors, the AMBA bus compliant communication architecture, memory models and support for parallel programming. A fully operating linux version for embedded systems has been ported on this platform, and a cross-toolchain has been developed as well. Our MP simulation environment turns out to be a powerful tool for the MP-SOC design stage. As an example thereof, we use our tool to evaluate the impact on system performance of architectural parameters and of bus arbitration policies, showing that the effectiveness of a particular system configuration strongly depends on the application domain and the generated traffic profile.Luca Benini received the B.S. degree (summa cum laude) in electrical engineering from the University of Bologna, Italy, in 1991, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University in 1994 and 1997, respectively. He is an associate professor in the department of electronics and computer science in the University of Bologna. He also holds visiting researcher positions at Stanford University and the Hewlett-Packard Laboratories, Palo Alto, CA.Dr. Benini’s research interests are in all aspects of computer-aided design of digital circuits, with special emphasis on low-power applications, and in the design of portable systems. He is co-author of the book: Dynamic Power management, Design Techniques and CAD tools, Kluwer 1998.Dr. Benini is a member of the technical program committee for several technical conferences, including the Design Automation Conference, the International Symposium on Low Power Design and the International symposium on Hardware-Software Codesign.Davide Bertozzi received the B.S. degree in electrical engineering from the University of Bologna, Bologna, Italy, in 1999.He is currently pursuing the Ph.D. degree at the same University and is expected to graduate in 2003. His research interests concern the development of SoC co-simulation platforms, exploration of SoC communication architectures and low power system design.Alessandro Bogliolo received the Laurea degree in electrical engineering and the Ph.D. degree in electrical engineering and computer science from the University of Bologna, Bologna, Italy, in 1992 and 1998.In 1995 and 1996 he was a Visiting Scholar at the Computer Systems Laboratory (CSL), Stanford University, Stanford, CA.From 1999 to 2002 he was an Assistant Professor at the Department of Engineering (DI) of the University of Ferrara, Ferrara, Italy. Since 2002 he’s been with the Information Science and Technology Institute (STI) of the University of Urbino, Urbino, Italy, as Associate Professor. His research interests are mainly in the area of digital integrated circuits and systems, with emphasis on low power and signal integrity.Francesco Menichelli was born in Rome in 1976. He received the Electronic Engineering degree in 2001 at the University of Rome “La Sapienza”. From 2002 he is a Ph.D. student in Electronic Engineering at “La Sapienza” University of Rome.His scientific interests focus on low power digital design, and in particular in level tecniques for low power consumption, power modeling and simulation of digital systems.Mauro Olivieri received a Master degree in electronic engineering “cum laude” in 1991 and a Ph.D. degree in electronic and computer engineering in 1994 from the University of Genoa, Italy, where he also worked as an assistant professor. In 1998 he joined the University of Rome “La Sapienza”, where he is currently associate professor in electronics. His research interests are digital system-on-chips and microprocessor core design. Prof. Olivieri supervises several research projects supported by private and public fundings in the field of VLSI system design.     

Standard-compliant parallel SystemC simulation of loosely-timed transaction level models: From baremetal to Linux-based applications support

To face the growing complexity of System-on-Chips (SoCs) and their tight time-to-market constraints, Virtual Prototyping (VP) tools based on SystemC/TLM2.0 must get faster while maintaining accuracy. However, the ASI SystemC reference implementation remains sequential and cannot leverage the multiple cores of modern workstations. In this paper, we present SCale 2.0, a new implementation of a parallel and standard-compliant SystemC kernel, reaching unprecedented simulation speeds. By coupling a parallel SystemC kernel with shared resources access monitoring and process-level rollback, we can preserve SystemC atomic thread evaluation while leveraging the available host cores. We also generate process interaction traces that can be used to replay any simulation deterministically for debug purpose. Evaluation on baremetal applications shows × 15 speedup compared to the ASI SystemC kernel using 33 host cores reaching speeds above 2300 Million simulated Instructions Per Second (MIPS). Challenges related to parallel simulation of full software stack with modern operating systems are also addressed with speedup reaching × 13 during recording run and × 24 during the replay run.     

SystemC在Turbo码实现和验证中的应用

在简述System C的设计方法和流程的基础上,针对SystemC在硬件芯片系统级设计和寄存器传输级设计的特点,以Turbo编码器为对象和开发目的,研究了SystemC基于寄存器传输级设计的可实现性,利用SystemC的模块化功能,通过分析Turbo编码器的结构与信号流图,进行建模仿真直到最后完成划分硬件模块与编程并在FPGA完成其实现与验证,充分证明了SystemC完全适用于基于寄存器传输级设计的IC应用.此外,此设计将系统级设计与寄存器传输级设计的工作合二为一,大大节省了开发的流程时间.     

调试功能仿真及验证平台设计

本文档针对ARM CPU芯片,介绍了支持双核CPU芯片调试功能仿真平台和验证平台的设计及实现方法.调试功能仿真平台主要由验证脚本和Debug Driver程序组成;调试功能验证平台是基于仿真平台进行设计,直接使用仿真平台的Debug Driver程序,由MCU中验证程序替代仿真验证脚本的功能,使用验证设计更加灵活、全面...     

Design and verification of a frequency domain equalizer

In this work we provide a methodology for the design and verification of a frequency domain equalizer. The performance analysis of the equalizer is conducted using two methods: simulation based verification in Simulink and System Generator and theorem proving techniques in Higher Order Logic. We conduct both floating-point and fixed-point error estimations for the design in Simulink and System Generator, respectively. Then, we use formal error analysis based on the theorem proving to verify an implementation of the frequency domain equalizer based on the Fast LMS algorithm. The formal error analysis and simulation based error estimation of the algorithm intend to show that, when converting from one number domain to another, the algorithm produces the same values with an accepted error margin caused by the round-off error accumulation. This work shows the efficiency of combining simulation and formal verification based methods in verifying complex systems such as the frequency domain equalizer.