应变SiGe沟道PMOSFET阈值电压模型

首先建立了应变SiGe沟道PMOSFET的一维阈值电压模型,在此基础上,通过考虑沟道横向电场的影响,将其扩展到适用于短沟道的准二维阈值电压模型,与二维数值模拟结果呈现出好的符合。利用此模型,模拟分析了各结构参数对器件阈值电压的影响,并简要讨论了无Sicap层器件的阈值电压。     

多晶硅薄膜晶体管中的晶粒间界电荷分享效应

通过对晶粒间界两侧耗尽区建立准二维模型,研究晶粒间界电荷分享效应对多晶硅薄膜晶体管阈值电压的影响.研究表明,考虑了晶粒间界电荷分享效应的阈值电压将变小,其中晶粒尺寸对阈值电压的影响最大.在此基础上,建立了多晶硅薄膜晶体管的阈值电压解析模型.     

自对准双扩散MOS器件的阈值电压分析

文章提出了精确描述自对准双扩散MOS器件阀值电压的解析模型，给出了其沟道中杂质的二维分布和源结耗尽层宽度的计算方法；分析了边缘效应对氧化层电容的影响，借助电荷共事模型，建立了反映非均匀沟道中耗尽层电荷变化及其对开启电压影响的阀值电压模型；同时，借助二维仿真器，计算出自对准双扩散MOS器件的阈值电压，其值与解析值相吻合。     

Analytical I–V model of SOI and SON MOSFETs: a comparative analysis

A generalised three-interface compact capacitive threshold voltage model for horizontal silicon-on-insulator/silicon-on-nothing (SOI/SON) MOSFET has been developed. The model includes different threshold voltage-modifying short-channel phenomena like fringing field, junction-induced 2D-effects, etc. Based on the threshold voltage model, an analytical current voltage model is formulated from the basic charge control analysis of MOSFET. In order to provide a better explanation to various observations and applicable to short-channel SOI and SON structures, the present current voltage model includes the effect of carrier velocity saturation and channel length modulation. Identical structures for both the devices, SOI and SON, are considered but for SON MOSFET, the buried oxide layer is replaced by air. The performance of the two devices are studied and compared in terms of threshold voltage roll-off, subthreshold slope, drain current and drain conductance. The SON MOSFET technology is found to offer devices with further scalability and enhanced performance in terms of threshold voltage roll-off, sub-threshold slope and greater current derivability, thereby providing scope for further miniaturisation of devices and much better performance improvement.     

Bias temperature reliability of p-channel high-voltage devices

Important shifts in the threshold voltage of high voltage p-channel DMOS transistors have been observed. These shifts are strongly dependent on the stress conditions.An empirical degradation model is derived from measurement data. For a given allowed shift in threshold voltage, this model can determine the safe operating area of the device.The shift in threshold voltage in the p-channel DMOS transistors is explained by excitation and trapping of holes at the oxide-silicon interface at the drain side.     

A two-dimensional analytical-model-based comparative threshold performance analysis of SOI-SON MOSFETs

A generalized threshold voltage model based on two-dimensional Poisson analysis has been developed for SOI/SON MOSFETs.Different short channel field effects,such as fringing fields,junction-induced lateral fields and substrate fields,are carefully investigated,and the related drain-induced barrier-lowering effects are incorporated in the analytical threshold voltage model.Through analytical model-based simulation,the threshold voltage roll-off and subthreshold slope for both structures are compared for different operational and structural parameter variations.Results of analytical simulation are compared with the results of the ATLAS 2D physics-based simulator for verification of the analytical model.The performance of an SON MOSFET is found to be significantly different from a conventional SOI MOSFET.The short channel effects are found to be reduced in an SON,thereby resulting in a lower threshold voltage roll-off and a smaller subthreshold slope.This type of analysis is quite useful to figure out the performance improvement of SON over SOI structures for next generation short channel MOS devices.     

Deep submicrometer double-gate fully-depleted SOI PMOS devices: aconcise short-channel effect threshold voltage model using a quasi-2Dapproach

This paper reports a concise short-channel effect threshold voltage model using a quasi-2D approach for deep submicrometer double-gate fully-depleted SOI PMOS devices. By considering the hole density at the front and the back channels simultaneously, the analytical threshold voltage model provides an accurate prediction of the short-channel threshold voltage behavior of the deep submicrometer double-gate fully-depleted SOI PMOS devices as verified by 2D simulation results. The analytical short-channel effect threshold voltage model can also be useful for SOI NMOS devices     

A threshold voltage model for short-channel MOSFETs taking into account the varying depth of channel depletion layers around the source and drain

In this paper, an analytical model for threshold voltage of short-channel MOSFETs is presented. For such devices, the depletion regions due to source/drain junctions occupy a large portion of the channel, and hence are very important for accurate modeling. The proposed threshold voltage model is based on a realistic physically-based model for the depletion layer depth along the channel that takes into account its variation due to the source and drain junctions. With this, the unrealistic assumption of a constant depletion layer depth has been removed, resulting in an accurate prediction of the threshold voltage. The proposed model can predict the drain induced barrier lowering (DIBL) effect and hence, the threshold voltage roll-off characteristics quite accurately. The model predictions are verified against the 2-D numerical device simulator, DESSIS of ISE TCAD.     

全耗尽SOI MOSFETs阈值电压和电势分布的温度模型

提出了一个全耗尽SOI MOSFETs器件阈值电压和电势分布的温度模型.基于近似的抛物线电势分布模型,利用适当的边界条件对二维的泊松方程进行求解.同时利用阈值电压的定义得到了阈值电压的模型.该温度模型详细地研究了电势分布和阈值电压跟温度之间的变化关系,同时还近似地探讨了短沟道效应.为了进一步验证模型的正确性,利用SILVACO ATAS软件进行了相应的模拟.结果表明,模型计算与软件模拟吻合较好.     

Analytical modelling of threshold voltage for underlap Fully Depleted Silicon-On-Insulator MOSFET

In this article, surface-potential-based analytical threshold voltage model for underlap Fully Depleted Silicon-On-Insulator MOSFET (underlap-SOI) is developed by solving two-dimensional Poisson equation. The gate underlap at source/drain (S/D) has different boundary conditions as compared to channel region under the gate dielectric that divide the whole channel into three regions. It leads us to derive the new surface potential model for three different channel regions, i.e. the region under the gate dielectric and two gate underlap regions at S/D. The effects of underlap length, channel length, body thickness, channel doping concentration, metal gate work function and gate dielectric constant on threshold voltage have been included in our model. The threshold voltage dependence on different device parameters has been studied using analytical model and simulations. The closeness between the simulation results and model results show that the analytical model accurately calculate the threshold voltage values for large range of device parameters.     

三栅MOSFET阈值电压模型

根据三栅(TG)MOSFET二维数值模拟的结果,分析了TG MOSFET中的电势分布,得出了在硅体与掩埋层接触面的中心线上的电势随栅压变化的关系;通过数学推导,给出了基于物理模型的阈值电压的解析表达式;并由此讨论了多晶硅栅掺杂浓度、硅体中掺杂浓度、硅体的宽度和高度以及栅氧化层厚度对阈值电压的影响;得出在TG MOSFET器件的阈值电压设计时,应主要考虑多晶硅栅掺杂浓度、硅体中掺杂浓度和硅体的宽度等参数的结论。     

A new threshold-voltage model for small-geometry buried-channel MOSFETs

This paper presents an analytic model for the threshold voltage of small-geometry buried-channel MOSFETs, in which the implanted buried-channel profile is approximated by a step profile. Based on the energy-band diagram, the threshold voltage of a buried-channel MOSFET is derived, in which the flatband voltage is physically defined. Using a new charge-sharing scheme, the threshold-voltage model considering the short-channel effect is calculated analytically. Similarly, based on the charge-sharing scheme, the narrow-width effect considering the field implant encroachment under the bird's beak is calculated. Combining both short-channel and narrow-width effects, the threshold-voltage model for small-geometry buried-channel MOSFETs is developed. In order to test the validity of the model, the buried-channel MOSFETs were fabricated in a production line and the threshold voltages were measured. Comparisons between the measured threshold voltage and the present model have been made. It is shown that satisfactory agreement has been obtained for wide ranges of channel lengths, channel widths and applied back-gate biases.     

全耗尽SOI MOSFETs阈值电压和电势分布的温度模型

提出了一个全耗尽SOI MOSFETs器件阈值电压和电势分布的温度模型. 基于近似的抛物线电势分布模型,利用适当的边界条件对二维的泊松方程进行求解. 同时利用阈值电压的定义得到了阈值电压的模型. 该温度模型详细地研究了电势分布和阈值电压跟温度之间的变化关系,同时还近似地探讨了短沟道效应. 为了进一步验证模型的正确性,利用SILVACO ATAS软件进行了相应的模拟. 结果表明,模型计算与软件模拟吻合较好.     

Analysis of temperature dependence of CMOS transistors' threshold voltage

In this paper an investigation of influence of the metal-semiconductor work function difference on the threshold voltage of high-temperature (up to 473 K) operating CMOS transistors, which is often neglected in the literature, is presented. Expressions for temperature dependence of the threshold voltage of both Al-gate and Si-gate CMOS transistors, which take into account the influence of the metal-semiconductor work function difference, are derived starting from the standard expression for the MOS transistor threshold voltage. The temperature coefficient of the threshold voltage is considered in more detail, to provide a simple approximate model for the temperature dependence of the threshold voltage. It is shown that neglecting the temperature dependence of the metal-semiconductor work function difference significantly affects accuracy in prediction of the threshold voltage temperature behavior.     

A self-consistent analytic threshold voltage model for thin SOI n-channel MOSFETs

An accurate analytical threshold voltage model is presented for fully-depleted SOI n-channel MOSFETs having a metal-insulator-semiconductor-insulator-metal structure. The threshold voltage is defined as the gate voltage at which the second derivative of the inversion charge with respect to the gate voltage is maximum. Since the inversion charge is proportional to the drain current at low bias, the model is self-consistent with the measurement scheme when the threshold voltage is measured as the gate voltage at which the variation of the transconductance at low drain bias is maximum. Numerical simulations show good agreement with the model with less than 3% error.     

多层浮栅FET pH传感单元阈值电压敏感模型分析和讨论

Research into new pH sensors fabricated by the standard CMOS process is currently a hot topic. The new pH sensing multi-floating gate field effect transistor is found to have a very large threshold voltage, which is different from the normal ion-sensitive field effect transistor. After analyzing all the interface layers of the structure, a new sensitive model based on the Gauss theorem and the charge neutrality principle is created in this paper. According to the model, the charge trapped on the multi-floating gate during the process and the thickness of the sensitive layer are the main causes of the large threshold voltage. From this model, it is also found that removing the charge on the multi-floating gate is an effective way to decrease the threshold voltage. The test results for three different standard pH buffer solutions show the correctness of the model and point the way to solve the large threshold problem.     

Analytical model for threshold voltage of double gate bilayer graphene field effect transistors

A new model for threshold voltage of double-gate Bilayer Graphene Field Effect Transistors (BLG-FETs) is presented in this paper. The modeling starts with deriving surface potential and the threshold voltage was modeled by calculating the minimum surface potential along the channel. The effect of quantum capacitance was taken into account in the potential distribution model. For the purpose of verification, FlexPDE 3D Poisson solver was employed. Comparison of theoretical and simulation results shows a good agreement. Using the proposed model, the effect of several structural parameters i.e. oxide thickness, quantum capacitance, drain voltage, channel length and doping concentration on the threshold voltage and surface potential was comprehensively studied.     

Semi-empirical model for the threshold voltage of a double implanted MOSFET and its temperature dependence

A simple and accurate semi-empirical model for the threshold voltage of a small geometry double implanted enhancement type MOSFET, especially useful in a circuit simulation program like SPICE, has been developed. The effect of short channel length and narrow width on the threshold voltage has been taken into account through a geometrical approximation, which involves parameters whose values can be determined from the curve fitting experimental data. A model for the temperature dependence of the threshold voltage for the implanted devices has also been presented. The temperature coefficient of the threshold voltage was found to change with decreasing channel length and width. Experimental results from various device sizes, both short and narrow, show very good agreement with the model. The model has been implemented in SPICE as a part of the complete d.c. model.     

应变Si调制掺杂NMOSFET电子面密度模型

应变Si(Strain Si)调制掺杂NMOSFET量子阱沟道中电子面密度直接影响器件的开关特性.本文通过求解泊松方程,建立了应变Si调制掺杂NMOSFET量子阱沟道静态电子面密度模型,并据此建立了器件阈值电压模型,利用MATLAB软件对该模型进行了数值分析.讨论了器件结构中δ-掺杂层杂质浓度和间隔层厚度与电子面密度和阈值电压的关系,分析了器件几何结构参数和材料物理参数对器件量子阱沟道静态电子面密度和阈值电压的影响.随着δ-掺杂层杂质浓度的减小和间隔层厚度的增加,量子阱沟道中电子面密度减小,阈值电压绝对值减小.     

A model for hydrogen-induced piezoelectric effect in InP HEMTs and GaAs PHEMTs

We have developed a model for the impact of the hydrogen-induced piezoelectric effect on the threshold voltage of InP HEMTs and GaAs PHEMTs. We have used two-dimensional (2-D) finite element simulations to calculate the mechanical stress caused by a Ti-containing metal gate that has expanded due to hydrogen absorption. This has allowed us to map the 2-D piezoelectric charge distribution in the semiconductor heterostructure. We then used a simple electrostatics model to calculate the impact of this piezoelectric polarization charge on the threshold voltage. The model explains experimental observations of hydrogen-induced threshold voltage shifts, both in InP HEMTS and in GaAs PHEMTs. It also suggests ways to mitigate the hydrogen sensitivity of these devices.