Binary adders of multigate single-electron transistors: specific design using pass-transistor logic

We describe how to construct area-efficient adders using single-electron transistors (SETs). The design is based on pass-transistor logic and multigate SETs are used as pass transistors. The proposed design enables us to construct a full adder using only six SETs. We also show that multibit binary adders can be built using cascaded SET structures without any long wires. The small number of transistors and no-metal-interconnection configuration significantly reduces the circuit area and capacitance to be charged. A Monte Carlo simulation shows that even when the inter-SET-node capacitances are reduced and consequently the carry signal level terribly fluctuates in its path due to single-electron charging effects, the carry can correctly propagate as long as the final output node capacitance is sufficiently large. This proves that the area reduction and speed improvement are compatible in our design. We also discuss the possibility of large-scale integration, touching on the random-offset-charge issue.     

New adders using hybrid circuit consisting of three-gate single-electron transistors (TG-SETs) and MOSFETs

A half-adder (HA) and a full-adder (FA) using hybrid circuits combining three-gate single-electron transistors (TG-SETs) with metal-oxide-semiconductor field-effect-transistors (MOSFETs) are proposed. The proposed HA consists of three TG-SETs, two enhanced-mode NMOSFETs, and two depletion-mode NMOSFETs, and the proposed FA consists of eight TG-SETs, two enhanced-mode NMOSFETs, and two depletion-mode NMOSFETs. The complexities in the HA and the FA are 7 and 12, respectively, and the worst-case delays in the HA and the FA are 1.48 ns and 2.25 ns, respectively. Compared with the conventional CMOS FA with 0.35 microm technology, the proposed FA can be constructed with 0.43 of devices, and can operate with 3.5 of worst-case delay, 1/534 of average power consumption, and 1/152 of power-delay-product (PDP). The proposed HA and FA can be operated as a half-subtractor (HS) and a full-subtractor (FS) in the case when the levels of the control gates in the HA and the FA are fitly determined. The basic operations of the proposed HA and the proposed FA have been successfully confirmed through SPICE circuit simulation based on the physical device model of TG-SETs.     

Nanowire single-electron memory

We demonstrate storage of electrons in semiconductor nanowires epitaxially grown from Au nanoparticles. The nanowires contain multiple tunnel junctions (MTJs) of InP barriers and InAs quantum dots designed such that the metal seed particles act as storage nodes. By positioning a second nanowire close to the seed particle it is possible to detect tunneling of individual electrons through the MTJ at 4.2 K. A strong memory effect is observed in the detector current when sweeping the writing voltage.     

Sketched oxide single-electron transistor

Devices that confine and process single electrons represent an important scaling limit of electronics. Such devices have been realized in a variety of materials and exhibit remarkable electronic, optical and spintronic properties. Here, we use an atomic force microscope tip to reversibly 'sketch' single-electron transistors by controlling a metal-insulator transition at the interface of two oxides. In these devices, single electrons tunnel resonantly between source and drain electrodes through a conducting oxide island with a diameter of ～1.5 nm. We demonstrate control over the number of electrons on the island using bottom- and side-gate electrodes, and observe hysteresis in electron occupation that is attributed to ferroelectricity within the oxide heterostructure. These single-electron devices may find use as ultradense non-volatile memories, nanoscale hybrid piezoelectric and charge sensors, as well as building blocks in quantum information processing and simulation platforms.     

Operating temperature of single-electron transistors

A modified approach is described to estimate the operating temperature of single-electron transistors which gives calculations in satisfactory agreement with the experimental data. Pis’ma Zh. Tekh. Fiz. 24, 16–19 (April 26, 1998)     

Time-resolved detection of single-electron interference

We demonstrate real-time detection of self-interfering electrons in a double quantum dot embedded in an Aharonov-Bohm interferometer, with visibility approaching unity. We use a quantum point contact as a charge detector to perform time-resolved measurements of single-electron tunneling. With increased bias voltage, the quantum point contact exerts a back-action on the interferometer leading to decoherence. We attribute this to emission of radiation from the quantum point contact, which drives noncoherent electronic transitions in the quantum dots.     

Ultrasonically driven nanomechanical single-electron shuttle

The single-electron transistor is the fastest and most sensitive electrometer available today. Single-electron pumps and turnstiles are also being explored as part of the global effort to redefine the ampere in terms of the fundamental physical constants. However, the possibility of electrons tunnelling coherently through these devices, a phenomenon known as co-tunnelling, imposes a fundamental limit on device performance. It has been predicted that it should be possible to completely suppress co-tunnelling in mechanical versions of the single-electron transistor, which would allow mechanical devices to outperform conventional single-electron transistors in many applications. However, the mechanical devices developed so far are fundamentally limited by unwanted interactions with the electrical mechanisms that are used to excite the devices. Here we show that it is possible to overcome this problem by using ultrasonic waves rather than electrical currents as the excitation mechanism, which we demonstrate at low temperatures. This is a significant step towards the development of high-performance devices.     

Room-temperature single-electron transistors using alkanedithiols

We have fabricated single-electron transistors by alkanedithiol molecular self-assembly. The devices consist of spontaneously formed ultrasmall Au nanoparticles linked by alkanedithiols to nanometer-spaced Au electrodes created by electromigration. The devices reproducibly exhibit addition energies of a few hundred meV, which enables the observation of single-electron tunneling at room temperature. At low temperatures, tunneling through discrete energy levels in the Au nanoparticles is observed, which is accompanied by the excitations of molecular vibrations at large bias voltage.     

Self-assembly of carbon-nanotube-based single-electron memories

We demonstrate the wafer-scale integration of single-electron memories based on carbon nanotube field-effect transistors (CNFETs) using a process based entirely on self assembly. First, a "dry" self-assembly step based on chemical vapor deposition (CVD) allows the growth and connection of CNFETs. Next, a "wet" self-assembly step is used to attach a single 30-nm-diameter gold bead in the nanotube vicinity via chemical functionalization. The bead is used as the memory storage node while the CNFET operating in the subthreshold regime acts as an electrometer exhibiting exponential gain. Below 60 K, the transfer characteristics of gold-CNFETs show highly reproducible hysteretic steps. Evaluation of the capacitance confirms that these current steps originate from the controlled storage of single electrons with a retention time that exceeds 550 s at 4 K.     

Imaging a single-electron quantum dot

Images of a single-electron quantum dot were obtained in the Coulomb blockade regime at liquid He temperatures using a cooled scanning probe microscope (SPM). The charged SPM tip shifts the lowest energy level in the dot and creates a ring in the image corresponding to a peak in the Coulomb-blockade conductance. Fits to the line shape of the ring determine the tip-induced shift of the energy of the electron state in the dot. SPM manipulation of electrons in quantum dots promises to be useful in understanding, building, and manipulating circuits for quantum information processing.     

Single- and double-island ferromagnetic single-electron transistors

Electronic transport in a ferromagnetic single-electron transistor has been considered theoretically in the sequential tunneling regime. The device consists of two external leads and one or two islands as the central part, connected to the leads by tunneling barriers. External gates are additionally attached to the islands. Generally, the two external electrodes and the islands can be ferromagnetic with arbitrary orientation of the corresponding magnetic moments. We have carried out detailed theoretical analysis of the current–voltage characteristics and spin-valve magnetoresistance in the limit of fast spin relaxation on the islands. Asymmetry in tunneling probabilities of spin-majority and spin-minority electrons leads to interesting features in the transport characteristics, like for instance magnetoresistance oscillations with the bias and gate voltages, negative differential resistance, and others.     

CMOS-compatible fabrication of room-temperature single-electron devices

Devices in which the transport and storage of single electrons are systematically controlled could lead to a new generation of nanoscale devices and sensors. The attractive features of these devices include operation at extremely low power, scalability to the sub-nanometre regime and extremely high charge sensitivity. However, the fabrication of single-electron devices requires nanoscale geometrical control, which has limited their fabrication to small numbers of devices at a time, significantly restricting their implementation in practical devices. Here we report the parallel fabrication of single-electron devices, which results in multiple, individually addressable, single-electron devices that operate at room temperature. This was made possible using CMOS fabrication technology and implementing self-alignment of the source and drain electrodes, which are vertically separated by thin dielectric films. We demonstrate clear Coulomb staircase/blockade and Coulomb oscillations at room temperature and also at low temperatures.     

Stable cryogenic vacuum capacitor for single-electron chargingexperiments

For use in our single-electron charging experiment, a novel cryogenic vacuum capacitor has been developed which is superior to the previous parallel-plate design. Due to its coaxial design consisting of a long cylindrical center electrode and a shorter cylindrical ring electrode, it is inherently stable against mechanical vibrations and thermal cycling. Electrical insulation is achieved by the exclusive use of sapphire, which promises extremely low leakage currents     

Fabrication of single-electron transistors using field-emission-induced electromigration

We report a novel technique for the fabrication of planar-type Ni-based single-electron transistors (SETs) using electromigration method induced by field emission current. The method is so-called "activation" and is demonstrated using arrow-shaped Ni nanogap electrodes with initial gap separations of 21-68 nm. Using the activation method, we are easily able to obtain the SETs by Fowler-Nordheim (F-N) field emission current passing through the nanogap electrodes. The F-N field emission current plays an important role in triggering the migration of Ni atoms. The nanogap is narrowed because of the transfer of Ni atoms from source to drain electrode. In the activation procedure, we defined the magnitude of a preset current Is and monitored the current I between the nanogap electrodes by applying voltage V. When the current I reached a preset current Is, we stopped the voltage V. As a result, the tunnel resistance of the nanogaps was decreased from the order of 100 T(omega) to 100 k(omega) with increasing the preset current Is from 1 nA to 150 microA. Especially, the devices formed by the activation with the preset current from 100 nA to 1.5 microA exhibited Coulomb blockade phenomena at room temperature. Coulomb blockade voltage of the devices was clearly modulated by the gate voltage quasi-periodically, resulting in the formation of multiple tunnel junctions of the SETs at room temperature. By increasing the preset current from 100 nA to 1.5 microA in the activation scheme, the charging energy of the SETs at room temperature was decreased, ranging from 1030 meV to 320 meV. Therefore, it is found that the charging energy and the number of islands of the SETs are controllable by the preset current during the activation. These results clearly imply that the activation procedure allows us to easily and simply fabricate planar-type Ni-based SETs operating at room temperature.     

Integration of single-electron transistors using field-emission-induced electromigration

A novel technique for the integration of planar-type single-electron transistors (SETs) composed of nanogaps is presented. This technique is based on the electromigration procedure, which is caused by a field emission current. The technique is called "activation." By applying the activation to the nanogaps, SETs can be easily obtained. Furthermore, the charging energy of the SETs can be controlled by adjusting the magnitude of the applied current during the activation process. The integration of two SETs was achieved by passing a field emission current through two series-connected initial nanogaps. The current-voltage (I(D)-V(D)) curves of the simultaneously activated devices exhibited clear electrical-current suppression at a low-bias voltage at 16 K, which is known as the Coulomb blockade. The Coulomb blockade voltage of each device was also obviously modulated by the gate voltage. In addition, the two SETs, which were integrated by the activation procedure, exhibited similar electrical properties, and their charging energy decreased uniformly with increasing the preset current during the activation. These results indicate that the activation procedure allows the simple and easy integration of planar-type SETs.     

A majority-logic device using an irreversible single-electron box

We describe a majority-logic gate device suitable for use in developing single-electron integrated circuits. The device consists of a capacitor array for input summation and an irreversible single-electron box for threshold operation. It accepts three binary inputs and produces a corresponding output, a complementary majority-logic output, by using the change in its tunneling threshold caused by the input signals; it produces a logical 1 output if two or three of the inputs are logical 0 and a logical 0 output if two or three of the inputs are logical 1. We combined several of these gate devices to form subsystems, a shift register and a full adder, and confirmed their operation by computer simulation. The gate device is simple in structure and powerful in terms of implementing digital functions with a small number of devices. These superior features will enable the device to contribute to the development of single-electron integrated circuits.     

A low-voltage and energy-efficient full adder cell based on carbon nanotube technology

Nano-Micro Letters - Scaling problems and limitations of conventional silicon transistors have led the designers to exploit novel nano-technologies. One of the most promising and feasible...     

Diffusion-based electron thermometry using a three-junction single-electron transistor

We describe a new mK-range nanoscale thermometer, based on a unique three-junction radio frequency single-electron transistor. The three-junction geometry allows separation of the thermal and electronic pathways, providing a potentially significant reduction of measurement-induced Joule heating. A radio frequency embedding tank circuit allows very fast readout. We demonstrate electronic and thermal operation, supported by numerical simulations. Applications to minimal back-action calorimetry and bolometry are discussed.     

Low energy 16-bit Booth leapfrog array multiplier using dynamic adders

The paper presents a low-voltage (1-1.5 V) 16-bit Booth leapfrog array multiplier with emphasis on low energy dissipation, relatively high speed and small IC area. These attributes are achieved in two ways. First, low (hardware) complexity dynamic adders (DAs) are proposed and they are used to reduce spurious switching in the multiplier. Second, the specificities of the leapfrog architecture are exploited with the use of different output rates of the sum and carry outputs of the proposed DAs. When compared with other array multiplier designs, the proposed multiplier features the lowest energy dissipation and one of the shortest delays, resulting in the lowest energy-delay product. Furthermore, when compared with the reported dynamic array multiplier that features somewhat similar electrical characteristics, the proposed multiplier is advantageous in its substantially smaller (~33%) IC area. Based on a 0.35 mum dual-poly four-metal CMOS process and at 1 V operation, the proposed multiplier dissipates ~18 pJ, has a delay of ~188 ns and occupies 0.11 mm² of IC area. The proposed design is appropriate for low-voltage energy-critical and IC area-critical applications including hearing aids