A low power high gain UWB LNA in 0.18-μm CMOS

A low power high gain differential UWB low noise amplifier (LNA) operating at 3-5 GHz is presented.A common gate input stage is used for wideband input matching; capacitor cross coupling (CCC) and current reuse techniques are combined to achieve high gain under low power consumption. The prototypes fabricated in 0.18-μm CMOS achieve a peak power gain of 17.5 dB with a -3 dB bandwidth of 2.8-5 GHz, a measured minimum noise figure (NF) of 3.35 dB and -12.6 dBm input-referred compression point at 5 GHz, while drawing 4.4 mA from a 1.8 V supply. The peak power gain is 14 dB under a 4.5 mW power consumption (3 mA from a 1.5 V supply). The proposed differential LNA occupies an area of 1.01 mm~2 including test pads.     

Design of a Sub-mW 960-MHz UWB CMOS LNA

This paper presents a sub-mW ultra-wideband (UWB) fully differential CMOS low-noise amplifier (LNA) operating below 960 MHz for sensor network applications. By utilizing both nMOS and pMOS transistors to boost the transconductance, coupling the input signals to the back-gates of the transistors, and combining the common-gate and shunt-feedback topologies, the LNA achieves 13 dB of power gain, a 3.6 dB minimum noise figure, and -10 dBm of IIP3 with only 0.72 mW of power consumption from a 1.2 V supply     

Design of a fully differential CMOS LNA for 3.1-10.6 GHz UWB communication systems

A fully differential complementary metal oxide semiconductor （CMOS） low noise amplifier （LNA） for 3.1-10.6 GHz ultra-wideband （UWB） communication systems is presented. The LNA adopts capacitive cross-coupling common-gate （CG） topology to achieve wideband input matching and low noise figure （NF）. Inductive series-peaking is used for the LNA to obtain broadband flat gain in the whole 3.1-10.6 GHz band. Designed in 0.18 um CMOS technology, the LNA achieves an NF of 3.1-4.7 dB, an Sll of less than -10 dB, an S21 of 10.3 dB with ±0.4 dB fluctuation, and an input 3rd interception point （IIP3） of -5.1 dBm, while the current consumption is only 4.8 mA from a 1.8 V power supply. The chip area of the LNA is 1×0.94 mm^2.     

3．1～10．6GHz超宽带低噪声放大器的设计

基于SIMC0．18μmRFCMOS工艺技术,设计了可用于3．1—10．6GHzMB—OFDM超宽带接收机射频前端的CMOS低噪声放大器（LNA）。该LNA采用三级结构：第一级是共栅放大器,主要用来进行输入端的匹配;第二级是共源共栅放大器,用来在低频段提供较高的增益;第三级依然为共源共栅结构,用来在高频段提供较高的增益,从而补偿整个频带的增益使得增益平坦度更好。仿真结果表明：在电源电压为1．8v的条件下,所设计的LNA在3．1～10．6GHz的频带范围内增益（521）为20dB左右,具有很好的增益平坦性f±0．4dB）,回波损耗S11、S22均小于-10dB,噪声系数为4．5dB左右,IIP3为-5dBm,PIdB为0dBm。     

A novel CMOS low-noise amplifier design for 3.1- to 10.6-GHz ultra-wide-band wireless receivers

An ultra-wideband (UWB) 3.1- to 10.6-GHz low-noise amplifier (LNA) employing a common-gate stage for wideband input matching is presented in this paper. Designed in a commercial 0.18-/spl mu/m 1.8-V standard RFCMOS technology, the proposed UWB LNA achieves fully on-chip circuit implementation, contributing to the realization of a single-chip CMOS UWB receiver. The proposed UWB LNA achieves 16.7/spl plusmn/0.8 dB power gain with a good input match (S11<-9 dB) over the 7500-MHz bandwidth (from 3.1 GHz to 10.6 GHz), and an average noise figure of 4.0 dB, while drawing 18.4-mA dc biasing current from the 1.8-V power supply. A gain control mechanism is also introduced for the first time in the proposed design by varying the biasing current of the gain stage without influencing the other figures of merit of the circuit so as to accommodate the UWB LNA in various UWB wireless transmission systems with different link budgets.     

2～12 GHz CMOS超宽带低噪声放大器设计

提出了一种基于双反馈电流复用结构的新型CMOS超宽带(UWB)低噪声放大器(LNA),放大器工作在2～12 GHz的超宽带频段,详细分析了输入输出匹配、增益和噪声系数的性能。设计采用TSMC 0.18μm RF CMOS工艺,在1.4 V工作电压下,放大器的直流功耗约为13mW(包括缓冲级)。仿真结果表明,在2～12 GHz频带范围内,功率增益为15.6±1.4 dB,输入、输出回波损耗分别低于-10.4和-11.5 dB,噪声系数(NF)低于3 dB(最小值为1.96 dB),三阶交调点IIP3为-12 dBm,芯片版图面积约为712μm×614μm。     

宽带CMOS低噪声放大器的设计

文章主要介绍应用于集群接收机系统的350MHz～470MHz低噪声放大器,采用0.6μm CMOS工艺。探讨了优化低噪声放大器的噪声系数、增益与线性度的设计方法,同时对宽带输入输出匹配进行了分析。这种宽带低噪声放大器的工作带宽350MHz～470MHz,噪声系数小于3dB,增益为24dB,增益平坦度为±1dB,输入1dB压缩点大于-15dBm。     

A 0.18μm CMOS 3-5 GHz broadband flat gain low noise amplifier

A 3-5 GHz broadband flat gain differential low noise amplifier (LNA) is designed for the impulse radio uitra-wideband (IR-UWB) system. The gain-flatten technique is adopted in this UWB LNA. Serial and shunt peaking techniques are used to achieve broadband input matching and large gain-bandwidth product (GBW). Feedback networks are introduced to further extend the bandwidth and diminish the gain fluctuations. The prototype is fabricated in the SMIC 0.18 μm RF CMOS process. Measurement results show a 3-dB gain bandwidth of 2.4-5.5 GHz with a maximum power gain of 13.2 dB. The excellent gain flatness is achieved with ±0.45 dB gain fluctuations across 3-5 GHz and the minimum noise figure (NF) is 3.2 dB over 2.5-5 GHz. This circuit also shows an excellent input matching characteristic with the measured S11 below-13 dB over 2.9-5.4 GHz. The input-referred 1-dB compression point (IPldB) is -11.7 dBm at 5 GHz. The differential circuit consumes 9.6 mA current from a supply of 1.8 V.     

High linearity technique for ultra-wideband low noise amplifier in 0.18 μm CMOS technology

A linearization technique for ultra-wideband low noise amplifier (UWB LNA) has been designed and fabricated in standard 0.18 μm CMOS technology. The proposed technique exploits the complementary characteristics of NMOS and PMOS to improve the linearity performance. A two-stage UWB LNA is optimized to achieve high linearity over the 3.1-10.6 GHz range. The first stage adopts inverter topology with resistive feedback to provide high linearity and wideband input matching, whereas the second stage is a cascode amplifier with series and shunt inductive peaking techniques to extend the bandwidth and achieve high gain simultaneously. The proposed UWB LNA exhibits a measured flat gain of 15 dB within the entire band, a minimum noise figure of 3.5 dB, and an IIP3 of 6.4 dBm while consuming 8 mA from a 1.8 V power supply. The total chip area is 0.39 mm², including all pads. The measured input return loss is kept below −11 dB, and the output return loss is −8 dB, from 3.1 to 10.6 GHz.     

A Compact Wideband CMOS Low-Noise Amplifier Using Shunt Resistive-Feedback and Series Inductive-Peaking Techniques

A wideband low-noise amplifier (LNA) with shunt resistive-feedback and series inductive-peaking is proposed for wideband input matching, broadband power gain and flat noise figure (NF) response. The proposed wideband LNA is implemented in 0.18-mum CMOS technology. Measured results show that power gain is greater than 10 dB and input return loss is below -10 dB from 2 to 11.5 GHz. The IIP3 is about +3 dBm, and the NF ranges from 3.1 to 4.1 dB over the band of interest. An excellent agreement between the simulated and measured results is found and attributed to less number of passive components needed in this circuit compared with previous designs. Besides, the ratio of figure-of- merit to chip size is as high as 190 (mW^-1 /mm² ) which is the best results among all previous reported CMOS-based wideband LNA.     

A High Dynamic Range CMOS Variable Gain Amplifier for Mobile DTV Tuner

A high dynamic range RF variable gain amplifier (RFVGA) suitable for mobile digital television (DTV) tuners is presented. Variable gain is achieved using a capacitive attenuator and current-steering transconductance (G_m) stages, which provide high linearity with relatively low power consumption. A novel broadband input impedance matching scheme based on resistive shunt-feedback is proposed. This scheme allows the RFVGA to achieve a low noise figure. A gain control technique suitable for CMOS current-steering variable gain amplifiers is described; it features 1 dB per step resolution, independent of process and temperature variations. The chip is fabricated in six-metal 0.18mum CMOS technology and consumes 12.2mA current from 1.8V supply. The RFVGA achieves 16dB maximum gain, 33dB gain control range, a 4.3dB noise figure, and an IIP3 higher than 25dBm     

A wideband CMOS VGLNA based on single-to-differential stage and resistive attenuator for TV tuners

A wideband CMOS variable gain low noise amplifier(VGLNA) based on a single-to-differential(S2D) stage and resistive attenuator is presented for TV tuner applications.Detailed analysis of input matching,noise figure(NF) and linearity for S2D is given.A highly linear passive resistive attenuator is proposed to provide 6 dB attenuation and input matching for each gain stage.The chip was fabricated by a 0.18μm 1P6M CMOS process, and the measurements show that the VGLNA covers a gain range over 36.4 dB and achieves a maximum gain of 21.3 dB,a minimum NF of 3.0 dB,an IIP3 of 0.9 dBm and an IIP2 of 26.3 dBm at high gain mode with a power consumption less than 10 mA from a 1.8 V supply.     

High‐Gain Wideband CMOS Low Noise Amplifier with Two‐Stage Cascode and Simplified Chebyshev Filter

An ultra‐wideband low‐noise amplifier is proposed with operation up to 8.2 GHz. The amplifier is fabricated with a 0.18‐μm CMOS process and adopts a two‐stage cascode architecture and a simplified Chebyshev filter for high gain, wide band, input‐impedance matching, and low noise. The gain of 19.2 dB and minimum noise figure of 3.3 dB are measured over 3.4 to 8.2 GHz while consuming 17.3 mW of power. The Proposed UWB LNA achieves a measured power‐gain bandwidth product of 399.4 GHz.     

A 0.18μm CMOS low noise amplifier using a current reuse technique for 3.1-10.6 GHz UWB receivers

A new,low complexity,ultra-wideband 3.1-10.6 GHz low noise amplifier(LNA),designed in a chartered 0.18μm RFCMOS technology,is presented.The ultra-wideband LNA consists of only two simple amplifiers with an inter-stage inductor connected.The first stage utilizing a resistive current reuse and dual inductive degeneration technique is used to attain a wideband input matching and low noise figure.A common source amplifier with an inductive peaking technique as the second stage achieves high flat gain and wide -3 dB bandwidth of the overall amplifier simultaneously.The implemented ultra-wideband LNA presents a maximum power gain of 15.6 dB,and a high reverse isolation of—45 dB,and good input/output return losses are better than -10 dB in the frequency range of 3.1-10.6 GHz.An excellent noise figure(NF) of 2.8-4.7 dB was obtained in the required band with a power dissipation of 14.1 mW under a supply voltage of 1.5 V.An input-referred third-order intercept point(IIP3) is -7.1 dBm at 6 GHz.The chip area,including testing pads,is only 0.8×0.9 mm2.     

Ultra-wideband CMOS low noise amplifier

A two-stage ultra-wideband CMOS low noise amplifier (LNA) is proposed. The first stage is optimised for wideband input matching and low noise figure, while the second stage is optimised to extend the -3 dB bandwidth of the overall amplifier. The combination of stages can provide lower noise figure and wider bandwidth simultaneously over that of previously reported feedback-based CMOS amplifiers. The implemented LNA shows a peak gain of 13.5 dB, more than 8.5 dB of input return loss, and a noise figure of 2.5-7.4 dB over a -3 dB bandwidth from 2 to 9 GHz with DC power consumption of 25.2 mW.     

A 2.7-V 900-MHz CMOS LNA and mixer

A CMOS low-noise amplifier (LNA) and a mixer for RF front-end applications are described. A current reuse technique is described that increases amplifier transconductance for the LNA and mixer without increasing power dissipation, compared to standard topologies. At 900 MHz, the LNA minimum noise figure (NF) is 1.9 dB, input third-order intercept point (IIP3) is -3.2 dBm and forward gain is 15.6 dB. With a 1-GHz local oscillator (LO) and a 900-MHz RF input, the mixer minimum double sideband noise figure (DSB NF) is 5.8 dB, IIP3 is -4.1 dBm, and power conversion gain is 8.8 dB. The LNA and mixer, respectively, consume 20 mW and 7 mW from a 2.7 V power supply. The active areas of the LNA and mixer are 0.7 mm×0.4 mm and 0.7 mm×0.2 mm, respectively. The prototypes were fabricated in a 0.5-μm CMOS process     

0.13微米CMOS双通道超宽带低噪声放大器设计

本文设计了一款超宽带低噪声放大器,并对设计流程进行分析仿真.该低噪放采用双通道结构,有效的输入阻抗匹配、平稳的增益和低噪声等性能可以同时实现.应用ADS工具TSMC 0.13μm CMOS工艺库的仿真结果表明,其最大功率增益为14.2dB,在8GHz频点的IIP3为-4dBm,输入、输出反射系数分别小于-10.2dB和-10.89dB,噪声指数单调下降到1.46dB,并且总功耗和带内最大增益摆幅较低.     

A low supply voltage SiGe LNA for ultra-wideband frontends

A low-power low-noise amplifier (LNA) for ultra-wideband (UWB) radio systems is presented. The microwave monolithic integrated circuit (MMIC) has been fabricated using a commercial 0.25-/spl mu/m silicon-germanium (SiGe) bipolar CMOS (BiCMOS) technology. The amplifier uses peaking and feedback techniques to optimize its gain, bandwidth and impedance matching. It operates from 3.4 to 6.9GHz, which corresponds with the low end of the available UWB radio spectrum. The LNA has a peak gain of 10dB and a noise figure less than 5dB over the entire bandwidth. The circuit consumes only 3.5mW using a 1-V supply voltage. A figure of merit (FoM) for LNAs considering bandwidth, gain, noise, power consumption, and technology is proposed. The realized LNA circuit is compared with other recently published low-power LNA designs and shows the highest reported FoM.     

A sub-1-dB NF±2.3-kV ESD-protected 900-MHz CMOS LNA

A sub-1-dB noise figure HBM ESD-protected [-3 kV, 2.3 kV] low noise amplifier (LNA) has been integrated in a 0.35-μm RF CMOS process with on-chip inductors. The sensitivity of the LNA performances to the spread of parasitics associated with package and bondwire has been attenuated by using an inductive on-chip source degeneration. At 920 MHz and P_dc=8.6 mW, the LNA features: noise figure NF=1 dB, input return loss=-8.5 dB, output return loss=-27 dB, power gain G _p=13 dB, input IIP3=-1.5 dBm. At a power dissipation of 5 mW and 17.6 mW, a NF respectively equal to 1.2 dB and 0.85 dB is measured. The CMOS LNA takes 12 pins of a TQFP48 package, an area of 1.0×0.66 mm² (bondwire pads excluded) and it is the first HBM ESD-protected [-3 kV, 2.3 kV] CMOS LNA to break the 1-dB NF barrier     

Low-power and low NF V-band down-converter in 0.13 μm CMOS

A V-band down-converter integrating a LNA and mixer in 0.13 mm CMOS technology is presented. The LNA has a current re-use topology for low power consumption. The transistor size of the LNA is optimised by the substrate noise for the low noise figure (NF) and f_max for high gain performance. The new resistive mixer for low LO power operation is proposed. The NF of the down-converter is 4.7 dB. The conversion gain and input P_1dB are 0.67 dB and 212.5 dBm, respectively. The proposed circuit, consuming only 11.6 mW, shows the lowest NF and highest linearity among V-band down-converters.