利用ISSG退火技术实现沉积二氧化硅薄膜平坦化

利用现场水汽生成(in-situ steam generation,ISSG)退火这种新型的低压快速氧化热退火技术,在对沉积二氧化硅薄膜热退火的同时进行补偿氧化生长,最终实现了沉积二氧化硅薄膜的平坦化.实验数据表明,ISSG退火补偿生长后整个晶圆表面的薄膜厚度波动(最大值与最小值之差)从0.76nm降到了0.16nm,49点厚度值的标准偏差从0.25nm降到了0.04nm.同时,薄膜的隧穿场强增加到4.3MV/cm,硅氧界面与传统的氧气快速退火工艺相比更为良好.实验结果为二氧化硅薄膜平坦化提供了新的思路,对实际生产具有重要意义.     

利用ISSG退火技术实现沉积二氧化硅薄膜平坦化

利用现场水汽生成(in-situ steam generation,ISSG)退火这种新型的低压快速氧化热退火技术,在对沉积二氧化硅薄膜热退火的同时进行补偿氧化生长,最终实现了沉积二氧化硅薄膜的平坦化.实验数据表明,ISSG退火补偿生长后整个晶圆表面的薄膜厚度波动(最大值与最小值之差)从0.76nm降到了0.16nm,49点厚度值的标准偏差从0.25nm降到了0.04nm.同时,薄膜的隧穿场强增加到4.3MV/cm,硅氧界面与传统的氧气快速退火工艺相比更为良好.实验结果为二氧化硅薄膜平坦化提供了新的思路,对实际生产具有重要意义.     

PEALD制备的Al2O3薄膜在n-TOPCon太阳电池上的钝化性能

对采用等离子体增强原子层沉积(PEALD)法制备的Al2O3薄膜在n型单晶硅隧穿氧化层钝化接触(TOPCon)太阳电池正表面的钝化性能进行了研究.采用少数载流子寿命、X射线电子能谱(XPS)及J-V特性的测试分析,重点研究了 Al2O3沉积温度、薄膜厚度及薄膜形成后不同退火条件对钝化性能的影响,实现了低表面复合速率、良好钝化效果的产业化制备的Al2O3薄膜工艺.研究结果表明,在沉积温度为150℃、膜厚为5 nm、退火温度为450℃时,测试计算得出薄膜中O和Al的原子数之比为2.08,电池发射极正表面复合速率较低,达到了Al2O3钝化的最优效果,并且分析了 Al2O3薄膜的化学态和形成机理.利用其Al2O3薄膜工艺制备的n型单晶硅TOPCon太阳电池开路电压提升了 8 mV,电池的平均光电转换效率达到了 23.30％.     

VO2(B)薄膜的制备及特性优化研究

采用直流磁控溅射法,在纯氩气氛中溅射V2O5靶材,在覆盖有氮化硅薄膜的P(100)硅基片表面沉积氧化钒薄膜.对沉积的薄膜进行了后续高真空高温退火处理.利用XRD对薄膜的晶相进行了分析,结果表明退火处理前和退火处理后的薄膜都具有VO2各晶面的取向,XPS分析证明了XRD的物相分析结果.对薄膜的方阻特性的测试表明生成的薄膜是典型的VO2(B)薄膜,退火后的薄膜方阻减小,方阻温度系数也降低.在此基础上,利用薄膜晶界散射理论,通过改变薄膜沉积时间和沉积温度使薄膜的方阻和方阻温度系数随薄膜厚度和晶粒大小而变化,从而使薄膜的电性能达到优化.     

适用于非制冷焦平面探测器的氧化钒薄膜制备研究

氧化钒薄膜由于其具有高电阻温度系数(TCR),近年来被广泛应用于非制冷红外探测器.利用离子束增强沉积法,通过精确控制溅射电压、退火温度优化了氧化钒的制备工艺,制备出的氧化钒薄膜电阻为40kΩ、TCR为-2.5%K-1,满足非制冷焦平面探测器氧化钒薄膜的应用的要求.     

镶嵌在超薄SiO2层中的纳米硅的库仑阻塞现象

采用等离子体氧化和逐层(layer by layer)生长技术在等离子体增强化学气相沉积 (PECVD)系统中原位制备了SiO2/nc-Si/SiO2的双势垒纳米结构,从nc-Si薄膜的喇曼谱中观察到结晶峰,估算出该薄膜的晶化成分和平均晶粒尺寸分别约为65%和6nm.通过对该纳米结构的电容-电压(C-V)测量,研究了载流子的隧穿和库仑阻塞特性.在不同测试频率的C-V谱中观测到了由于载流子隧穿引起的最大电容值抬升现象.通过低温低频C-V谱,计算出该结构中nc-Si的库仑荷电能为57meV.     

退火温度对ZrO_2高介电薄膜电学性能的影响

利用反应磁控溅射法沉积了ZrO2介电薄膜,研究了退火温度对ZrO2介电薄膜电学性能的影响,并对漏电流最小的样品的漏电流机制进行了分析。结果表明,随着退火温度的升高,漏电流先减小后增大,退火温度为300℃时所制备薄膜的漏电流最小,当所加电压为–1.4 V时,漏电流密度为8.32×10–4 A/cm2。当所加正偏压为0-0.8 V和0.8-4.0 V时,该样品的漏电流主导机制分别为肖特基发射和直接隧穿电流;当所加负偏压为–1.7-0 V和–4.0-–1.7 V时,其主导机制分别为肖特基发射和空间电荷限制电流。     

氩氧比与退火温度对磁控溅射VO2薄膜结构与电学性能的影响

采用反应直流磁控溅射法,通过调控溅射过程中的氩氧比,在石英玻璃衬底上制备了氧化钒薄膜,研究了溅射气氛及后处理条件对其微结构与电学性能的影响.经450和500℃退火,薄膜中易形成VO2,而550℃退火时薄膜中会形成大量非4价的钒氧化物.薄膜在较高温度500℃下退火时结晶度增加,但薄膜颗粒之间的间隙更为明显,导致电阻率显著提高;同时其电阻率-温度曲线的热滞回线宽度较窄,在加热过程中相转变温度较高.当氩氧比中氧含量增加时,沉积的VO2薄膜中生成了少量非4价的钒氧化物.结果表明,反应磁控溅射法制备的氧化钒薄膜的微结构、电阻率、相变温度等特性与氩氧比和后退火温度密切相关.     

低温沉积ZnO薄膜的压敏特性及其热处理影响

采用GDARE法在较低温度下,通过一次和多次沉积制备单层及多层ZnO薄膜.AFM和XRD分析表明,薄膜具有以ZnO(002)晶面取向为主的多晶结构,多层膜的晶粒尺寸增大.经200～300℃退火热处理,薄膜呈现出良好的低压压敏特性.经200℃退火热处理后,多层ZnO薄膜的非线性系数达到61.54,压敏电压20.10V.在一定范围内升高热处理温度,可明显降低压敏电压.分析了不同膜层及热处理温度对ZnO薄膜压敏特性的影响机理.     

低温沉积ZnO薄膜的压敏特性及其热处理影响

采用GDARE法在较低温度下,通过一次和多次沉积制备单层及多层ZnO薄膜.AFM和XRD分析表明,薄膜具有以ZnO(002)晶面取向为主的多晶结构,多层膜的晶粒尺寸增大.经200～300℃退火热处理,薄膜呈现出良好的低压压敏特性.经200℃退火热处理后,多层ZnO薄膜的非线性系数达到61.54,压敏电压20.10V.在一定范围内升高热处理温度,可明显降低压敏电压.分析了不同膜层及热处理温度对ZnO薄膜压敏特性的影响机理.     

Effects of nitric oxide annealing of thermally grown silicondioxide characteristics

The effects of nitric oxide (NO) annealing on conventional thermal oxides are reported in this letter. The oxide thickness increase, resulting from NO annealing, is found to be only a few angstroms (<0.5 nm) and independent on the initial oxide thickness. Furthermore, both the electrical and physical characteristics are improved. This technique is expected to achieve sub-5 nm high quality ultrathin dielectric films for the applications in EEPROM's and ULSI     

Decrease of gate oxide dielectric constant in tungsten polycidegate processes

The gate oxide thickness for tungsten (W) polycide gate processes is studied, with tungsten silicide (WSi_x) deposited either by chemical vapor deposition (CVD) or sputtering. For WSi_x deposited by CVD, it is found that the effective thickness of gate oxide as determined by CV measurement increases in all cases if the annealing temperature is 900°C or higher. However, high-resolution transmission electron microscopy (TEM) measurement indicates that the physical thickness does not change after a 900°C anneal. In this case, the dielectric constant of the gate oxide decreases by 7%. As the annealing temperature increases to 1000°C, CV and TEM measurements give the same thickness and the decrease of the dielectric constant disappears. In contrast, for WSi_x film deposited by sputtering, annealing at 900°C has no effect on the gate oxide thickness as measured by CV and TEM     

Slight gate oxide thickness increase in PMOS devices with BF2 implanted polysilicon gate

The gate oxide thickness increase in PMOSFET devices with BF₂ implanted p⁺ polysilicon gate is observed even when rapid thermal annealing (RTA) is used as a dopant activation thermal process. The increase of oxide thickness is studied as a function of RTA temperature, RTA time, and initial oxide thickness in the 35 Å regime and is being reported for the first time. It was found that oxide thickness increase could be as significant as 7% in this regime. This phenomenon can be explained by the model of fluorine incorporation, which is found to he effectively suppressed with nitrogen implanted in the polysilicon     

HfTiO高κ栅介质Ge MOS电容特性研究

采用反应磁控共溅射方法在Ge衬底上制备亚-nm等效氧化物厚度(EOT)的HfTiO高κ栅介质薄膜,研究了湿N2和干N2气氛退火对GeMOS电容电特性的影响。隧穿电子显微镜、椭偏仪、X射线光电子频谱、原子力显微镜以及电特性的测量结果分别表明,与干N2退火比较,湿N2退火能明显抑制不稳定的低κGeOx界面层的生长,从而减小栅介质厚度,降低栅介质表面粗糙度,有效提高介电常数,改善界面质量和栅极漏电流特性,这都归因于GeOx的易水解性。还研究了Ti靶溅射功率对HfTiO栅介质GeMOS器件性能的影响。     

Models of the formation of oxide phases in nanostructured materials based on lead chalcogenides subjected to treatment in oxygen and iodine vapors

Model concepts concerning control over the formation of oxide layers during the course of oxidation are developed on the basis of experimental results of studies of systematic features of the formation of nanostructured layers after diffusion annealing. Data on a variation in the composition of oxide phases as the extent of deviation from stoichiometry is changed in the initial lead chalcogenide are presented. Model concepts related to the possibility of varying the thickness of the coating oxide phases using annealing in an oxygen-containing medium are developed. It is shown that annealing in an iodine atmosphere ensures the effective penetration of oxygen into the grains, which is necessary for an increase in the photoluminescence efficiency.     

Ar Annealing for Suppression of Gate Oxide Thinning at Shallow Trench Isolation Edge

We investigated the effects of high-temperature N₂ and Ar annealing after sacrificial oxidation on the rounding of the top corners in shallow trench isolation (STI). With the N₂ and Ar annealing, the corners were rounded, and the gate oxide thinning was suppressed, indicating that high-temperature annealing in an inert gas ambient is effective for rounding the corners and increasing the gate oxide thickness. With the N₂ annealing, however, the hump in the I_d-V_g curve increased, and the time-dependent dielectric breakdown (TDDB) characteristics were degraded. The possible reason is that the suppression of gate oxidation and/or the oxide quality change occurs at the local spots at the top corners due to the introduction of nitrogen. With the Ar annealing, there was no hump, and the TDDB characteristics improved. It is presumed that the Ar did not accumulate at the sacrificial oxide/substrate interface. Therefore, Ar annealing after gap filling is promising in improving the performance and reliability of transistors with STI.     

Measurement and modeling of the annealing kinetics of stress induced leakage current in ultra-thin oxides

The annealing properties of the stress induced leakage current (SILC) for 55 and 65 Åthick oxides are investigated. It is demonstrated that the SILC is a fully reversible degradation process and that its generation kinetics are nearly unchanged after successive stressing/annealing cycles. The activation energy and diffusion coefficient of the annealing process has been extracted and shown to be independent of oxide thickness. Moreover the annealing kinetics are quantitatively simulated using a drift-diffusion model with the experimentally extracted parameters.     

Characteristics of HfO/sub 2/ pMOSFET prepared by B/sub 2/H/sub 6/ plasma doping and KrF excimer laser annealing

The electrical characteristics of HfO/sub 2/ pMOSFETs prepared by B/sub 2/H/sub 6/ plasma doping and excimer laser annealing were investigated. Various metal gate electrodes were evaluated to protect the high-/spl kappa/ oxide during laser irradiation. Although the aluminum gate electrode showed superior reflectivity to the laser, the equivalent oxide thickness was increased due to the interaction between aluminum and HfO/sub 2/, which resulted in reduced capacitance. In contrast, the Al-TaN stacked gate showed good reflectivity up to laser energy of 500 mJ/cm/sup 2/ and improved capacitance was obtained compared with the Al gate. For the first time, the electrical characteristics of a HfO/sub 2/ pMOSFET with an Al-TaN gate fabricated by plasma doping and excimer laser annealing were demonstrated. It was also demonstrated that plasma doping and excimer laser annealing combined with a metal gate could be applied for high-/spl kappa/ oxide MOSFET fabrication.