氧等离子体处理条件对poly-SiO2/Si结构平带电压的影响

氧等离子体处理高阻P型、〈100〉硅片上的聚硅烷涂层,制备了SiO2/Si结构.用C-V技术测量其MOS结构平带电压,结果表明平带电压随氧等离子体处理时间、反应室气压和射频功率等条件的改变而变化.平带电压最小可达-0.55～-0.88V,比同一环境热氧化法制备的SiO2/Si结构平带电压小得多.     

LiNbO3/SiO2/Si薄膜的蓝光发射

采用射频磁控溅射方法制备了LiNbO3/SiO2/Si薄膜.通过X射线衍射(XRD)、电感耦合等离子体质谱(ICP-MS)和傅立叶变换红外吸收光谱(FT-IR)对薄膜的物相、晶体取向和成分进行了表征.采用荧光分光光度计研究了LiNbO3/SiO2/Si薄膜的光致发光.研究结果表明:在280 nm激发光的激发下,LiNbO3/SiO2/Si薄膜在室温下发射470 nm的蓝光,来源于LiNbO3薄膜与SiO2层界面处自捕获激子的辐射复合,发现在SiO2/Si薄膜上生长LiNbO3薄膜调制SiO2/Si薄膜的发光机制.     

厚二氧化硅光波导薄膜的制备

随着光通信的飞速发展，Si基SiO2平面光波导集成器件的应用更加重要和广泛。在Si基上制备高质量的厚SiO2薄膜，是制作SiO2光波导及其集成器件的基础。本文介绍了Si基厚SiO2薄膜的几种制备方法。     

在SiO2中掺A1对Au／纳米（SiO2／Si／SiO2）／p—Si结构电致发光的影响

利用射频磁控溅射方法,制成纳米SiO2层厚度一定而纳米Si层厚度不同的纳米（SiO2/Si/SiO2）/p-Si结构和纳米（SiO2:A1/Si/SiO2:A1)/p-Si结构,用磁控溅射制备纳米SiO2:A1时所用的SiO2/A1复合靶中的A1的面积百分比为1%。上述两种结构中Si层厚度均为1-3nm,间隔为0.2nm。为了对比研究,还制备了Si层厚度为零的样品。这两种结构在900℃氮气下退火30min,正面蒸半透明Au膜,背面蒸A1作欧姆接触后,都在正向偏置下观察到电致发光（EL）。在一定的正向偏置下,EL强度和峰位以及电流都随Si层厚度的增加而同步振荡,位相相同。但掺A1结构的发光强度普遍比不掺A1结构强。另外,这两种结构的EL具体振荡特性有明显不同,对这两种结构的电致发光的物理机制和SiO2中掺A1的作用进行了分析和讨论。     

LiNbO_3/SiO_2/Si薄膜的蓝光发射

采用射频磁控溅射方法制备了LiNbO3/SiO2／Si薄膜。通过X射线衍射（XRD）、电感耦合等离子体质谱（ICP-MS）和傅立叶变换红外吸收光谱（FT-IR）对薄膜的物相、晶体取向和成分进行了表征。采用荧光分光光度计研究了LiNbO3／SiO2／Si薄膜的光致发光。研究结果表明：在280nm激发光的激发下,LiNbO3／SiO2／Si薄膜在室温下发射470nm的蓝光,来源于LiNbO3薄膜与SiO2层界面处白捕获激子的辐射复合,发现在SiO2／Si薄膜上生长LiNbO3薄膜调制SiO2／Si薄膜的发光机制。     

热释电薄膜单片式非致冷红外焦平面阵列的研究

采用改进的溶胶-凝胶(sol-gel)技术,在Pt/Ti/SiO2/Si3N4/SiO2/Si基片上研制出具有优良热释电性能的BST,PLT和PZT铁电薄膜,它们是制备单片式非致冷红外焦平面阵列的优选探测材料。解决了制备热释电薄膜单片式非致冷红外焦平面阵列的关键技术,成功研制出8元、9元、10元线列和8×8元阵列,器件电压响应率(RV)达8.6×103V/W。     

在SiO2中掺Al对Au/纳米(SiO2/Si/SiO2)/p-Si 结构电致发光的影响

利用射频磁控溅射方法,制成纳米SiO2层厚度一定而纳米Si层厚度不同的纳米(SiO2/Si/SiO2)/p-Si结构和纳米(SiO2∶Al/Si/SiO2∶Al)/p-Si结构,用磁控溅射制备纳米SiO2∶Al时所用的SiO2/Al复合靶中的Al的面积百分比为1%．上述两种结构中Si层厚度均为1—3nm,间隔为0.2nm．为了对比研究,还制备了Si层厚度为零的样品．这两种结构在900℃氮气下退火30min,正面蒸半透明Au膜,背面蒸Al作欧姆接触后,都在正向偏置下观察到电致发光（EL）．在一定的正向偏置下,EL强度和峰位以及电流都随Si层厚度的增加而同步振荡,位相相同．但掺Al结构的发光强度普遍比不掺Al结构强．另外,这两种结构的EL具体振荡特性有明显不同．对这两种结构的电致发光的物理机制和SiO2中掺Al的作用进行了分析和讨论．     

AWG用Si基SiO2波导材料的制备

平面光波导在光波分复用技术中起着重要的作用，尤其是Si基SiO2波导器件在光通信领域中具有许多优点。因此，如何在Si衬底上制备出性能稳定良好的SiO2光波导材料至关重要。本文介绍了几种制备SiO2厚膜的方法。     

PLT/PbO铁电薄膜的制备及性能研究

采用射频磁控溅射技术,在室温溅射、后续退火条件下,以PbO为过渡层,在Pt(111)/Ti/SiO2/Si(100)衬底上制备出具有完全钙钛矿结构的(Pb0.90La0.10)Ti0.975O3(PLT)铁电薄膜;比较了在Pt(111)/Ti/SiO2/Si(100)衬底上有无PbO过渡层的PLT薄膜的微结构和铁电性能。实验结果表明,在Pt(111)/Ti/SiO2/Si(100)衬底上增加PbO过渡层提高了PLT薄膜的相纯度,并且所制备的PLT/PbO/Pt(111)/Ti/SiO2/Si(100)薄膜具有优良的介电和铁电性能,其剩余极化强度Pr为21.76μC/cm2,室温热释电系数p为2.75×10-8C/cm2.K。     

双层SiO2薄膜对ZnO/Si结构瑞利波器件性能的改善

利用3D有限元法分析了SiO2薄膜对ZnO/IDT/Si结构中瑞利波特性的影响,包括相速度(vp)、机电耦合系数(k2)和频率温度系数(τf)。结果表明,当hZ/λ=0.44时,ZnO/IDT/Si结构激发的瑞利波的机电耦合系数最大值k2max=2.38%,且vp=3 016 m/s,τf= -32.94×10-6 ℃-1。引入底层SiO2薄膜,即ZnO/IDT/SiO2/Si结构,瑞利波的机电耦合系数大幅提高,当hZ/λ=0.44,hsb/λ=0.25时,k2max=3.41%,且vp=2 801 m/s,τf=-11.43×10-6 ℃-1。继续引入顶层SiO2薄膜,即SiO2/ZnO/IDT/SiO2/Si结构,瑞利波相速度得到提高,但机电耦合系数随着SiO2厚度的增加而减小。当hZ/λ=0.44,hsb/λ=0.25,hst/λ=0.25时,k2=2.61%,vp=3 036 m/s,τf=18.44×10-6 ℃-1。双层SiO2薄膜的引入提高了ZnO/IDT/Si结构瑞利波器件的相速度、机电耦合系数,实现了温度补偿,因此,该结构可用于高机电耦合系数、高温度稳定性及低成本SAW器件的研制。     

Ultrathin stacked Si/sub 3/N/sub 4//SiO/sub 2/ gate dielectrics prepared by rapid thermal processing

Ultrathin (58 AA equivalent oxide thickness) stacked Si/sub 3/N/sub 4//SiO/sub 2/ (NO) films with the bottom oxide prepared by rapid thermal oxidation (RTO) in O/sub 2/ and the top nitride deposited by rapid thermal processing chemical vapour deposition (RP-CVD) were fabricated and studied. Results show that the charge trapping and leakage current of the stacked films are comparable to those of pure SiO/sub 2/ and low-field breakdown events are significantly reduced. By scaling down the top nitride thickness the commonly observed flat-band voltage instability of MNOS devices was minimised, but the low-defect property was still preserved.<>     

聚硅烷的氧等离子体处理特性

红外吸收谱分析表明，聚硅烷Ｐｏｌｙｍｅｔｈｙｌ ｐｈｅｎｅｔｈｙｌ ｓｉｌａｎｅ（ＰＭＰＥＳ）在氧等离子体处理后转变成ＰＳｉＯ膜，ＰＳｉＯ中的ｘ在１．５－２．０之间，其高频Ｃ－Ｖ特性曲线的平带电压力正，大小与氧等离子处理条件和ＰＭＰＥＳ厚度有关。     

不同退火氛围对TiN/HfO2/SiO2/Si结构电荷分布的影响

热退火技术是集成电路制造过程中用来改善材料性能的重要手段。系统分析了两种不同的退火条件(氨气氛围和氧气氛围)对TiN/HfO₂/SiO₂/Si结构中电荷分布的影响,给出了不同退火条件下SiO₂/Si和HfO₂/SiO₂界面的界面电荷密度、HfO₂的体电荷密度以及HfO₂/SiO₂界面的界面偶极子的数值。研究结果表明,在氨气和氧气氛围中退火会使HfO₂/SiO₂界面的界面电荷密度减小、界面偶极子增加,而SiO₂/Si界面的界面电荷密度几乎不受退火影响。最后研究了不同退火氛围对电容平带电压的影响,发现两种不同的退火条件都会导致TiN/HfO₂/SiO₂/Si电容结构平带电压的正向漂移,基于退火对其电荷分布的影响研究,此正向漂移主要来源于退火导致的HfO₂/SiO₂界面的界面偶极子的增加。     

金属/SiO2/Si基Bi4Ti3O12铁电薄膜的J-V特性

采用sol-gel方法在Pt/Ti/SiO2/Si衬底上制备了Bi4Ti3O12铁电薄膜。测试了其在直流电场下流过铁电薄膜的漏导电流J-V特性。测量结果显示正向漏电流明显小于负向漏电流。并讨论了金属–铁电薄膜所形成的整流接触特性,以及金属/SiO2/Si基Bi4Ti3O12铁电薄膜系统在不同电压范围(0~±6V)的导电机制。     

Au/(Si/SiO2)/p-Si结构中电流输运机制的研究

用射频磁控溅射法制备了Si/SiO2薄膜,利用Au/(Si/SiO2)/p-Si结构的I-V特性曲线对其输运机制进行了分析。结果表明,在较高的正向电场下,载流子主要是以电场协助隧穿(Fowler-Nordheim隧穿)方式通过氧化层,而在低场范围内和反向电场下,电流的产生则以热电子发射的方式为主。     

碳氟等离子体中CF2对SiO2，Si3N4和Si刻蚀的作用

The CF2 density and etch rate of SiO2, Si3N4 and Si are investigated as a function of gas pressure and O2 flow rate in fluorocarbon plasma. As the pressure increases, the self-bias voltage decreases whereas the SiO2 etch rate increases. Previous study has shown that SiO2 etch rate is proportional to the self-bias voltage. This result indicates that other etching parameters contribute to the SiO2 etching. Generally, the CF2 radical is considered as a precursor for fluorocarbon layer formation. At a given power, defluorination of fluorocarbon under high-energy ion bombardment is a main source of fluorine for SiO2 etching. When more CF2 radical in plasma, SiO2 etch rate is increased because more fluorine can be provided. In this case, CF2 is considered as a reactant for SiO2 etching. The etch rate of Si3N4 and Si is mainly determined by the polymer thickness formed on its surface which is dominated by the CF2 density in plasma. Etching results obtained by varying O2 flow rate also support the proposition.     

SiO_2:Er和Si_xO_2:Er薄膜室温Er~(3+)1.54μm波长的电致发光

在 n+ -Si衬底上用磁控溅射淀积掺 Er氧化硅 (Si O2 :Er)薄膜和掺 Er富硅氧化硅 (Six O2 :Er,x>1 )薄膜 ,薄膜经适当温度退火后 ,蒸上电极 ,形成发光二极管 (LED)。室温下在大于 4V反偏电压下发射了来自 Er3+的 1 .5 4μm波长的红外光。测量了由 Si O2 :Er/n+ -Si样品和 Six O2 :Er/n+ -Si样品分别制成的两种 LED,其 Er3+1 .5 4μm波长的电致发光峰强度 ,后者明显比前者强。还发现电致发光强度与 Si O2 :Er/n+ -Si样品和 Six O2 :Er/n+ -Si样品的退火温度有一定依赖关系     

Capacitance/voltage characteristics of semiconductor-insulator-semiconductor (SIS) structure

Ideal capacitance/voltage curves of Si(2)-SiO2-Si(1) structure are computed in the absence of surface states and oxide changes with the SiO2 thickness, conductivity types, impurity concentrations of Si(1) and (2) as parameters. Impurity concentrations of Si(1), (2) and SiO2 thickness can be estimated from the measured capacitance/voltage curves by comparing them with the calculated ones as is the case with the conventional MOS structure.     

Role of CF2 in the etching of SiO2, Si3N4 and Si in fluorocarbon plasma

The CF2 density and etch rate of SiO2, Si3N4 and Si are investigated as a function of gas pressure and 02 flow rate in fluorocarbon plasma. As the pressure increases, the self-bias voltage decreases whereas the SiO2 etch rate increases. Previous study has shown that SiO2 etch rate is proportional to the self-bias voltage. This result indicates that other etching parameters contribute to the SiO2 etching. Generally, the CF2 radical is considered as a precursor for fluorocarbon layer formation. At a given power, defluorination of fluorocarbon under high-energy ion bombardment is a main source of fluorine for SiO2 etching. When more CF2 radical in plasma, SiO2 etch rate is increased because more fluorine can be provided. In this case, CF2 is considered as a reactant for SiO2 etching. The etch rate of Si3N4 and Si is mainly determined by the polymer thickness formed on its surface which is dominated by the CF2 density in plasma. Etching results obtained by varying O2 flow rate also support the proposition.     

衬底对钛酸铋铁电薄膜生长及性能的影响

采用溶胶–凝胶工艺在Si和Pt/Ti/SiO2/Si两种衬底上制备了Bi4Ti3O12铁电薄膜,研究了衬底对Bi4Ti3O12铁电薄膜生长及性能的影响。研究表明:Pt/Ti/SiO2/Si基Bi4Ti3O12薄膜的剩余极化较高但易出现焦绿石相,而Si基Bi4Ti3O12薄膜易于沿c轴取向生长,有利于改善铁电薄膜与硅衬底之间的界面特性,但8mC/cm2的剩余极化却比前者有所降低。