Investigation of read disturb in split-gate memory and its feasible solution

The intrinsic read disturb mechanism in split-gate memory cells has been studied based on large amounts of experimental data and simulation results of 0.11 μm NOR SuperFlash® technology memory cells. It is shown that non-planar Floating Gate (FG) structure induced field enhance effect helps to cause Fowler-Nordheim Tunneling (F-N tunneling) in tunnel oxide during read operation, which will further lead to the leakage of electrons from FG to Word Line (WL). Then, the sensitivity of read disturb to process variation is investigated to expound the difference between typical cells and weak cells. The experiment has also demonstrated the weakening of read disturb due to induced tunnel oxide traps after program/erase (P/E) cycles. Based on these findings, we have rationally proposed possible solutions to reduce the read disturb on the perspectives of chip testing. The study of intrinsic read disturb mechanism is significant to the scaling of split-gate memory technology as well as to the assessment of read disturb risk in split-gate memory products.     

Degradations due to hole trapping in flash memory cells

Degradation in the hot-electron programmability of the flash memory cell is observed after erasing from the drain. Trapped holes in the oxide near the drain junction are found to be responsible for this degradation. Hole trapping in the oxide also causes another problem known as gate disturb, which is the undesired increase in the threshold voltage of an erased cell during programming of the other cells on the same word line. Threshold-voltage shifts due to gate disturb are used to monitor the amount of trapped holes in the oxide after cell erasure. It is determined that the trapped holes are mainly externally injected from the junction depletion region rather than directly generated in the oxide by the Fowler-Nordheim (F-N) tunneling process     

Over-erase phenomenon in SONOS-type flash memory and its minimization using a hafnium oxide charge storage Layer

The over-erase phenomenon in the polysilicon-oxide-silicon nitride-oxide-silicon (SONOS) memory structure is minimized by using hafnium oxide or hafnium aluminum oxide to replace silicon nitride as the charge storage layer (the resulting structures are termed SOHOS devices, where the "H" denotes the high dielectric constant material instead of silicon nitride). Unlike SONOS devices, SOHOS structures show a reduced over-erase phenomenon and self-limiting charge storage behavior under both erase and program operations. These are attributed to the differences in band offset and the crystallinity of the charge storage layer.     

NROM: A novel localized trapping, 2-bit nonvolatile memory cell

This paper presents a novel flash memory cell based on localized charge trapping in a dielectric layer and on a new read operation. It is based on the storage of a nominal ~400 electrons above a n⁺/p junction. Programming is performed by channel hot electron injection and erase by tunneling enhanced hot hole injection. The new read methodology is very sensitive to the location of trapped charge above the source. This single device cell has a two physical bit storage capability. The cell shows improved erase performances, no over erase and erratic bit issues, very good retention at 250°C, and endurance up to 1M cycles. Only four masks are added to a standard CMOS process to implement a virtual ground array. In a typical 0.35 μm process, the area of a bit is 0.315 μm² and 0.188 μm² in 0.25 μm technology. All these features and the small cell size compared to any other flash cell make this device a very attractive solution for all NVM applications     

Novel program versus disturb window characterization for split-gate flash cell

In this letter, a new methodology for program versus disturb window characterization on split gate flash cell is presented for the first time. The window can be graphically illustrated in V/sub wl/ (word-line)-V/sub ss/ (source) domain under a given program current. This method can help us understand quantitatively how the window shifts versus bias conditions and find the optimal program condition. The condition obtained by this method can have the largest tolerance for program bias variations. This methodology was successfully implemented in 0.18-/spl mu/m triple self-aligned (SA3) split-gate cell characterization to provide program condition for 32 M products.     

Modeling for the 2nd-bit effect of a nitride-based trapping storage flash EEPROM cell under two-bit operation

In this letter, we propose a macromodeling approach for the nitride-based trapping storage Flash EEPROM cell with intriguing 2nd-bit effect. Both unusual I/sub D/-V/sub D/ and I/sub D/-V/sub G/ characteristics of this 2-bit Flash cell can be accurately modeled by the macromodel. It also provides insights into the special device characteristics of the programmed cell. Furthermore, we can use this model to correctly evaluate the read speed degradation resulting from 2nd-bit effect.     

The flash memory read path: building blocks and critical aspects

The ever-increasing demand for portable equipment is leading to the use of flash memory devices for nonvolatile storage. Fast access time and low power consumption are obviously key requirements. Moreover, multilevel storage techniques are mandatory to reduce the cost per megabit. As a consequence, the READ operation becomes more and more critical, and optimized solutions are needed for almost all circuits involved in the read path. This paper examines the whole read path from addresses to data output, and describes several schemes developed to achieve the required high performances.     

A 1.8-V 128-Mb 125-MHz multilevel cell flash memory with flexible read while write

Application of multilevel cell (MLC) technology to a flexible read-while-write flash memory has been achieved through the use of a highly optimized sensing architecture. The goal of this implementation is to provide performance on par with single-bit-per-cell implementations while significantly reducing the overall die size. In order to achieve the required high-speed operation using MLC structures, all offsets to the sense amplifier were minimized and the column load and local sense amplifier were optimized to provide ample differential gain. Through the use of these optimization techniques, a 1.8-V MLC-based flexible read-while-write memory with 125-MHz continuous burst and 40-ns random read access time has been manufactured. Using a 0.13-/spl mu/m technology, this new device provides a die size that is 25% of the size of the equivalent single-bit-per-cell device manufactured on a 0.18-/spl mu/m technology.     

Lateral migration of trapped holes in a nitride storage flash memory cell and its qualification methodology

The negative threshold voltage (V/sub t/) shift of a nitride storage flash memory cell in the erase state will result in an increase in leakage current. By utilizing a charge pumping method, we found that trapped hole lateral migration is responsible for this V/sub t/ shift. Hole transport in nitride is characterized by monitoring gate induced drain leakage current and using a thermionic emission model. The hole emission induced V/sub t/ shift shows a linear correlation with bake time in a semi-logarithm plot and its slope depends on the bake temperature. Based on the result, an accelerated qualification method for the negative V/sub t/ drift is proposed.     

A novel erase scheme to suppress overerasure in a scaled 2-bit nitride storage flash memory cell

The cause of over-erasure in a two-bit nitride storage flash memory cell is investigated. Extra positive charges accumulated above the n/sup +/ junction and channel-shortening enhanced drain-induced barrier lowering effect are found to be responsible for threshold voltage (V/sub t/) lowering in an over-erased cell. A modified erase scheme is proposed to resolve this issue. By applying a source voltage during erase, the erase speed can be well controlled for cells with different channel lengths and a wide range of program-state V/sub t/ distribution, which will reduce overerasure significantly.     

Read disturb in flash memories: reliability case

It is known that program/erase cycling of Flash memories induces a degradation of the tunnel oxide insulating property usually referred to as Stress-Induced Leakage Current (SILC). An issue related to SILC is the read disturb, affecting cells in an addressed word-line, which can cause electron injection through tunnel oxide in the floating gate of erased cells during read operation. Read disturb can also be present in Flash memory with a weak tunnel oxide quality: aim of this paper is to discuss in detail the effect of this read disturb phenomena. Cell Failure Density (CDF) extrapolation from experimental data using statistical method is able to estimate defect probability and application’s failure rate for both SILC and weak tunnel oxide quality cases.     

Characterization of programmed charge lateral distribution in a two-bit storage nitride flash memory cell by using a charge-pumping technique

In this paper, we use a modified charge pumping technique to characterize the programmed charge lateral distribution in a hot electron program/hot hole erase, two-bit storage nitride Flash memory cell. The stored charge distribution of each bit over the source/drain junctions can be profiled separately. Our result shows that the second programmed bit has a broader stored charge distribution than the first programmed bit. The reason is that a large channel field exists under the first programmed bit during the second bit programming. Such a large field accelerates channel electrons and causes earlier electron injection into the nitride. In addition, we find that programmed charges spread further into the channel as program/erase cycle number increases.     

Temperature effect on read current in a two-bit nitride-based trapping Storage Flash EEPROM cell

The temperature effect on the read current of a two-bit nitride-storage Flash memory cell is investigated. In contrast to a conventional silicon-oxide-nitride-oxide (SONOS) cell with uniform Fowler-Nordheim (FN) programming, a significant high-V/sub T/ state read current increase, which results in the read window narrowing at high temperature, is observed in a channel hot electron (CHE) programmed cell. The increment of high-V/sub T/ state leakage current shows a positive correlation with program/erase threshold voltage window. Since the temperature effect is very sensitive to a locally trapped charge profile, a two-dimensional simulation with a step charge profile is employed to characterize the relationship between current increment and both charge width and charge density.     

A new method to extract gate coupling ratio and oxide trapped charge in flash memory cell

A new method to obtain the gate coupling ratio (α_g) and oxide trapped charge (Q_ox) as a result of cycling in flash memory cells is described here. Three cells with an equivalent physical structure but different erase characteristics are measured. The threshold changes versus erase times are fitted to the charge removal rate calculated based on Fowler-Nordheim (FN) tunneling and the capacitive relations among all nodes. The extracted α_g is independent of technologies and this method is particular useful when the profile of the floating gate is not traditionally rectangular owing to advanced processes such as trapezoidal poly etch or a poly-spacer addition on the floating gate sidewall. The Q_ox can also be determined once α_g is extracted.     

新型多位非均匀沟道电荷俘获型存储器及新型虚拟源端的NAND阵列结构

为了解决传统多位存储NAND型存储器中位与位互相干扰的问题,本文提出了一种新型的用于多位存储的非均匀沟道电荷俘获型存储器及新型NAND结构。该器件能够很好地抑制SBE效应从而提供3比特/单元的存储能力。由于n-缓冲区的存在,由SBE效应导致的阈值电压漂移能够减小到400mV,在3比特/单元的存储能力下最小阈值电压窗口可以达到750mV。本器件还引入了富硅氮氧化硅层最为电荷俘获层,从而很好地提高了器件的电荷保持特性。     

New operation mode for stacked-gate flash memory cell

A new operational mode is proposed that lowers the threshold voltage of a stacked-gate flash memory cell. The mode features the set-up of the word-line voltage and bit-line voltage. An AC signal is applied to a word-line while a bit-line is kept floating after it is charged. The signal is applied to lower the threshold voltage of the cell and to test it. A SPICE simulation of this operation has revealed that the converged voltage of floating gate has negligible dependency on the initial voltage and the tunnel oxide thickness and that the cell threshold voltage is controllable through the world-line voltage. This operation mode is easily applicable to a conventional flash memory. Furthermore, it may allow the use of flash cells in analog applications or in multi-level memory cells     

Bipolar transistor selected P-channel flash memory cell technology

A novel BIpolar Transistor Selected (BITS) P-channel flash memory cell is proposed, where a bipolar transistor embedded in the source region of the cell amplifies cell-read-current and acts as a select transistor. With this cell, not only a very low 1.5 V non-word-line-boosting read operation, but also a sector-erase operation are successfully achieved with only a small cell-size increase over the conventional NOR cell. Moreover, this cell technology maintains all the advantages of the P-channel DIvided-bit-line NOR (DINOR) flash memory     

A study of hot-hole injection during programming drain disturb in flash memories

Program disturbs in NOR-type Flash arrays significantly degrade the tunnel oxide by hot-hole injection (HHI) induced by band-to-band tunneling at the drain overlap. This paper provides a comprehensive experimental and modeling analysis of HHI in Flash memories under program-disturb conditions. Carrier-separation measurements on arrays of Flash memories with contacted floating-gate (FG) allows for a direct investigation of hole-initiated impact ionization and HHI. A Monte Carlo (MC) model is used to simulate carrier multiplication and injection into the FG. After validating the MC model against experimental data for both secondary electron generation and HHI, the model is used to provide further insight into the hole-injection mechanism.     

Compact modeling of a flash memory cell including substrate-bias-dependent hot-electron gate current

We propose a compact model for a Flash memory cell that is suitable for circuit simulation. The model includes a hot-electron gate current model that considers not only channel hot electron injection but also channel initiated secondary electron injection to express properly substrate bias dependence of gate current. Tunneling gate current for erasing is expressed by the BSIM4 tunneling gate current model. Good agreement between measured and simulated results of both programming and erasing characteristics for 130-nm technology Flash memory cells indicates that our model is useful in designing and optimizing circuit for Flash memories.