The effects of source/drain resistance on deep submicrometer deviceperformance

As MOSFET channel lengths approach the deep-submicrometer regime, performance degradation due to parasitic source/drain resistance (R _sd) becomes an important factor to consider in device scaling. The effects of R_sd on the device performance of deep-submicrometer non-LDD (lightly doped drain) n-channel MOSFETs are examined. Reduction in the measured saturation drain current (R_sd=600 Ω-μm) relative to the ideal saturation current (R_sd=0.0 Ω-μm) is about 4% for L_eff=0.7 μm and T_ox =15.6 nm and 10% for L_eff=0.3 μm and T _ox=8.6 nm. Reduction of current in the linear regime and reduction of the simulated ring oscillator speed are both about three times higher. The effect of salicide technologies on device performance is discussed. Projections are made of the ultimate achievable performance     

A new cobalt salicide technology for 0.15-μm CMOS devices

A new cobalt (Co) salicide technology for sub-quarter micron CMOS transistors has been developed using high-temperature sputtering and in situ vacuum annealing. Sheet resistance of 11 Ω/□ for both gate electrode and diffusion layer was obtained with 5-nm-thick Co film. No line width dependence of sheet resistance was observed down to 0.15-μm-wide gate electrode and 0.33-μm-wide diffusion layer. The high temperature sputtering process led to the growth of epitaxial CoSi ₂ layers with high thermal stability. By using this technology 0.15 μm CMOS devices which have shallow junctions were successfully fabricated     

0.12-μm gate III-V nitride HFET's with high contact resistances

HFET's with 0.12-μm gate length were fabricated on a III-V nitride wafer. The contact resistance from unannealed Ti/Au ohmic contact was 10 Ω·mm. Even with this relatively high contact resistance, f_T of 46.9 GHz and f_max of 103 GHz were measured with the Ti/Au contacts, the highest yet achieved on III-V nitride FETs. The improvement in the frequency response was mainly due to the decrease in the gate length (0.12 μm). In addition, the effects of high contact resistances at high frequency are discussed     

Spiral inductors on Si p/p+ substrates with resonantfrequency of 20 GHz

Porous Si of up to 200 μm in thickness has been used to fabricate high-performance spiral inductors on heavily doped Si substrates (0.007 Ω-cm). Spiral inductors with L~5.7 nH are fabricated demonstrating Q_max~29 at 7 GHz and f_r>20 GHz. The resonant frequency (f_r) increases with increasing porous Si thickness and saturates beyond 120 μm. A corresponding decrease in total capacitance is observed. Q_max increases monotonically with porous Si layer thickness to beyond 200 μm. For inductors with a smaller footprint, Q_max begins to saturate at less than 100-μm thick porous Si     

Low-resistance self-aligned Ti-silicide technology for sub-quartermicron CMOS devices

A low-resistance self-aligned Ti-silicide process featuring selective silicon deposition and subsequent pre-amorphization (SEDAM) is proposed and characterized for sub-quarter micron CMOS devices. 0.15-μm CMOS devices with low-resistance and uniform TiSi₂ on gate and source/drain regions were fabricated using the SEDAM process. Non-doped silicon films were selectively deposited on gate and source/drain regions to reduce suppression of silicidation due to heavily-doped As in the silicon. Silicidation was also enhanced by pre-amorphization, using ion-implantation, on the narrow gate and source/drain regions. Low-resistance and uniform TiSi₂ films were achieved on all narrow, long n⁺ and p⁺ poly-Si and diffusion layers of 0.15-μm CMOS devices. TiSi₂ films with a sheet resistance of 5 to 7 Ω/sq were stably and uniformly formed on 0.15-μm-wide n⁺ and p⁺ poly-Si. No degradation in leakage characteristics was observed in pn-junctions with TiSi₂ films. It was confirmed that, using SEDAM, excellent device characteristics were achieved for 0.15-μm NMOSFET's and PMOSFET's with self-aligned TiSi₂ films     

A low thermal budget self-aligned Ti silicide technology usinggermanium implantation for thin-film SOI MOSFET's

In this paper, a titanium salicide technology with a very low thermal annealing temperature using germanium implantation for thin film SOI MOSFET's is investigated in detail. Ti silicide formation on the amorphous silicon generated by germanium implantation is studied. Compared to the conventional Ti salicide process, the Ti silicidation temperature is significantly lowered and the silicide depth is well controlled through the pre-amorphized layer. Therefore, the potential problems of the salicide process for SOI MOSFET's such as lateral voids, dopant segregation, thermal agglomeration, and increase of resistance on narrow gate are suppressed by germanium implantation. With the Ge pre-amorphization salicide process, a very low silicide contact resistance is obtained and sub-0.25-μm SOI MOSFET's are fabricated with good device characteristics     

A rail-to-rail input/output CMOS power amplifier

A rail-to-rail amplifier that maintains a high common-mode rejection ratio (CMRR) over the whole common-mode range and has a low harmonic distortion despite the use of relatively small output devices is discussed. The circuit, which measures only 0.3 mm² in a 3-μm technology, has a quiescent current consumption of 600 μA and a CMRR larger than 55 dB. It handles up to 4 nF, and can, with a 5-V supply, drive 3.8 V_pp into 100 Ω (0.1% total harmonic distortion at 10 kHz)     

New Ti-SALICIDE process using Sb and Ge preamorphization forsub-0.2 μm CMOS technology

A new process for thin titanium self-aligned silicide (Ti-SALICIDE) on narrow n⁺ poly-Si lines and n⁺ diffusion layers using preamorphization implantation (PAI) with heavy ions of antimony (Sb) and germanium (Ge) has been demonstrated for application to 0.2-μm CMOS devices and beyond. Preamorphization enhances the phase transformation from C₄₉Ti_xSi _x to C₅₄TiSi₂ and lowers the transformation temperature by 80°C so that it occurs before conglomeration in narrow lines. Preamorphization by Sb and Ge implantation yields better results than that by As. The sheet resistance of TiSi₂ on heavily As doped poly-Si lines are 3.7 Ω/□ and 3.8 Ω/□ for the samples preamorphized by Ge and Sb implantations even with line width down to 0.2 μm. There is less leakage in the Ti-SALICIDE diode with preamorphization than without it. The probable reasons and mechanisms are discussed     

Low resistance intracavity-contacted oxide-aperture VCSELs

The authors study, analytically and experimentally, the extrinsic series resistance in intracavity-contacted vertical-cavity surface-emitting lasers (VCSEL's). Low resistance, low threshold-current, intracavity-contacted VCSELs are fabricated, with resistances ranging from 355 Ω for 4-μm square apertures to 80 Ω for 12-μm square apertures and threshold voltages as low as 1.35 V. To the best of our knowledge, these are the lowest values reported for this type of VCSEL. The threshold currents range from 270 μA for 4 μm×4 μm apertures to 850 μA for 12 ×12 μm. From a comparison of the resistance as a function of oxide aperture radius, the measured data follows closely with the calculated data, demonstrating the validity of the derived expressions for series resistance     

1.57 μm strained-layer quantum-well GaInAlAs ridge-waveguidelaser diodes with high temperature (130°C) and ultrahigh-speed (17GHz) performance

The fabrication of GaInAlAs strained-layer (SL) multiple-quantum-well (MQW) ridge-waveguide (RW) laser diodes emitting at 1.57 μm is discussed. Due to an optimized layer structure, a very high characteristic temperature of 90 K was obtained. As a consequence for episide-up mounted devices, the maximum continuous wave (CW)-operation temperature is 130°C. At room temperature, a maximum output power of 47 mW was measured for 600-μm-long lasers with one high-reflection coated facet. The low series resistance of 4 Ω (2 Ω) for 200-μm-(400-μm)-long devices yields an ultrahigh 3-dB bandwidth of 17 GHz. These static and dynamic properties also result from a high internal quantum-efficiency of 0.83 and a high differential gain of 5.5×10^-15 cm²     

An 0.3-μm Si epitaxial base BiCMOS technology with 37-GHzfmax and 10-V BVceo for RF telecommunication

In this paper, a 0.3-μm BiCMOS technology for mixed analog/digital application is presented. A typical emitter area of this technology is 0.3 μm×1.0 μm. This technology includes high f _max of 37 GHz at the low collector current of 300 μA and high BV_ceo of 10 V NPN transistor, CMOS with L_eff=0.3 μm, and passive elements. By using the shallow and deep trench isolation technology and nonselective epitaxial intrinsic base, the C_jc can be reduced to 1.6 fF, which is the lowest value reported so far. As a results, we have managed to obtain the high f_max at the low current region and high BV _ceo concurrently. These features will contribute to the development of high-performance BiCMOS LSI's for various mixed analog/digital applications     

Room temperature pulsed operation of 1.5 μm GaInAsP/InPvertical-cavity surface-emitting laser

Room-temperature pulsed operation of a GaInAsP/InP vertical-cavity surface-emitting laser diode (VCSELD) with an emission wavelength near 1.55 μm is reported. A double heterostructure with a 34-pair GaInAsP (λ_g=1.4 μm)/InP distributed Bragg reflector (DBR) was grown by metalorganic chemical vapor deposition (MOCVD). The measured reflectivity of the semiconductor DBR is over 97% and threshold current is 260 mA for a 40-μmφ device with a 0.88-μm-thick active layer. Threshold current density is as low as 21 kA/cm² at room temperature     

SHG and internal conical refraction experiments in CsTiOAsO4, comparison with KTiOPO4 and KTiOAsO4, for1.32-μm type II SHG

The internal conical refraction angles between 0.5321.32 μm, the phase-matching directions of 1.064 μm type I second harmonic generation (SHG) and of 1.32-μm type II SHG are measured in a sphere of CsTiOAsO₄ (CTA). The relative sign and absolute magnitude of two independent quadratic nonlinear coefficients are determined by 1.32-μm phase-matched type II SHG conversion efficiency measurements in a sphere and strips: d₁₅=1.09±0.09 pm/V and d₂₄=1.7±0.6 pm/V at 0.65 μm. AH the results are compared with previous work. The comparison of CTA with KTiOPO₄ and KTiOAsO₄ is made in order to evaluate the crystal which provides the highest conversion efficiency for 1.32-μm type II SHG depending on the crystal length and on the beam waist radius     

High-performance long-wavelength (λ~1.3 μm) InGaAsPNquantum-well lasers

We demonstrate high-performance InGaAsPN quantum well based long-wavelength lasers grown on GaAs substrates, nitrogen containing lasers emitting in the λ=1.2- to 1.3-μm wavelength range were grown by gas source molecular beam epitaxy using a RF plasma nitrogen source. Under pulsed excitation, lasers emitting at λ=1.295 μm exhibited a record low threshold current density (J_TH) of 2. 5 kA/cm². Lasers grown with less nitrogen in the quantum well exhibited significantly lower threshold current densities of J_TH =1.9 kA/cm² at λ=1.27 μm and J_TH=1.27 kA/cm² at λ=1.2 μm. We also report a slope efficiency of 0.4 W/A and an output power of 450 mW under pulsed operation for nitrogen containing lasers emitting at 1.2 μm     

SiGe drift base bipolar transistor with self-aligned selectiveCVD-tungsten electrodes

A new device and process technology is developed for high-speed SiGe epitaxial base transistors. A 60-nm SiGe epitaxial base and the selectively ion-implanted collector (SIC) structure enhance the cutoff frequency to about 40 GHz. Base resistance is minimized to 165 Ω (emitter area: 0.2×3 μm²), and an f_MAX of 37.1 GHz is achieved by employing 0.2-μm EB lithography for the emitter window, selective CVD tungsten for the base electrode and a self-aligned oxide side wall for the emitter-to-base separation. Circuit simulations predict that this device could reduce the ECL gate delay to below 20 ps     

Low-power bandgap references featuring DTMOSTs

This paper describes two CMOS bandgap reference circuits featuring dynamic-threshold MOS transistors. The first bandgap reference circuit aims at application in low-voltage, low-power ICs that tolerate medium accuracy. The circuit runs at supply voltages down to 0.85 V while consuming only 1 μW; the die area is 0.063 mm² in a standard digital 0.35-μm CMOS process. The second bandgap reference circuit aims at high accuracy operation (σ=0.3%) without trimming. It consumes approximately 5 μW from a 1.8-V supply voltage and occupies 0.06 mm² in a standard 0.35-μm CMOS process     

Investigation of broad-band quantum-well infrared photodetectorsfor 8-14-μm detection

Typical quantum-well infrared photodetectors (QWIPs) exhibit a rather narrow spectral bandwidth of 1-2 μm. For certain applications, such as spectroscopy, sensing a broader range of infrared radiation is highly desirable. In this paper, we report the design of four broad-band QWIPs (BB-QWIPs) sensitive over the 8-14-μm spectral range. Two n-type BB-QWIPs, consisting of three and four quantum wells of different thickness and/or composition in a unit cell which is then repeated 20 times to create the BB-QWIP structure, are demonstrated. The three-well n-type In_xGa_1-xAs-Al_yGa_1-yAs BB-QWIP was designed to have a response peak at 10 μm, with a full-width at half-maximum (FWHM) bandwidth that varies with the applied bias. A maximum bandwidth of Δλ/λ_p=21% was obtained for this device at V_b=-2 V. The four-well n-type In_xGa_1-xAs-GaAs BB-QWIP not only exhibits a large responsivity of 2.31 A/W at 10.3 μm and V_b=+4.5 V, but also achieves a bandwidth of Δλ/λ_p=29% that is broader than the three-well device. In addition, two p-type In _xGa_1-xAs-GaAs BB-QWIPs with variable well thickness and composition, sensitive in the 7-14-μm spectral range, are also demonstrated. The variable composition p-type BB-QWIP has a large FWHM bandwidth of Δλ/λ_p=48% at T=40 K and V_b=-1.5 V. The variable thickness p-type BB-QWIP was found to have an even broader FWHM bandwidth of Δλ/λ _p=63% at T=40 K and V_b=1.1 V, with a corresponding peak responsivity of 25 mA/W at 10.2 μm. The results show that a broader and flatter spectral bandwidth was obtained in both p-type BB-QWIP's than in the n-type BS-QWIP's under similar operating conditions     

Self-aligned bottom-gate submicrometer-channel-length a-Si-:Hthin-film transistors

Fully self-aligned bottom-gate thin-film transistors (TFTs) fabricated by using a back substrate exposure technique combined with a metal lift-off process are discussed. Ohmic contact to the sources and drains is accomplished by a 40-nm-thick layer of phosphorous-doped microcrystalline silicon. Devices with channel lengths ranging from 0.4 to 12 μm are processed with overlap dimensions between the gate and the source and the gate and the drain ranging from 0.0 to 1.0 μm. Analysis of the conductance data in the linear voltage regime reveals a parasitic drain-to-channel and source-to-channel resistance that is 14% of the channel resistance for a 10-μm device and 140% for a 1-μm device. Thus, increase in the device speed caused by reducing the channel length does not follow expected behavior. A similar situation exists in the nonlinear regime. The on-current of the devices starts to saturate below channel lengths of 2 μm. Current on/off ratios taken at V_d=5 V and V_G=15 V and 0 V, respectively, are approximately 1×10⁶ for the 1- and 12-μm-long devices. The on/off ratio is reduced to 1×10⁵ for the 0.4-μm device     

High reliability InGaP/GaAs HBT

Excellent long term reliability InGaP/GaAs heterojunction bipolar transistors (HBT) grown by metalorganic chemical vapor deposition (MOCVD) are demonstrated. There were no device failures (T=10000 h) in a sample lot of ten devices (L=6.4 μm ×20 μm) under moderate current densities and high-temperature testing (J_c=25 kA/cm ², V_ce=2.0 V, Junction Temp =264°C). The dc current gain for large area devices (L=75 μm ×75 μm) at 1 kA/cm² at a base sheet resistance of 240 ohms/sq (4×10 ¹⁹ cm^-3@700 Å) was over 100. The dc current gain before reliability testing (L=6.4 μm ×10 μm) at 0.8 kA/cm² was 62. The dc current gain (0.8 kA/cm²) decreased to 57 after 10000 h of reliability testing. The devices showed an f_T=61 GHz and f_max=103 GHz. The reliability results are the highest ever achieved for InGaP/GaAs HBT and these results indicate the great potential of InGaP/GaAs HBT for numerous low- and high-frequency microwave circuit applications. The reliability improvements are probably due to the initial low base current at low current densities which result from the low surface recombination of InGaP and the high valence band discontinuity between InGaP and GaAs     

Simplified Z-propagating DC bias stable TE-TM modeconvertor fabricated in Y-cut lithium niobate

A TE-TM mode converter, useful at either 0.632 or 0.840 μm, has been fabricated on y-cut LiNbO₃ by Ti indiffusion with the channel waveguide placed parallel to the z-axis. For TE polarized input, the maximum TM modulation depth is 97 percent at 0.632 μm with a 5-V (pp) drive and 99 percent at 0.840 μm with a 12-V (pp) drive. A similar device operating at 1.3 μm displays 98-percent TE-TM switching at 68 V. Operation involves only coplanar electrodes placed alongside the channel acting on the r₆₁ electrooptic coefficient. A separately deposited buffer layer is unnecessary. Testing indicates a substantially greater tolerance to electrode misalignment than afforded by similar structures formed in x-cut substrates. Data illustrating immunity to photorefractive drift in the presence of a DC bias voltage is presented for 0.840-μm wavelength operation