Design of Solder Joint Structure for Flip Chip Package with an Optimized Shear Test Method

The structure of flip chip solder bumps was optimized in terms of shear height and shear speed using a shear test method with both experimental investigation and nonlinear, three-dimensional, finite element analysis being conducted. A representative, Pb-free solder composition, Sn-3.0Ag-0.5Cu, was used to optimize the shear test of the flip chip solder joints. Increasing the shear height, at a fixed shear speed, decreased the shear force, as did decreasing the shear speed, at a fixed shear height. These experimental and computational results supported the recommendation of low shear height and low shear speed condition for the shear testing of flip chip solder bumps. This optimized shear test method was applied to investigate the effect of various heights of mini bumps on the shear force of the solder joints. The shear force increased with increasing Ni-P mini bump height.     

一种低成本倒装芯片用印刷凸焊点技术的研究

利用化学镀底部金属化层结合丝网印刷制作凸焊点的技术,通过剪切实验得到了凸焊点的剪切强度,用电子显微镜对失效表面进行了分析研究,应用SEM及EDAX分析了凸焊点的组织结构与成分变化,对热老炼后凸焊点的强度变化进行了研究。结果表明凸焊点内部组织结构的变化是剪切失效的主要原因。经X光及扫描声学显微镜检测,表明组装及填充工艺很成功。对已完成及未进行填充的两种FCOB样品进行热疲劳实验对比,发现未进行填充加固的样品在115周循环后出现失效,而经填充加固后的样品通过了1 000周循环,表明下填料明显延长了倒装焊封装的热疲劳寿命。     

HV‐SoP Technology for Maskless Fine‐Pitch Bumping Process

Recently, we have witnessed the gradual miniaturization of electronic devices. In miniaturized devices, flip‐chip bonding has become a necessity over other bonding methods. For the electrical connections in miniaturized devices, fine‐pitch solder bumping has been widely studied. In this study, high‐volume solder‐on‐pad (HV‐SoP) technology was developed using a novel maskless printing method. For the new SoP process, we used a special material called a solder bump maker (SBM). Using an SBM, which consists of resin and solder powder, uniform bumps can easily be made without a mask. To optimize the height of solder bumps, various conditions such as the mask design, oxygen concentration, and processing method are controlled. In this study, a double printing method, which is a modification of a general single printing method, is suggested. The average, maximum, and minimum obtained heights of solder bumps are 28.3 μm, 31.7 μm, and 26.3 μm, respectively. It is expected that the HV‐SoP process will reduce the costs for solder bumping and will be used for electrical interconnections in fine‐pitch flip‐chip bonding.     

Solder wetting in a wafer-level flip chip assembly

Wafer-level flip chips provide an innovative solution in establishing flip chip as a standard surface mount process. In this paper, the wetting of solder bumps within confining underfill during the reflow of a wafer-level flip chip assembly is addressed. For real time monitoring of an assembly during the reflow process, a system using a high-speed camera is utilized. The collapse of solder bumps on the chip in the vertical direction is found to be a prerequisite of solder wetting. Underfill voids and outgassing are found to cause chip drift and tilt during the reflow process. In addition, symmetry of the underfill flow and fillet formation is identified as a critical factor in maintaining chip to substrate alignment. During solder wetting of the metallization pads on the substrate, the underfill needs to maintain a low viscosity. With the selection of a thermally stable underfill and corresponding process development, wafer-level flip chip assemblies with good solder interconnects are demonstrated     

Bump formation for flip chip and CSP by solder paste printing

Area array packages (flip chip, CSP and BGA) require the formation of bumps for the board assembly. Since the established bumping methods need expensive equipment or are limited by the throughput, minimal pitch and yield the industry is currently searching for new and lower cost bumping approaches. In this paper the experimental work of stencil printing to create solder bumps for flip chip and wafer level CSP (CSP-WL) is described in detail.This paper is divided into two parts. In the first part of the paper a low cost wafer bumping process for flip chip applications will be studied in particular. The process is based on an electroless Nickel under bump metallization and solder bumping by stencil printing. The experimental results for this technology will be presented and the limits concerning pitch, reproducibility and bump height will be discussed in detail. The second part of the paper is focused on solder paste printing for wafer-level CSPs. In order to achieve large bumps an optimized printing method will be presented. Additionally advanced stencil design will be shown and the achieved results will be compared with conventional methods.     

Mechanical loading of flip chip joints before underfill: the impact on yield and reliability

The underfill-facilitated migration from ceramic to lower cost laminate substrates has become a powerful enabler of direct chip attach by offering lower cost, greater electrical functionality, and a smaller system footprint over comparable packaging technologies. Once underfilled, flip chip on laminate has proven extremely reliable even in severe automotive environments. However, between the process steps of reflow and underfill cure, unprotected flip chip solder joints assembled to laminate boards are susceptible to damage and breakage if mishandled. Here, the survivability and long-term reliability of flip chip joints was studied over a range of applied strains. Mechanical loading of joints was applied via beam deflections of populated, but nonunderfilled, laminate boards. Electrical continuity was monitored before and after testing to determine when the load applied to the flip chip exceeded the joint fracture strength. The propensity for solder joint fracture was then calculated as a function of solder bump size and also as a function of strain rate. Analysis of the mechanical properties of solder revealed assembly strategies which reduce bump damage and eliminate yield loss during the process steps leading up to underfill cure. Both strained and unstrained units were then underfilled and cycled between −50 and +150 °C. While mechanical damage was evident in bump cross-sections of strained flip chip assemblies, the fatigue lives of underfilled solder joints were found to be independent of the size of mechanical loads applied before underfill.     

Cycling copper flip chip interconnects

Use of flip chip assembly on compound semiconductor circuits is relatively new. Although solder bumping has been around for a while, use of copper bumps is also new. This discussion is intended to provide some initial data on the melding of copper flip chip bumps and compound semiconductor technologies, with respect to thermal excursion testing––cycling. For comparison, it is known that attempts to accelerate degradation caused by thermal excursions on solder bumps can result in irregular failure mechanisms. This work shows that on-chip power cycling can be used to cause identical failure mechanisms to those caused by normal temperature cycling.     

Low cost bumping by stencil printing: process qualification for 200 μm pitch

Area array packages (flip chip, CSP (Chip scale packages) and BGA) require the formation of bumps for the board assembly. Since the established bumping methods need expensive equipment and/or are limited by the throughput, minimal pitch and yield, the industry is currently searching for new and lower cost bumping approaches. The experimental work of stencil printing to create solder bumps for flip chip devices is described in detail in this article. In the first part of this article, a low cost wafer bumping process for flip chip applications will be studied in particular. The process is based on an electroless nickel under bump metallization and solder bumping by stencil printing. The experimental results for this technology will be presented, and the limits concerning pitch, stencil design, reproducibility and bump height will be discussed in detail. In the second part, a comparison of measured standard deviations of bump heights as well as the quality demands for ultrafine pitch flip chip assembly are shown.     

The effect of solder bump pitch on the underfill flow

An underfill encapsulant was used to fill the gap between the chip and substrate around solder joints to improve the long-term reliability of flip chip interconnect systems. The underfill encapsulant was filled by the capillary effect. In this study, the filling time and pattern of the underfill flow in the process with different bumping pitch, bump diameter, and gap size were investigated. A modified Hele-Shaw flow model, that considered the flow resistance in both the thickness direction and the restrictions between solder bumps, was used. This model estimated the flow resistance induced by the chip and substrate as well as the solder bumps, and provided a reasonable flow front prediction. A modified model that considered the effect of fine pitch solder bumps was also proposed to estimate the capillary force in fine pitch arrangements. It was found that, on a full array solder bump pattern, the filling flow was actually faster for fine pitch bumps in some arrangements. The filling time of the underfill process depends on the parameters of bumping pitch, bump diameter, and gap size. A proposed capillary force parameter can provide information on bump pattern design for facilitating the underfilling process.     

Long time reliability study of soldered flip chips on flexible substrates

Due to the requirements of new light, mobile, small and multifunctional electronic products the density of electronic packages continues to increase. Especially in medical electronics like pace makers the minimisation of the whole product size is an important factor. So flip chip technology becomes more and more attractive to reduce the height of an electronic package. At the same time the use of flexible and foldable substrates offers the possibility to create complex electronic devices with a very high density. In terms of human health the reliability of electronic products in medical applications has top priority.In this work flip chip interconnections to a flexible substrate are studied with regard to long time reliability. Test chips and substrates have been designed to give the possibility for electrical measurements. Solder was applied using conventional stencil printing method. The flip chip contacts on flexible substrates were created in a reflow process and underfilled subsequently.The assemblies have been tested according to JEDEC level 3. The focus in this paper is the long time reliability up to 10,000 h in thermal ageing at 125 °C and temperature/humidity testing at 85 °C/85% relative humidity as well as thermal cycling (0 °C/+100 °C) up to 5000 cycles. Daisy chain and four point Kelvin resistances have been measured to characterise the interconnections and monitor degradation effects.The failures have been analysed in terms of metallurgical investigations of formation and growing of intermetallic phases between underbump metallisation, solder bumps and conductor lines. CSAM was used to detect delaminations at the interfaces underfiller/chip and underfiller/substrate respectively.     

Fabrication on uniform plating-based flip chip solder bumps after reflow process using a polishing mechanism

This paper presents an innovative polishing process aimed at leveling rough surface of plating-based flip chip solder bumps so as to get uniform coplanarity across the whole substrate after both electroplating and reflow processes. This polishing mechanism is characteristic of combining mechanical-dominated polishing force with slight chemical reaction together. A large number of extremely but inevitably rugged mushroom-like structures after electroplating are drastically smoothed down with the help of this newly-developed polishing process. Nearly 70 μm solder bumps in height with two different profiles as square and circle on the substrates reach as flatly as ±3 μm between different substrates after reflow process; ±2.5 μm in single substrate; and even ±1 μm in die, respectively. Besides, surface roughness among the solder bumps is simultaneously narrowed down from Ra 0.6 to Ra 0.03 along with the coplanarity improvement. Excellent uniformity and smooth surface roughness in solder bumps are absolutely beneficial to pile up and deposit in the following steps in MEMS and semiconductor fields.     

Effects of pre-bump probing and bumping processes on eutectic solder bump electromigration

This paper investigates the electromigration reliability of flip chip packages with and without pre-bump wafer probing via high temperature operation life test (HTOL) using printed and electroplated bumps. Under bump metallization (UBM) of printed and electroplated bumps is a thin film of Al/Ni(V)/Cu and Ti/Cu/Ni, respectively, while the bump material consists of eutectic Sn/Pb solder. Current densities from 7380 to 20 100 A/cm² and ambient temperatures at 100, 125 and 150 °C are applied in order to study their impact on electromigration. The results reveal that the bump temperature has a higher influence than the current density when it comes to bump failures. The observed interconnect damage is from bumps with electrical current flowing upward into the UBM/bump interface (cathode). Identified failure sites and modes reveal structural damage at the region of the UBM and UBM/bump interface, in the form of solder voiding and cracking. The effects of current polarity, current crowding, and operation temperature are key factors to electromigration failures of flip chip packaging. The maximum allowable current density of the electroplated bumps is superior to the printed bumps by a factor of 3.0–3.7 times. Besides, the median time to failure (MTTF) of without-underfill packaging is preferred to that of with-underfill packaging by 1.5–2.2 times. Furthermore, the differences in MTTF between pre-bump and without pre-bump probing procedures are 2.0–19.4% and 1.6–10.3% for printed and electroplated bumps, respectively.     

倒装芯片热电极键合工艺研究

文章将论述一种无掩模制造细小焊料凸点技术。利用热电极键合工艺将带有凸点的倒装芯片焊到基板上。此项工艺能将间距小至40μm的倒装芯片组装到基板上。文章也论述了间距为40μm、电镀AuSn钎料凸点的倒装芯片组装工艺技术。金属间化合物相的形成对焊点可靠性有重要影响,尤其是对于细小焊点。文中研究了金属间化合物相的形成与增加对可靠性的影响。讨论分析了热循环和湿气等可靠性试验结果。     

形成倒装芯片焊点的铜接线柱焊凸(SBC)法

在倒装芯片应用中生长晶圆焊凸的工艺中对于间距较小(即小于150μm)、具有数个尺寸为150μm的焊凸,倒装前的焊锡涂敷好坏对产品的良率和可靠性起着重要作用。因为,如果涂敷的焊锡体积不均匀,就经不起涂敷过程中为确保涂敷在引线框上焊锡的完整和体积一致性而引入的强制视像系统检查,从而降低产出率。这就是一些组装工艺正设法减少或取消这些限制的原因。另一方面,采用直接熔化焊凸的方法来形成焊点是一种速度较快的工艺,但在保证回流处理后的离板高度方面有缺点,导致在温度和功率循环测试中的表现较差。介绍的采用铜接线柱焊凸(SolderBumponCopperStud;SBC)法解决了这些问题;对于那些需要倒装的组装工艺而言,这是可保障其制造性较佳的解决方案。介绍采用铜接线柱焊凸(SBC)工艺在附着在倒装芯片上的金属基片和焊凸之间形成焊点的新方法,利用铜接线柱焊凸技术再配合晶圆级的焊锡丝印工艺在半导体上预先形成焊凸。这是替代电镀焊凸工艺一种别具成本效益的方法。     

Effect of Gold Stud Bump Topology on Reliability of Flip Chip on Flex Interconnects

The flip chip technique using conductive adhesives have emerged as a good alternative to solder flip chip methods. Different approaches of the interconnection mechanism using conductive adhesives have been developed. In this paper, test chips with gold stud bumps are flip-chipped with conductive adhesives onto a flexible substrate. An experimental study to characterize the bonding process parameters is reported. Initial results from the environmental studies show that thermal shock test causes negligible failure. On the other hand, high humidity test causes considerable failure in flip chip on flex assemblies. Improvements in the reliability of the assembly are achieved by modifying the shape of the gold stud bumps.     

Using active thermography for defects inspection of flip chip

With the development of electronics towards smaller, more compact, and increasingly complex, flip chip technology has been used extensively in microelectronic packaging, and disadvantages occur in traditional detection methods. It is indispensable to explore new methods for flip chip solder joint inspection. In this paper we investigate an approach for solder joint inspection based on the active thermography. The basic principle of the active thermography method is described, and the experimental investigation is carried out using the method. The test flip chip is heated by a non-contact heating source. The thermal distribution on two kinds of chips is captured by an infrared thermal imager. With median filter and segmentation processes, positions of the bumps are segmented. For chips with smaller bumps, principal component thermography is introduced to enhance the segmentation process. The analysis results demonstrate that missing bumps in flip chips can be discerned obviously, which proves the feasibility of the proposed method for defects inspection of flip chips.     

Structural Modal Analysis for Detecting Open Solder Bumps on Flip Chips

Although flip chips have received wide acceptance as an integrated circuit package, significant manufacturing problems exist with the integrity of the connection between the package and the printed circuit board (PCB). Conventional X-ray, ultrasonic and electronic testing systems have been used to assess the integrity of this connection, however, none of these have proven suitable for detecting open solder bumps between the chip and the board. The inability to detect open solder bumps with traditional methods merits the investigation of new, nondestructive methods for detecting defects in a manufacturing environment. This work assesses the feasibility of monitoring the vibration characteristics of flip chips to detect open solder joints. Test vehicles with open solder joints were created, and a nondestructive laser ultrasonic system was used to measure the free vibration response of the chips attached to the printed circuit board. The algorithm of mode isolation (AMI) was applied to the vibration response data in order to extract the modal parameters of the chip. The statistical differences between the modal parameters of sets of damaged and undamaged chips were assessed, revealing the ability of the method to determine the location and severity of these defects in the presence of experimental scatter and manufacturing variation. The parameters of the first mode of vibration, especially its mode shape, were found to be much more sensitive to damage than those of a higher frequency mode.     

Application assessment of high throughput flip chip assembly for ahigh lead-eutectic solder cap interconnect system using no-flowunderfill materials

Flip chip on board (FCOB) is one of the most quickly growing segments in advanced electronic packaging. In many cases, assembly processes are not capable of providing the high throughputs needed for integrated surface mount technology (SMT) processing (Tummala et al, 1997). A new high throughput process using no-flow underfill materials has been developed that has the potential to significantly increase flip chip assembly throughput. Previous research has demonstrated the feasibility and reliability of the high throughput process required for FCOB assemblies. The goal of this research was to integrate the high throughput flip chip process on commercial flip chip packages that consisted of high lead solder balls on a polyimide passivated silicon die bonded with eutectic solder bumped pads on the laminate substrate interface (Qi, 1999). This involved extensive parametric experimentation that focused on the following elements: no-flow process evaluation and implementation on the commercial packages, reflow profile parameter effects on eutectic solder wetting of high lead solder bumps, interactions between the no-flow underfill materials and the package solder interconnect and tented via features, void capture and void formation during processing, and material set compatibility and the effects on long term reliability performance     

Investigation on flip chip solder joint fatigue with cure-dependent underfill properties

A cure-dependent viscoelastic constitutive relation is applied to describe the curing process of epoxy underfill in flip chip on board (FCOB). The chemical shrinkage of the epoxy underfill during the curing process is applied via incremental initial strains. Thus, the stress and strain build-up, caused by the simultaneous increase in stiffness and shrinkage during the curing process, are simulated. Accelerated fatigue experiments with thermal cycles from -55/spl deg/C to 80/spl deg/C are carried out for a specially designed flip chip configuration. Based on the obtained curing induced initial stress and strain fields, thermo-mechanical predictions are presented for the test carriers. The solder bumps are modeled with temperature dependent visco-plastic properties. A combination of a Coffin-Manson based fatigue relation and a creep fatigue model is used as fatigue failure criterion. The results show that the finite element method (FEM)-based fatigue life predictions match better with the experimental results, if the curing induced initial stress state is taken into account. The effect of cure-induced hydrostatic stress is qualitatively investigated by using a modified energy partitioning damage model with a correction factor in the creep damage formulation to take into account the effect of the hydrostatic stress.     

Reliability investigations of hard core solder bumps using mechanical palladium bumps and SnPb solder

The choice of solder joint metallurgy is a key issue especially for the reliability of flip-chip assemblies. Besides the metallurgical systems already widely used and well understood, new materials are emerging as solderable under bump metallization (UBM). For single chip bumping Pd stud bumps form a solid core under the solder layer. These hard core solder bumps are an adequate solution if single dies are available only and the chosen assembly technology is flip chip soldering. The scope of this paper is to summarize the results from aging of lead/tin solder bumps on palladium. The growth of intermetallic and its impact on the mechanical reliability are investigated.