Fabrication and characteristics of ion-implanted GaAs/GaAlAs integrated injection logic inverter

An integrated injection logic inverter has been realised in GaAs/GaAlAs material using ion implantation and Zn diffusion. Si ions have been implanted to merge the current source with the switching transistor, whereas the Be implantation provides the base contact. The shallow p+-emitter of the pnp current source has been fabricated by Zn diffusion. Instead of a lateral pnp transistor, which is typical in I2L technology, a vertical arrangement has been used. This type of transistor shows a better current efficiency and can be fabricated with a better uniformity in terms of base width. First results of an I2L inverter with a vertical pnp transistor are shown.     

A complementary DMOS-VMOS IC structure

A new complementary MOS structure has been fabricated consisting of a p-channel DMOS transistor and an n-channel double-diffused VMOS transistor. The transconductance of each transistor was between 0.85-0.98 of the theoretical gm. The threshold voltages have been adjusted by either ion implantation or by adjusting the diffusion profiles. The inverter operation is similar to that of standard CMOS.     

Double heterojunction GaAs/GaAlAs I2L inverter

GaAs/GaAlAs double heterojunction I2L inverters with a vertical pnp current source were fabricated by ion implantation and Zn-diffusion into LPE structures. The current gain of the upside-down-operated double heterojunction npn transistor has been improved by a factor of two compared to the gain of the npn transistor of the otherwise similar structure. In addition, the wide-gap junction pnp transistor gives a solution to the critical switch-on problem which can occur when a wide-gap emitter transistor is used for the switching transistor.     

Planar heterojunction bipolar transistor with an implanted base

A novel process to fabricate a planar emitter-up AlGaAs-GaAs heterojunction bipolar transistor HBT, has been developed relying on selective base implantation through the emitter and the heterojunction. The selective base definition means that all three transistor contacts can be made from the top surface, thereby making device integration easier because of the planar surface topology. This simple transistor fabrication process was examined using MOCVD material. Transistors with a DC current gain of 120 have been measured.<>     

离子注入技术现状与发展趋势

离子注入制程已成为器件设计的最前端工作．现在更被视为实现32nm和22nm晶体管制程的推动要素。器件漏电流、浅结面制作,器件尺寸缩小,以及急速增加成本的挑战,正在限制摩尔定律的延伸。针对32nm节点离子注入制程器件的工艺要求．介绍了离子注入设备的发展方向。     

An ion-implanted diamond metal-insulator-semiconductor field-effecttransistor

A p-type conducting layer has been formed in a substrate of semi-insulating natural diamond (type IIa) by boron implantation. Silicon dioxide was deposited over this layer to make an insulated-gate field-effect transistor. Saturation and pinch-off were both observed at room temperature. The transconductance was 3.9 μS-mm^-1 and the output conductance was 60 nS-mm^-1. This is the first reported use of ion implantation to successfully fabricate a field-effect device in diamond     

j-MOS transistors fabricated in oxygen-implanted silicon-on-insulator

The j-MOS transistor reported earlier has now been fabricated in silicon-on-insulator (SOI) prepared by oxygen ion implantation. Significant improvements in the drain breakdown voltage and off-state leakage current are attributed to a contoured gate oxide and to the quality of the SOI structure, respectively. The electron mobility in the channel silicon is 910 cm²/V . s and the minority-carrier lifetime is 3 µs. We conclude that the j-MOS transistor in SOI shows promise for controlling moderate power loads, particularly in dielectrically isolated power integrated circuit applications.     

A 22-nm damascene-gate MOSFET fabrication with 0.9-nm EOT and local channel implantation

We introduce a novel CMOS transistor fabrication technique using damascene gate with local channel implantation (LCI). This transistor has a benefit to reduce the resistance of source/drain extension (SDE) localizing the severe blanket channel implantation under the channel only. It can reduce the junction capacitance as well. This process technology is reliable for the formation of channel length down to 22 nm with smooth gate line edge roughness. Some unique processes for the small transistor fabrication are also introduced. The 22-nm nMOSFET with 0.9 nm RTO is achieved with the drive current of 930 /spl mu/A//spl mu/m for the off-current of 100 nA//spl mu/m at 1.0 V. Hot carrier reliability exceeding 10 years for 1.0 V operation is also obtained.     

An ion-implanted Schottky-barrier gate field-effect transistor

Techniques of fabricating an n-channel silicon field-effect transistor using phosphorus ion implantation and a platinum silicide Schottky-barrier gate (SB-FET) have been developed. The platinum silicide Schottky-barrier top gate is part of the contact metallization process. The phosphorus-doped channel is obtained by using a 50-keV ion-implanted predeposition and an 1100°C drive-in. A range of implantation doses and drive-in times were used to achieve various SB-FET characteristics. A threshold/pinchoff voltage range of +0.4 to -7.5 V has been obtained with typical spreads of approximately 0.1 V across the slice. A positive threshold voltage represents a SB-FET that is normally off and is turned on by a forward-biased gate. Results have been obtained for     

选择离子注入集电极技术研究

为提高超高速双极晶体管的电流增益 ,降低大电流下基区扩展效应对器件的影响 ,将选择离子注入集电区技术 (SIC)应用于双层多晶硅发射极晶体管中。扩展电阻的测试结果显示出注入的 P离子基本上集中在集电区的位置 ,对发射区和基区未造成显著影响。电学特性测量结果表明 ,经过离子注入的多晶硅发射极晶体管的电流增益和最大电流增益对应的集电极电流明显高于未经离子注入的晶体管。因此 ,在双层多晶硅晶体管中采用 SIC技术 ,有效地降低了基区的扩展效应 ,提高了器件的电学特性。     

Triple implant (In,Ga)As/InP n-p-n heterojunction bipolar transistors for integrated circuit applications

For the first time (In,Ga)As/InP n-p-n heterojunction bipolar transistors (HJBT's) applicable to integrated circuits have been fabricated by triple ion implantation. The base has been formed by beryllium ion implantation and the collector by silicon ion implantation. The implants were made into an LPE-grown n-n (In,Ga)As/InP heterostructure on an n+-InP substrate. This inverted mode emitter-down heterojunction transistor structure demonstrates to a maximum current gain of 7 with no hysteresis in the characteristics. The ideality factors of the IBversus VBE, and ICversus VBEcharacterisitics with VCB= 0, are 1.25 and 1.08, respectively, indicating that the defect level in the herterojunction is low and that minority-carrier injection and diffusion is the dominant current flow mechanism.     

AlGaAs/GaAs emitter-down HBT fabricated by MBE overgrowth

A planar emitter-down AlGaAs/GaAs heterojunction bipolar transistor (HBT) has been fabricated by a molecular beam epitaxy overgrowth of the n-GaAs collector on top of the base layer after the base layer was formed by beryllium implantation and rapid thermal annealing. The emitter down transistors fabricated by this process had DC current gains of 20, and ring oscillators gave a maximum switching speed of 250 ps/gate.<>     

400MHz,CW 300W VDMOS功率场效应晶体管

采用 Mo栅工艺技术降低栅串联电阻 ,通过优化工艺参数 ,全离子注入工艺 ,研制出了在 40 0 MHz下共源推挽结构连续波输出 30 0 W的高性能 VDMOSFET,其漏极效率大于 5 0 % ,增益大于 9d B。     

Oxide-isolated monolithic technology and applications

Describes the use of selective oxidation and ion implantation to fabricate integrated circuits. The technique of selective oxidation is used to fabricate a `walled emitter' structure as proposed by Panousis. This allows a substantial reduction in transistor size, for a given active area, over standard fabrication techniques. At the same time, parasitic device capacitances are reduced and a considerable improvement in circuit performance is realized. The impurity distribution in the various components is established by the extensive use of ion implantation. It has been demonstrated, experimentally, a 30-pJ resistor transistor-transistor logic gate fabricated using the collector diffusion isolation technology, can be fabricated in oxide isolated monolithic technology with a power-delay product of 6 pJ. Current-mode logic gates have been fabricated with a power-delay product of 1 pJ.     

SOI-LIGBT寄生晶体管电流增益的研究

采用二维器件模拟仿真软件Tsuprem4和Medici模拟了SOI-LIGBT的n型缓冲层掺杂剂量、阳极p+阱区长度、漂移区长度以及阳极所加电压对SOI-LIGBT寄生晶体管电流增益β的影响,通过理论分析定性的解释了产生上述现象的原因和机理,并且通过实验测试结果进一步验证了分析结论的正确性。其中,n型缓冲层掺杂剂量对电流增益β的影响最为明显,漂移区长度的影响最弱。基本完成了对SOI-LIGBT寄生晶体管电流增益β主要工艺影响因素的定性分析,对于SOI-LIGBT的设计有一定的借鉴意义。     

Oxygen implantation to suppress parasitic bipolar action in CMOS

Oxygen implantation and subsequent epitaxial silicon deposition have been developed to improve CMOS latchup prevention through reducing the current gains of parasitic bipolar transistors. The buried oxygen implanted layer is well confined, and defects do not extend into the epitaxial silicon layer. The device characteristics of the n- and p-MOSFETs fabricated on a wafer with the oxygen implantation are therefore not affected by the buried implanted layer. The oxygen implanted layer can reduce the minority-carrier lifetime and hence decrease the current gain of the lateral parasitic bipolar transistor. In addition, it introduces a potential barrier which decreases the current collected at the frontside contact of the vertical parasitic bipolar transistor. The common base current gain is reduced by 50% and 80% for the lateral and the vertical parasitic bipolar transistors, respectively. As a consequence, the CMOS latchup immunity is significantly improved     

Ion-implanted bipolar transistor carrier concentration profiles

The investigation of ion implantation as a dopant process for the fabrication of narrow base width (1000 Å) n-p-n microwave (5–10 GHz) bipolar transistors has been made. The performance of a bipolar transistor is intimately related to the impurity dopant distribution in the emitter and base regions of the device. Ionized impurity profiles have been determined by making Hall effect and resistivity measurements as a function of dopant layer thickness. The profiles of arsenic, phosphorus, and boron were investigated in this matter. The phosphorus layers were formed both by diffusion and implantation, while only ion implanted boron and arsenic layers were measured. The results obtained are presented.     

A high power MOSFET with a vertical drain electrode and a meshed gate structure

A MOSFET with a maximum power of 200 W in a 5/spl times/5 mm/SUP 2/ chip which exhibits 20-A current, 3000-millimho transconductance and 100-V breakdown voltage has been developed. The features of the device structure are a vertical drain electrode which makes it possible to use most of the surface area for the source electrode, and a meshed gate structure which realizes an increase in the channel width per unit area. The p-channel device with an offset gate structure was fabricated from an n on p/SUP +/ epitaxial wafer by using polysilicon gate and ion implantation processes. The device can be operated stably at ambient temperatures up to 180/spl deg/C. While the bipolar transistor is a suitable power device in the low voltage region, the MOSFET looks more promising in the high voltage region than the V-FET and the bipolar transistor.     

High speed integrated injection logic (I/SUP 2/L)

High speed integrated injection logic (I/SUP 2/L) circuits can be manufactured in a process using oxide separation involving a very thin epitaxial layer and ion implantation. Electronic improvements which decrease the charge storage in both the p-n-p and n-p-n transistor are discussed. Analytic expressions are derived which show the consequences for the minority charge stored in the base of the n-p-n transistor and for the influences on the current noise margin. A tradeoff between noise margin and speed is then made. Besides the reduction in delay time, another attractive aspect of this approach is that it allows a simple layout design. By using separate p-n-p and n-p-n transistors, the position of the n-p-n transistors can be adapted to the logic wiring because there is no limitation in the number of crossovers. Some experimental results are given. A minimum value of the propagation delay time of 3 ns has been measured.     

NMOS器件ESD特性模拟

NMOS管I-V曲线在ESD(electrostatic discharges)脉冲电流作用下呈现出反转特性,其维持电压VH、维持电流IH、触发电压VB、触发电流IB以及二次击穿电流等参数将会影响NMOS管器件的抗ESD能力。文章通过采用SILVACO软件,对1.0μm工艺不同沟长和工艺条件的NMOS管静电放电时的峰值电场、晶格温度以及VH进行了模拟和分析。模拟发现,在ESD触发时,增加ESD注入工艺将使结峰值场强增强,VH减小、VB减小,晶格温度降低;器件沟长和触发电压VB具有明显正相关特性,但对VH基本无影响。最后分析认为NMOS管ESD失效主要表现为高电流引起的热失效,而电场击穿引起的介质失效是次要的。