共查询到20条相似文献,搜索用时 15 毫秒
1.
Denorme S. Mathiot D. Dollfus P. Mouis M. 《Electron Devices, IEEE Transactions on》1995,42(3):523-527
Boron diffusion has been simulated in the context of a low thermal budget technology for thin-base integrated bipolar transistors. The simulation was performed using advanced physical models of diffusion, accounting for coupling with point defect diffusion. It has been found that in polysilicon emitter bipolar transistors, where the effect of the emitter implantation has the advantage of being suppressed, the excess point defects generated during the lateral extrinsic base implantations could still induce a nonnegligible broadening of the base and a shrinking of the active region. The influence of such parameters as the type of defects involved and their diffusion coefficient has been investigated 相似文献
2.
Babcock J.A. Schroder D.K. Huang W.-L.M. Ford J.M. 《Electron Devices, IEEE Transactions on》2001,48(5):956-965
Low-frequency (1/f) noise is characterized as a function of base current density (JB) on thin-film-silicon-on-insulator (TFSOI) lateral bipolar transistors. In the low injection region of operation, the noise power spectral density was proportional to JB 1.8 for JB<0.4 μA/μm2, which suggest that the noise in these devices is primarily dominated by a uniform distribution of noise sources across the emitter-base area. However in the high current region of operation (JB>0.4 μm2), the noise bias dependence shifts to JB 1.2, indicating current crowding effects, alter the contribution of noise sources near the extrinsic base link region of the device. In addition to the expected 1/f noise and shot noise, we have observed a bias dependent generation-recombination (Gm) noise source in some of the devices. This G/R noise is correlated to random-telegraph-signal (RTS) noise resulting from single trapping centers, located at or near the spacer oxide and/or the Si to SIMOX interface, which modulate the emitter-base space charge region 相似文献
3.
《Solid-State Circuits, IEEE Journal of》1985,20(6):1151-1157
Two bandgap references are presented which make use of CMOS compatible lateral bipolar transistors. The circuits are designed to be insensitive to the low beta and alpha current gains of these devices. Their accuracy is not degraded by any amplifier offset. The first reference has an intrinsic low output impedance. Experimental results yield an output voltage which is constant within 2 mV, over the commercial temperature range (0 to 70/spl deg/C), when all the circuits of the same batch are trimmed at a single temperature. The load regulation is 3.5 /spl mu/V//spl mu/A, and the power supply rejection ratio (PSRR) at 100 Hz is 60 dB. Measurements on a second reference yield a PSRR of minimum 77 dB at 100 Hz. Temperature behaviour is identical to the first circuit presented. This circuit requires a supply voltage of only 1.7 V. 相似文献
4.
This paper describes an improved lumped circuit model of power bipolar junction transistors (BJTs) that can predict the turn-off fall time to a greater accuracy than currently available models. Though the existing models simulate the storage time and delay time to a good accuracy, the fall time performance is neglected. This is because the existing models do not account for the charge decay due to recombination. The model presented in this paper is based on the charge dynamics of the device. The charge dynamics are explained in detail using simulation results from an advanced two-dimensional (2-D) device and circuit simulator. Based on a physical understanding of the charge dynamics, this model is implemented to incorporate the charge decay due to recombination to account for the current tail during turn-off. The lumped-circuit model is implemented in PSPICE using the existing quasisaturation model along with controlled sources. To validate the model, the device was subjected to hard- as well as soft-switching renditions (zero current switching and zero voltage switching). The modeled results are observed to have a good match with measured results 相似文献
5.
NPN and PNP lateral bipolar transistors having a base length shorter than 0.5 ?m have been made in thin (100 nm) silicon-on-insulator films. Current gains of 75 and 40 have been obtained in NPN and PNP devices, respectively. Measurements indicate a base generation lifetime of 1 ?s, and leakage currents of a fraction of a picoampere have been measured. The device fabrication is compatible with an SOI CMOS fabrication process. 相似文献
6.
We report buried oxide effects on the Silicon-On-Insulator Lateral Bipolar Transistor (SOILBT) performance by two-dimensional (2-D) numerical simulation and experiments. An early punchthrough is observed in SOILBT compared to the bulk due to the presence of buried oxide. In addition to dopant segregation into the buried oxide, the presence of buried oxide also diverts some electric field lines emanating from collector toward substrate, due to 2-D distribution of field, leaving fewer across the base region and hence increased depletion widths and punchthrough. One-dimensional (1-D) depletion approximation fails to predict this punchthrough. To establish the evidence of buried oxide induced punchthrough without dopant segregation effect, simple and yet novel measurement techniques are proposed to extract effective base width and base doping concentration near the buried oxide-silicon film interface using the parasitic MOSFET in SOILBT. Good agreement between 2-D simulation and experimental results was observed. Finally design curves are generated using 2-D numerical simulation for different base doping and buried oxide thicknesses on SOI substrates 相似文献
7.
In this paper, an attempt is made to derive a general analytical formulation for the current gain and emitter transit time of a polysilicon emitter bipolar transistor (BJT), which includes all previous models as particular cases. Firstly, it is shown that the minority-carrier injection and storage in the polysilicon region can be simply described by effective values of the minority-carrier diffusion length and mobility. These quantities are precisely defined, and depend on the microscopic transport properties of polysilicon grains and grain boundaries. Secondly, a general expression for the effective recombination velocity relative to the poly/mono interface is derived, which includes, and in some cases extends, all previous approaches. This results in a simple and general formulation which avoids some unnecessary simplification present in nearly all previous treatments, and allows easy comparison of the different models for the poly/mono interface and a clear assessment of the relevance of each physical mechanism. Finally, minority-carrier injection and storage in the single-crystal region is addressed. The effect of oxide breakup on both current gain and emitter transit time is also considered, and different models are compared 相似文献
8.
Zi-En Ooi Samarendra P. Singh Serene L.G. Ng Gregory K.L. Goh Ananth Dodabalapur 《Organic Electronics》2011,12(11):1794-1799
Lateral heterostructure field-effect bipolar transistors (LH-FEBTs) are thin-film transistors that have a distinct heterojunction located roughly midway between the source and drain contacts, with a p-type semiconductor on one side of the junction, and an n-type semiconductor on the other. These devices have potential in display applications but are relatively new to the research community. In this paper, we describe the fabrication of a hybrid LH-FEBT using pentacene and ZnO as the p- and n-type semiconductors, respectively, and describe its unusual bell-shaped electrical transfer characteristics. Using an equivalent circuit approach, we analyse quantitatively how the main features of the current–voltage curves relate to semiconductor properties such as carrier mobility and threshold voltage – information that is essential to the design of such devices. 相似文献
9.
《Electron Device Letters, IEEE》1986,7(12):652-654
The concept of partitioned-charge-based (PC) modeling of bipolar transistors is developed and demonstrated, and shown to be fundamentally superior to conventional quasi-static charge-control modeling, the basis of the common (capacitance-based) Gummel-Poon (GP) equivalent circuit. SPICE transient simulations with PC and GP models are contrasted to show a first-order accounting for non-quasi-static (NQS) delay in the PC model which is not accounted for in the GP model. Additional model contrasts in the small-signal domain, compared with exact ac solutions, confirm the superiority of the PC model, the characterization of which is in fact no more tedious than that of the GP model. 相似文献
10.
An approach for the analytical timing modeling of bipolar VLSI circuits that is based on average branch current analysis and the parametric correction scheme is presented. The combination of these techniques permits complex delay-sensitive effects of bipolar digital circuits to be incorporated in the derivation of the bipolar delay models. The delay functions of two basic bipolar subcircuit configurations (the series-gated structure and the emitter follower) are derived using the proposed techniques. It is shown that accurate timing information for the high-speed bipolar digital circuit, such as ECL, CML, and BiCMOS, can be obtained by repeated processing of these subcircuit delay functions. The delay estimates obtained with these timing models have been shown to be accurate typically within 10% of SPICE estimates. Applications include switch-level timing simulation, timing analysis and verification cell optimization, and technology mapping 相似文献
11.
The stress-induced leakage current is predominantly a Shockley-Read-Hall-like generation-recombination current. As the stress progresses, the leakage current increases, eventually reaches a maximum and then decays. The leakage current lowers the current gain at low biases. It affects the narrow-emitter transistors more since it is proportional to the emitter edge length. But, its impact is less significant if the transistor is operated at a high V be , as required by constant-current scaling. The loss of the current gain does not affect the circuit speed directly. Instead, it reduces the logic swing and thus the noise margin of the circuit. The design to absorb the degradation with a larger initial logic swing results in a speed penalty. The reverse-stress-induced junction degradation can be eliminated by properly designing the circuit There is no concern for emitter-coupled logic (ECL) circuits when the logic swing is less than the V be of the transistors 相似文献
12.
Improved digital/analogue conversion technique using currentsplitting in lateral bipolar transistors
Describes the use of multiple collector lateral bipolar transistors as precision current splitting elements suitable for use in high resolution monolithic D/A convertor design. Multiple collector structures result in better overall linearity and smaller chip area than previously suggested techniques. A six-bit convertor implemented on a linear bipolar semicustom array is used to demonstrate the advantages of this technique 相似文献
13.
Analytical expressions for the thermal resistance of bipolar transistors on bulk and SOI substrates are presented. The models are derived on the basis of intuitive physical pictures and validated by comparison with experimental data and three-dimensional (3D) device simulation. The effect of bulk and SOI substrates, shallow- and deep-trench isolation, and multiple emitter fingers is accounted for. All models are suitable for both hand calculations and computer-aided design 相似文献
14.
15.
Enhai Zhao Zeynep elik-Butler Frank Thiel Ranadeep Dutta 《Microelectronics Reliability》2004,44(1):89-94
1/f noise was measured on lateral bipolar PNP transistors over a temperature range of 220<T<450 K. Noise power spectral density measurements were performed simultaneously across two resistors connected in series with base and collector. The equivalent base current noise source SIB has two dominant components. One is SIBE that is between the base and the emitter, in parallel with rπ. The other is SIBC coming from the surface recombination current at the neutral base, between the base and the collector. The extracted SIB exhibited a near square law dependence on base current IB. The noise remained nearly constant when the temperature was below 310 K. However, it presented strong temperature dependence when the temperature was beyond 310 K. Two different models are proposed for the noise in different temperature regions. For the high temperature region, the surface recombination velocity fluctuation model is proposed, which indicates that the noise is coming from the fluctuations in the surface recombination velocity at the neutral base surface. The tunneling assistant trapping model is responsible for the low temperature region, where the noise source is the carrier trapping–detrapping by the defects in the spacer oxide covering the surface of the depletion layer. 相似文献
16.
The current transport mechanisms in double-heterojunction bipolar transistors, including the effects of conduction-band discontinuities of spikes, is analyzed. Two approaches, one based on the back-and-forth motion of electrons in the base between confining spikes and the other on the solution of the continuity equation in the base, are shown to be equivalent. The simplified derivation of the Ebers-Moll-like terminal current expressions ensures that the physical transport mechanisms have not been obscured. The general model is used to match the shape of device DC characteristics successfully by including separately measured parameters and adjusting other unknowns such as injection efficiency. A more complete model is possible by adding effects such as surface and bulk recombination through the emitter injection efficiency term and tunneling through an effective spike height. The physical effects resulting in collector-emitter offset voltages are also fully described and good agreement with experimental results is demonstrated 相似文献
17.
A computer solution is obtained for the voltage drop across a saturated transistor as a function of IC/IB, on the assumption that the emitter and collector currents may each be expressed as a superposition of three voltage-dependent terms. The result, showing good agreement with experiment, is a family of curves with the base current as the variable parameter. 相似文献
18.
The profound influence of Herbert Kroemer's ideas on the development of high-performance bipolar transistors is described. The historical context and subsequent development of innovations such as the drift base, achieved through concentration gradients and later with semiconductor bandgap grading, the use of wide bandgap emitters, concepts of collector-up transistors, and the introduction of new heterojunction materials, are reviewed 相似文献
19.
《Electron Device Letters, IEEE》1983,4(6):193-195
Thin-film lateral n-p-n bipolar transistors (BJT) have been fabricated in moving melt zone recrystallized silicon on a 0.5-µm silicon dioxide substrate thermally grown on bulk silicon. Current-voltage characteristics of devices with different base widths (5 and 10 µm) have been analyzed. The use of a metal gate over oxide covering the base region has allowed the devices to be operated as n-channel MOSFET's as well thus surface effects on device characteristics have been investigated under varying gate-bias voltages. Maximum dc current gain values of 2.5 were achieved with a 5-µm base width and values around 0.5 with a 10-µm base width. Higher gain values were impeded by onset of high-level injection which occurred at low currents because of light base doping of these devices. 相似文献
20.
The advanced bipolar transistor operating in the quasi-saturation region has been modeled, including collector current spreading effects. It is shown that the multidimensional collector current spreading, resulting from high carrier concentration gradient in the collector, ameliorates quasi-saturation effects in the d.c. and transient operation. The mechanism of collector spreading is investigated by physical device simulations. SPICE circuit simulations employing the collector spreading model are compared with measurements and are found to be in excellent agreement. 相似文献