A New Testability Calculation Method to Guide RTL Test Generation

Current paper presents a unified approach for calculating mixed-level testability measures. In addition, a new method of testability guided RTL Automated Test Pattern Generation (ATPG) for sequential circuits is introduced. The methods and algorithms are based on path tracing procedures on decision diagrams. The previous known methods have been implemented in test synthesis and in guiding gate-level test generation. However, works on application of testability measures to guide high-level test generation are missing. The main aim of this paper is to bridge this gap. Current method is compared to a recent approach known from the test synthesis area. Experiments show that testability measures greatly influence the fault coverage in RT-level test generation with the proposed approach achieving the best results. Similar to earlier works, our research confirms that RT-level fault coverage is in correlation with logic level one.This revised version was published online in March 2005 with corrections to the cover date.     

Design for Testability Techniques at the Behavioral and Register-Transfer Levels

Improving testability during the early stages of the design flow can have several benefits, including significantly improved fault coverage, reduced test hardware overheads, and reduced design iteration times. This paper presents an overview of high-level design methodologies that consider testability during the early (behavior and architecture) stages of the design flow, and their testability benefits. The topics reviewed include behavioral and RTL test synthesis approaches that generate easily testable implementations targeting ATPG (full and partial scan) and BIST methodologies, and techniques to use high-level information for ATPG.     

Behavioral Testability Insertion for Datapath/Controller Circuits

A method for test synthesis in the behavioral domain is described.The approach is based on the notion of adding a test behavior to the normal-mode design behavior. This testbehavior describes the behavior of the design in test mode. Thenormal-mode design behavior and test-mode test behavior are combinedand then synthesized by any general-purpose synthesis system toproduce a testable design with inserted BIST structures. The testbehavior is derived from the design behavior using testabilityanalysis based on metrics that quantify the testability of signalsand variables embedded within behaviors. The insertion method iscombined with a behavioral test scheme thatintegrates a) the design controller and test controller, b) testingof the entire datapath and controller. Examples show that when thetestability insertion procedure is used to modify a behavior beforesynthesis, the resulting synthesized physical implementation isindeed more easily tested than an implementation synthesized directlyfrom the original behavior.     

可测性度量的计算及研究

本文对ＳＣＯＡＰ可测性度量方法作了改进，提出了动态ＳＣＯＡＰ算法。此算法反映测试生成过程中系统和电路各节点可测性的变化，比静态ＳＣＯＡＰ更准确地描述了每个故障的可测性难度，为测试生成过程提供更有效的启发性信息。     

Incremental Testability Analysis for Partial Scan Selection and Design Transformations

This paper presents an efficient estimation method for incremental testability analysis, which is based partially on explicit testability re-calculation and partially on gradient techniques. The analysis results have been used successfully to guide design transformations and partial scan selection. Experimental results on a variety of benchmarks show that the quality of our incremental testability analysis is similar to those of the conventional explicit testability re-calculation methods and the technique can be used efficiently for improving the testability of a design during the high-level test synthesis and partial scan selection processes.     

Testability and test generation for majority voting fault-tolerant circuits

The testability of majority voting based fault-tolerant circuits is investigated and sufficient conditions for constructing circuits that are testable for all single and multiple stuck-at faults are established. The testability conditions apply to both combinational and sequential logic circuits and result in testable majority voting based fault-tolerant circuits without additional testability circuitry. Alternatively, the testability conditions facilitate the application of structured design for testability and Built-In Self-Test techniques to fault-tolerant circuits in a systematic manner. The complexity of the fault-tolerant circuit, when compared to the original circuit can significantly increase test pattern generation time when using traditional automatic test pattern generation software. Therefore, two test pattern generation algorithms are developed for detecting all single and multiple stuck-at faults in majority voting based circuits designed to satisfy the testability conditions. The algorithms are based on hierarchical test pattern generation using test patterns for the original, non-fault-tolerant circuit and structural knowledge of the majority voting based design. Efficiency is demonstrated in terms of test pattern generation time and cardinality of the resulting set of test patterns when compared to traditional automatic test pattern generation software.     

Interconnection optimization in data path allocation using minimal cost maximal flow algorithm

In most designs of digital systems, as the area taken up by multiplexers and wires outweighs that of functional modules and registers, the interconnection optimization in high-level synthesis becomes very significant. In this paper, a layout area estimation model based on bit-sliced standard cell design style is presented. With the model, a data path allocation system was developed to optimize the interconnection. Both the module allocation problem and the register allocation problem are modeled as the minimal cost maximal flow problem in a network. Experimental results show that the layout area estimation model is suitable to guide the design decisions during the allocation and good designs with optimal interconnections can be produced by the system.     

Finite state machine synthesis with fault tolerant test function

According to a recent synthesis for testability proposal, a test function specified as a finite state machine with the same number of state variables as the given object machine, is incorporated into the state diagram prior to synthesis. Since a complete verification of the test machine is not practical, an often used heuristic sets and observes each state variable. The two machines share logic and a fault can result in partial or total loss of the test function. We show that the tests generated under the assumption that the entire test function is intact can become invalid. We propose a new method of synthesizing PLA-based finite state machines with fault tolerant test machines. Our approach eliminates testing of the test function. A constrained logic minimization phase insures that faults have predictable effect on the state diagram of the composite machine (object machine embedded with the test function). This allows effective use of the test function during test generation even in the presence of faults that effect both object and test machines. Only a combinational test generator is required for test generation. Each combinational vector is augmented by appropriate initialization and propagation sequences. Unlike prior approaches, ourO(log₂ n) length test sequence isguaranteed to detect any targeted crosspoint fault. Experimental results on the MCNC Logic Synthesis Workshop finite state machine benchmark set are given as evidence of practicality of the proposed approach.Supported by C&C Research Laboratories, NEC USA, during summer 1991.     

The optimistic update theorem for path delay testing in sequential circuits

For sequential circuit path delay testing, we propose a new update rule for state variables whereby flipflops are updated with their correct values provided they are destinations of at least one robustly activated path delay fault. Existing algorithms in the literature, for robust fault simulation and test generation, assign unknown values to off-path latches that have non-steady signals at their inputs in the previous vector. Such procedures are pessimistic and predict low fault coverages. They also have an adverse effect on the execution time of fault simulation especially if the circuit has a large number of active paths. The proposed update rule avoids these problems and yet guarantees robustness.     

An efficient built-in self test method for robust path delay fault testing

Single Input Change (SIC) testing has been proposed for robust path delay fault testing. In this letter a new Built-In Self Test (BIST) method for SIC vector generation is presented. The proposed method compares favourably to the previously proposed methods for SIC pattern generation with respect to hardware overhead and time required for completion of the test.     

Exploiting Behavioral Information in Gate-Level ATPG

This paper aims at broadening the scope of hierarchical ATPG to the behavioral-level. The main problem is identified, namely the mismatch of timing models between the behavioral- and gate-levels. As a main contribution of this paper, a theoretical analysis of this problem led to the definition of a novel concept, that of dominated patterns, that captures the needed link between the levels. Some metrics are defined, taken from the software realm, that allow generation of test patterns at the behavioral-level. To validate the concept correctness, different ATPG systems are presented, and experimental results show an improvement in the test quality, thanks to the exploitation of behavioral-level information.     

Partial scan and symbolic test at the register-transfer level

This paper presents a partial scan methodology suited for (pipelined) data paths described at the Register-Transfer level. The method is based on feedback elimination by making existing registers scannable or by adding extra transparent scan registers An optimal set (in terms of area cost) of scan registers is selected using an exact branch and bound algorithm. This approach can deal with complex realistic data paths requiring orders of magnitude lower CPU times than gate devel techniques. Furthermore, our symbolic test pattern generation technique can very effectively deal with the delay in the remaining acyclic sequential circuit parts. This symbolic test method makes various scan schemes possible which ensure a correct assembly and application of the test vectors. They are discussed and compared in terms of hardware requirements, test application times and test accuracy.     

A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis

This paper presents a partitioned and embedded BIST technique for data path like circuits. The BIST scheme is defined at behavioral level for full optimization of both system and BIST modes during High Level Synthesis. Test time, area overhead and fault coverage are under the scope of the method. User-given constraints on fault coverage to achieve on data path operators and on test time are used to guide the BIST insertion technique towards the lowest area overhead solution.     

数据通路的并发差错检测技术

随着芯片密度的不断增加和对可靠性要求的不断提高,嵌入式系统的容错设计越来越受到关注。直接的复制比较策略将导致大量的硬件开销,而实现故障保险的数据通路可以增加硬件的共享。文章对近年来数据通路的RTL级的并发差错检测技术进行了分析和比较;研究结果表明,故障保险的方法和内省方法应该是优先考虑的并发差错检测方法．而半并发蔗错检测方法和算法级重计算方法主要应用于对硬件要求严格,而对时间和差错检测能力要求较低的时候。     

Trade-offs in scan path and BIST implementations for RAMs

In this article we propose efficient scan path and BIST schemes for RAMs. Tools for automatic generation of these schemes have been implemented. They reduce the design effort and thus allow the designer to select the more appropriate scheme with respect to various constraints.     

Performance analysis for the dynamic virtual path bandwidth control method in ATM networks

Broadband ISDN (integrated services digital network) should provide various kinds of communication services for multimedia traffic, including voice, computer data, still picture and motion video, and an ATM (asynchronous transfer mode) technology is expected to satisfy those demands. In ATM networks, a VP (virtual path) concept is introduced for simplifying the network resource management. However, if the bandwidth of each VP is fixed, it cannot absorb traffic load fluctuation. In this case, it is likely to happen that one VP has no remaining bandwidth while other VPs on the same physical link have free capacities. Another extremity is that a VP is not introduced, and that all VCs along the same physical link share the whole bandwidth of the link. This can achieve an efficient use of the link, but it apparently requires complicated call set-up procedures. In this paper, we propose a new dynamic VP bandwidth control method, in which the bandwidth allocated to each VP is dynamically changed according to traffic fluctuation. More specifically, in the case that multiple VPs are multiplexed on the same link between two nodes, when the utilization of some VP is increased, that VP requests an additional bandwidth. When the traffic load becomes low and the utilization of a VP is decreased, a part of the assigned bandwidth is released. We consider two methods for this purpose; one is the basic method in which the bandwidth increase request is issued after the VP bandwidth is exhausted. The other is the look-ahead method where the bandwidth increase is requested in advance before the bandwidth starvation. An approximate analysis for the above methods is provided, and the validation of its accuracy is assessed by comparing with simulation results. Through numerical examples, we show that our methods can provide performance improvement in terms of call loss probabilities of each VP.     

浅析KYN28A-12高压开关柜预防性试验过程应注意的问题

本文对KYN28A-12高压开关柜试验过程发现的问题进行分析,并提出相应的解决措施.     

Reducing Test Time in the High-Volume Production of Analog Circuits using Efficient Test-Vector Generation and Interpolation Techniques

Test cost is one of the main factors determining the profit margin of a device in production. Current test strategies require hundreds of measurements to determine the specifications of a parameter. In this paper, we present an automatic test-vector generation technique that is based on transfer function manipulation and requires only one circuit simulation. The proposed method consists of generating the first set of vectors by applying a derivation technique to the golden transfer function of the circuit under test (CUT). An interpolation technique allows a new transfer function to be constructed based on the first set of test vectors. The difference between the reconstructed transfer function and the golden transfer function is used to select the second set of test vectors. These new test vectors are selected to achieve the best possible fit. Our technique reduces the test vector size to values that at present can be achieved only by using powerful and time-consuming fault simulation tools. As an example, we apply the method to state variable and Chebyshev filters. We also compute the fault coverage in order to demonstrate the effectiveness of this new technique.