互阻抗放大器的设计

大多数工程师都知道,设计互阻抗放大器需要一个足够大的电阻,以把输入电流转换成一个在合理范围内的输出电压。为了使电路稳定,需要在反馈电阻上并联一个足够大的电容。本文将说明在确保互阻抗放大器具有尽可能大的带宽以及保证系统稳定的情况下,如何计算反馈电容值。     

放大器输入保护的利与弊

当今的许多高速运算放大器都具有片上输入保护.在大多数情况下,这种保护对用户是透明的.但在某些应用中,这种保护可能是电路的致命弱点.本文讨论输入保护需求、实现及其潜在的缺点,本文还给出利用具有输入保护功能放大器的替代方案与电路方案.     

I/V特性扫描在静电放电试验中的应用

随着超大规模集成电路工艺的高速发展,特征尺寸越来越小,而静电放电(Electrostatic Discharge)对器件可靠性的危害变得越来越显著。因此,静电放电测试已经成为对器件可靠性评估的一个重要项目。I/V特性扫描是静电放电试验中必不可少的一环。文章介绍了I/V特性扫描的目的、波形、程序、扫描过程中遇到的问题和应用。     

负载阻抗变动对放大器动特性的影响

上一期已经就扬声器的阻抗变化对放大器的驱动电压和驱动频率特性的影响作了分析。这一回介绍通过测量冲击脉冲响应和累积频谱．了解负载阻抗的变化对放大器动特性的影响．以及真空管放大器与晶体管放大器的差异。     

TE电路保护部推出面向各种高数据速率应用的、业界最低电容的硅静电放电保护器件

TEConnectivity旗下的一个业务部门TE电路保护部发布一个系列8款全新的单，多通道硅静电放电（SESD）保护器件，可提供市场上最低的电容（双向：典型值为0．10pF，单向：典型值为0．20pF）、最高的ESD保护（20kV空气放电和接触放电）和最小尺寸封装（多通道：最小的直通外形尺寸、厚度为0．31mm）。     

高阻抗微弱信号测量的保护电路设计

针对高阻抗微弱信号测量问题,对测量精度与系统输入阻抗、输入偏置电流的关系进行分析,应用保护技术设计了带保护电路的测量电路,将电路中的低阻抗节点加上保护电势,减小漏电流的影响.通过PSpice仿真分析,验证保护电路能提高测量系统的输入阻抗和降低输入偏置电流,结果表明保护电路技术能实现对高阻抗微弱信号的高精度测量.     

一种基于BiFET工艺的高输入阻抗运算放大器

针对CMOS运算放大器存在的输入失调电压高、噪声性能差等问题,提出了一种基于双极结型场效应晶体管(BiFET)工艺的高输入阻抗运算放大器。采用P沟道JFET差分对作为输入级,实现了pA量级的极低输入偏置电流/失调电流和nV/Hz量级的极低输入噪声电压谱密度。采用双极晶体管构成的共集-共射增益级和互补推挽输出级,实现了100 dB的开环增益、10 V/μs的输出电压转换速率和10 MHz的带宽。该运算放大器适用于对微弱模拟信号的采集和放大。     

集成独特保护功能的全新基站放大器

TQP7M9101和TQP7M9102作为TriQuint新基站器件系列，功耗极低，且可保护移动网络免受系统断电和服务故障的影响。这些放大器与目前市面上的其他产品的不同之处在于它们采用了集成式保护功能，包括防止静电放电和直流电超压故障的方法。TriQuint还集成了射频过激保护功能，     

采用SOT-23封装的低成本36V电流检测放大器具有高精确度

凌力尔特公司(Linear Technology Corporation)推出低成本高端电流检测放大器LT6106,该器件可以从高达36V的共模电压中分辨小的差分信号。LT6106的输入失调电压仅为250μV (最大值),满标度差分输入为500mV,具有2000:1的动态范围。其输入偏置电流保证不高于40nA,基本消除了偏置电流成为误差源的问题。为了应对故障情况,LT6106可以承受高达44V的共模电压,并可以在3.5μs之内响应信号变化。-40℃至125℃的工作温度范围使得LT6106非常适用于工业和汽车应用,如电源管理、运动控制和     

ST推出超大带宽的HDMI接口静电放电保护芯片

日前，意法半导体再次扩大该公司的超低电容的高清视频产品保护IC产品组合。新产品允许高清多媒体接口（HDMI）在1．65Gbit／s的标准速率甚至最高3．2Gbit／s速率下具有高达15kV的人体接触和空气静电放电（ESD）保护功能。新产品HDMIULC6—4SC6是当前市场上带宽最大的（超过5GHZ）单片专用保护芯片，可为4条数据线路提供轨到轨的保护，而且不会破坏数据信号的完整性。     

A thyristor-only input ESD protection scheme for CMOS RF ICs

We propose an input protection scheme composed of thyristor devices only avoiding usage of a clamp NMOS device to minimize the area consumed by an input pad structure in CMOS RF ICs. For this purpose, we suggest low-voltage triggering thyristor protection device structures assuming usage of standard CMOS processes, and attempt an in-depth comparison study with a conventional thyristor protection scheme incorporating a clamp NMOS device in the input pad. The comparison study mainly focuses on robustness against the human body model electrostatic discharge (HBM ESD) in terms of peak voltages applied to gate oxides in an input buffer and lattice heating inside protection devices based on DC and mixed-mode transient analyses utilizing a 2-dimensional device simulator. We constructed an equivalent circuit for the input HBM test environment of the CMOS chip equipped with the input ESD protection devices, and by executing mixed-mode simulations including up to four protection devices and analyzing the results for five different test modes, we attempt a detailed analysis on the problems which can occur in real HBM tests. We figure out strength of the proposed thyristor-only protection scheme, and suggest guidelines relating the design of the protection devices and circuits.     

ESD protection design for mixed-voltage I/O buffer with substrate-triggered circuit

A substrate-triggered technique is proposed to improve the electrostatic discharge (ESD) robustness of a stacked-nMOS device in the mixed-voltage I/O circuit. The substrate-triggered technique can further lower the trigger voltage of a stacked-nMOS device to ensure effective ESD protection for mixed-voltage I/O circuits. The proposed ESD protection circuit with substrate-triggered design for a 2.5-V/3.3-V-tolerant mixed-voltage I/O circuit has been fabricated and verified in a 0.25-/spl mu/m salicided CMOS process. The substrate-triggered circuit for a mixed-voltage I/O buffer to meet the desired circuit application in different CMOS processes can be easily adjusted by using HSPICE simulation. Experimental results have confirmed that the human- body-model (HBM) ESD robustness of a mixed-voltage I/O circuit can be increased /spl sim/60% by this substrate-triggered design.     

A low-voltage triggering SCR for on-chip ESD protection at outputand input pads

A novel silicon-controlled rectifier (SCR) structure for on-chip protection against electrostatic discharge (ESD) stress at output or input pads is presented. The SCR switches to an ON state at a trigger voltage determined by the gate length of an incorporated nMOS-like structure. Thus, the new SCR can be designed to consistently trigger at a voltage low enough to protect nMOS transistors from ESD. The capability of a protection circuit using the new SCR design is experimentally demonstrated. The tunability of the SCR trigger voltage with reference to the nMOS breakdown voltage is exploited to improve the human body model (HBM) ESD failure threshold of an output buffer from 1500 to 5000 V     

ESD protection for CMOS output buffer by using modified LVTSCRdevices with high trigger current

Modified designs of the low-voltage triggering semiconductor-controlled rectifier (LVTSCR) devices with high trigger current are proposed to protect the CMOS output buffer against electrostatic discharge (ESD) events in submicrometer CMOS technologies. The high trigger current is achieved by inserting the bypass diodes into the structures of the modified PMOS-trigger lateral SCR (PTLSCR) and NMOS-trigger lateral SCR (NTLSCR) devices, these modified PTLSCR and NTLSCR devices have a lower trigger voltage to effectively protect the output transistors in the ESD-stress conditions, but they also have a higher trigger current to avoid the accidental triggering due to the electrical noise on the output pad in the normal operating conditions of CMOS IC's. Experimental results have verified that the trigger current of the modified PTLSCR (NTLSCR) is increased up to 225.5 mA (218.5 mA). The noise margin to the overshooting (undershooting) voltage pulse on the output pad, without accidentally triggering on the modified NTLSCR (PTLSCR), is more than VDD+12 V (VSS-12 V)     

TLP analysis of 0.125 μm CMOS ESD input protection circuit

In this investigation, TLP ESD analysis shows that if a large input resistor is used in combination with a secondary ggNMOS clamp in the input protection circuitry, then the trigger voltage, V_t1, of the ggNMOS clamp is not a constant. The value is influenced by the size and properties of the input resistor, by current injection problems due to parallel resistive networks formed between the primary and secondary ESD circuits, by reverse bias diode leakage currents effects, and by source elevation effects due to voltage rises along the ESD ground bus.     

Complementary-SCR ESD protection circuit with interdigitatedfinger-type layout for input pads of submicron CMOS IC's

A new ESD protection circuit with complementary SCR structures and junction diodes is proposed. This complementary-SCR ESD protection circuit with interdigitated finger-type layout has been successfully fabricated and verified in a 0.6 μm CMOS SRAM technology with the LDD process. The proposed ESD protection circuit can be free of VDD-to-VSS latchup under 5 V VDD operation by means of a base-emitter shorting method. To compensate for the degradation on latching capability of lateral SCR devices in the ESD protection circuit caused by the base-emitter shorting method, the p-well to p-well spacing of lateral BJT's in the lateral SCR devices is reduced to lower its ESD-trigger voltage and to enhance turn-on speed of positive-feedback regeneration in the lateral SCR devices. This ESD protection circuit can perform at high ESD failure threshold in small layout areas, so it is very suitable for submicron CMOS VLSI/ULSI's in high-pin-count or high-density applications     

ESD protection design on analog pin with very low input capacitancefor high-frequency or current-mode applications

An electrostatic discharge (ESD) protection design is proposed to solve the ESD protection challenge to the analog pins: for high-frequency or current-mode applications, By including an efficient power-rails clamp circuit in the analog input/output (I/O) pin, the device dimension (W/L) of an ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (μm/μm) in a 0.35-μm silicided CMOS process, but it can sustain the human body model (HBM) and machine model (MM) ESD level of up to 6 kV (400 V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only ~1.0 pF (including the bond-pad capacitance) for high-frequency applications     

Adaptive-biased buffer with low input capacitance

A new analogue buffer, which is a differential-pair-based level shifter followed by an adaptive-biased cascode source follower, is proposed. The structure exhibits low input capacitances, enhanced slew rate, high bandwidth and low distortion. The simulated results have shown input capacitance of 99.5 fF at 1 MHz, slew rate of 55.5 V/μs, -3 dB bandwidth of 37.9 MHz, and THD less than 1% for 1 Vpp input signal up to 6 MHz at a 100 kΩ//15 pF load. The buffer consumes 2.4 mW at 5 V supply in a 0.8 μm n-well CMOS technology     

Pin-pin ESD protection for electro-explosive device under severe human body ESD

Electrostatic discharge (ESD) may introduce huge damages to electro-explosive devices (EEDs). This paper studies the pin-pin ESD protection for EED under server human body ESD. We use the PSpice and MATLAB to simulate the ESD of EED protected with transient voltage suppressor (TVS), varistor, semiconductor arrester and capacitance. Moreover, we achieve the decay time, current waveforms, voltage waveforms and energy integration waveforms of the EED during the ESD, with different protections. Simulation results reveal that TVS succeeded in protecting bridgewire EED against the pin-pin ESD, while other three did not provide adequate protection. The pin-pin ESD experiments have been performed using the TVS and varistor. Experimental results show that, using the TVS protection, the EED is not firing under the severe 50 kV ESD voltage. However, by using varistor protection, the ESD protection capability increases by more than 90%, while the protection capability only enhances by 3.1%. The response time of the TVS, i.e. 10^− 12 s, is much faster than that of the varistor, i.e. 10^− 8 s.     

多指条nMOSFET抗ESD设计技术

利用多指条nMOSFET进行抗ESD设计是提高当前CMOS集成电路抗ESD能力的一个重要手段，本文针对国内某集成电路生产线，利用TLP(Transmission Line Pulse)测试系统，测试分析了其nMOSFET单管在ESD作用下的失效机理，计算了单位面积下单管的抗ESD(Electro Static Discharge)能力，得到了为达到一定抗ESD能力而设计的多指条nMOSFET的面积参数，并给出了要达到4000V抗ESD能力时保护管的最小面积，最后通过ESDS试验进行了分析和验证。