VHDL─A:VHDL的扩展

VHDL作为数字系统的硬件描述语言已应用多年，并取得了成功。对于模拟系统尚没有一种IEEE标准的硬件描述语言问世，本文介绍正在标准化进程中的模拟硬件描述语言VHDL─A，该语言是VHDL的扩展，在VHDL的基础上加入了可描述模拟系统的对象、类型和结构。     

用VHDL实现多媒体通信复接设备

介绍了ＶＨＤＬ（ＶＨＳＩＣ ｈａｒｄｗ ａｒｅｄｅｓｃｒｉｐｔｉｏｎ ｌａｎｇｕｇｅ） 的优越性和以ＶＨＤＬ开发多媒体通信中ＩＣ（ｉｎｔｅｇｒａｔｅｄ ｃｉｒｃｕｉｔ） 的一个实例,并总结了一些应用ＶＨＤＬ的经验     

DES算法的S盒的设计优化

DES(数据加密标准)算法被广泛应用于软件加密和硬件加密。S盒是DES算法中的一个关键环节,它的设计好坏直接影响DES的加密性能。VHDL(甚高速集成电路硬件描述语言)是借助EDA(电子设计自动化)工具进行硬件设计的基本描述语言。文中结合VHDL的特点,对使用VHDL设计S盒进行了一些分析,综合速度、资源利用率等提出了最优方案。     

VHDL语言在数字电路教学中的探讨

指出了电类专业的学生，应该熟悉掌握VHDL语言，探讨了把硬件描述语言引入数字电路教学首先要向学生介绍VHDL语言设计的基本内容，然后要求学生完成一个VHDL语言的综合设计。实践表明，这种方法有助于克服学习VHDL语言中的一些难点。     

模拟/混合信号HDL的应用与发展

目前 ,在数字硬件设计全过程中 ,类似于 VHDL的硬件描述语言 (HDL)已能支持系统仿真、综合、测试和形式验证等大多数设计步骤。然而 ,模拟 CAD工具还没有相应的硬件描述语言的支持 ,这主要是由模拟电路的多样性和复杂性决定的。本文详细介绍了模拟 /混合信号系统的硬件描述语言—— VHDL - AMS,并通过实例进行说明     

基于VHDL的数字逻辑电路设计

分析了硬件描述语言VHDL的特点、结构和描述;说明了基于VHDL进行数字逻辑电路设计的方法;结合实例介绍了VHDL在数字逻辑电路设计中的应用方法。     

基于VHDL逻辑电路设计与应用

随着集成电路技术的高速发展,VHDL已成为设计数字硬件时常用的一种重要手段。介绍EDA技术及VHDL语言特点,以串行加法器为例,分析串行加法器的工作原理,提出了一种基于VHDL语言的加法器设计思路,给出串行加法器VHDL源代码,并在MAX PLUSII软件上进行仿真通过。     

VHDL 电路结构优化设计探讨

VHDL作业一种通用的硬件描述语言,在电路设计中被广泛使用。本文探讨了VHDL电路设计的优化方法。     

Designing Run-Time Reconfigurable Systems with JHDL

Run-time reconfigurable (RTR) systems are FPGA-based systems that reconfigure FPGAs during execution to alter hardware organization and composition to meet the varying needs of applications as they execute. These systems are difficult to describe with conventional tools (schematic capture, VHDL synthesis, etc.) because most tools assume that the underlying hardware organization is static. JHDL is a Java-based design environment capable of describing, netlisting, simulating and executing complex, dynamic RTR systems. Using conventional Java syntax, users describe hardware structures as objects; as these hardware-object constructors are invoked, JHDL automatically configures hardware circuits onto FPGA hardware, thus directly supporting the dynamic nature of RTR systems with standard language constructs. JHDL also supports codesign of the software and hardware parts of the system; in other words, the entire application can be described in a single piece of Java code that can be co-simulated/co-executed with the FPGA hardware. To date, RTR design with JHDL has focused on the development of automated target recognition (ATR) systems, and working systems described in JHDL have been demonstrated.     

An Overview of a Compiler for Mapping Software Binaries to Hardware

As new applications in embedded communications and control systems push the computational limits of digital signal processing (DSP) functions, there will be an increasing need for software applications to be migrated to hardware in the form of a hardware-software codesign system. In many cases, access to the high-level source code may not be available. It is thus desirable to have a technology to translate the software binaries intended for processors to hardware implementations. This paper provides details on the retargetable FREEDOM compiler. The compiler automatically translates DSP software binaries to register-transfer level (RTL) VHDL and Verilog for implementation on field-programmable gate arrays (FPGAs) as standalone or system-on-chip implementations. We describe the underlying optimizations and some novel algorithms for alias analysis, data dependency analysis, memory optimizations, procedure call recovery, and back-end code scheduling. Experimental results on resource usage and performance are shown for several program binaries intended for the Texas Instruments C 6211 DSP (VLIW) and the ARM 922 T reduced instruction set computer (RISC) processors. Implementation results for four kernels from the Simulink demo library and others from commonly used DSP applications, such as MPEG-4, Viterbi, and JPEG are also discussed. The compiler generated RTL code is mapped to Xilinx Virtex II and Altera Stratix FPGAs. We record overall performance gains of 1.5-26.9 for the hardware implementations of the kernels. Comparisons with the power aware compiler techniques (PACT) high-level synthesis compiler are used to show that software binaries can be used as intermediate representations from any high-level language and generate efficient hardware implementations.     

VHDL设计电路优化探讨

CPLD／FPGA设计越来越复杂，使用硬件描述语言设计可编程逻辑电路已经被广泛采用。在应用VHDL语言开发的过程中注意综合质量优化也显得日益重要。文中对应用VHDL时优化其综合质量给出了几点探讨。     

基于CPLD的数字系统设计

介绍了应用可编程逻辑器件CPLD及硬件描述语言VHDL设计数字系统的方法,说明基于CPLD器件进行数字系统设计的特点、VHDL设计流程,重点介绍了在数字系统设计中,采用CPLD设计是一种基于芯片的、层次化、自顶向下的方法。以数字频率计设计为例,说明基于可编程逻辑器件的数字系统设计的方法。     

二维DWT／IDWT处理器的VLSI设计

在本文中，我们设计了基于多分辨分析，适合于硬件实现的二维ＤＷＴ和ＩＤＷＴ实时系统，采用了ｔｏｐ－ｄｏｗｎ的ＶＬＳＩ设计方法，用硬件描述语言ＶＨＤＬ，在Ｓｙｎｏｐｓｙｓ系统中进行了验证和综合，综合结果表明：系统的规模为７１４０单元面积，对于四层信小波变换，数据处理速度约可达到４Ｍｐｉｘｅｌ／ｓ。     

VHDL语言在数字电路实验中的应用

传统数字电路实验通常采用TTL或CMOS芯片,不能满足现代数字系统设计的要求。而应用VHDL的数字电路实验降低了数字系统的设计难度,因而应用更加广泛。通过介绍VHDL语言及VHDL语言的程序结构和设计流程,以数字钟为例描述VHDL语言设计数字电路模块化、自顶向下的设计方法,从而说明VHDL语言在数字电路实验中的优点,对实验教学有一定的指导作用。     

基于VHDL实现的自动售货机芯片设计

VHDL语言是一种功能强大应用广泛的数字电路硬件描述语言,运用该语言进行集成电路芯片设计可以在不涉及具体电路情况下对集成电路芯片进行模块化设计并详细规定各个单元电路模块功能。此设计使用VHDL语言实现了一种自动售货机芯片,该芯片能够设定多种商品和货币的交易模式,并智能精确地完成交易过程。经MAXPLUS II进行仿真实验表明该设计具有设计全面、功能完善、交易准确等特点,达到了设计要求。