Fabrication of self-aligned graded junction termination extensions with applications to 4H-SiC P-N diodes

The properties of SiC make this wide band-gap semiconductor a promising material for high power devices. This potential is demonstrated in various devices, such as p-n diodes, Schottky diodes, bipolar junction transistors, thyristors, etc., all of which require adequate and affordable termination techniques to reduce leakage current and increase breakdown voltage in order to maximize power-handling capabilities. In this paper, we describe a technique for fabricating a graded junction termination extension (GJTE) that is effective and self-aligned, a feature that simplifies the implantation process during fabrication and, therefore, has the potential to reduce production costs. Implanted anode p-n diodes fabricated using this technique on 10-μm thick n⁻ epitaxial layer had a maximum breakdown voltage of 1830 V. This was comparable to the ideal parallel-plane breakdown of 1900 V predicted by numerical simulation.     

High-voltage planar p-n junctions

A concentric ring junction has been devised to prevent surface breakdown of a planar junction. By properly choosing the spacing between the main junction and the ring, the ring junction acts like a voltage divider at the surface. In addition, the ring junction minimizes the effect of the junction curvature at the periphery of a planar junction. Devices fabricated with three such rings showed breakdown voltages of 2000 and 3200 volts on n-type silicon with impurity concentrations 6.5 × 10¹³and 2.5 × 10¹³cm^-3, respectively. That the structure operated as proposed was corroborated by comparison of the reverse leakage current with a one parameter fit to a theoretically calculated current obtained from the approximated volume of the space charge regions. These results together with the photo response measurements indicate that the field-limiting ring junction can be used successfully to obtain high-voltage planar p-n junctions.     

4H-SiC混合PN/Schottky二极管的研制

报道了4H-SiC混合PN/Schottky二极管的设计、制备和特性．该器件用镍作为肖特基接触金属,使用了结终端扩展（JTE）技术．在肖特基接触下的n型漂移区采用多能量注入的方法形成P区而组成面对面的PN结,这些PN结将肖特基接触屏蔽在高场之外,离子注入的退化是在1500℃下进行了30min．器件可耐压600V,在600V时的最小反向漏电流为1×10-3A/cm2．1000μm的大器件在正向电压为3V时电流密度为200A/cm2,而300μm的小尺寸器件在正向电压为3.5V电流密度可达1000A/cm2．     

关于雪崩结开启电压和关断电压差别的研究

本文详细研究了雪崩结导通电压和关断电压的差别。 当结特征尺度在微米量级时,这个差别将不能忽略, 这个结果与现有报道不一致,并且对对器件参数的正确表征有较大影响。 实验发现当结面积变小时, 这个差别将增大。 本文对该现象进行了分析, 给出了理论解释,认为这个现象是由于结导通的阈值增益随着结面积的减小而增加的缘故。在雪崩渐近电流公式中, 所谓的“击穿电压”实际上应该是雪崩结关断电压。 修正了传统的关于雪崩渐近电流和盖革模式雪崩光电二极管的增益公式。     

A theory of voltage breakdown of cylindrical P-N junctions, with applications

In certain p-n junctions, such as those made by the alloy method, edges on the junction surface will, by field concentration, lead to lower inverse breakdown voltages than would otherwise be obtained. These edges are approximated by pieces of circular cylinders, and a formula for the voltage breakdown of a circular cylindrical junction obtained. The results agree qualitatively with those found for certain alloy-type diodes.     

双极RF功率管的深阱结终端

给出了双极 RF功率管新的深阱结终端结构 .模拟分析表明 ,具有优化宽度、优化深度且填充绝缘介质的深阱结终端结构能使雪崩击穿电压提高到理想值的 95 %以上 .实验结果表明 ,深阱结终端结构器件 DCT2 6 0的BVCBO为理想值的 94 % ,比传统终端结构器件高 14 % ;与传统结构相比 ,在不减小散热面积的情况下 ,该结构还减小集电结面积和漏电流 ,器件的截止频率提高 33% ,功率增益提高 1d B     

The planar junction etch for high voltage and low surface fields in planar devices

A modification of the moat etch type of surface contouring is described which can increase the avalanche breakdown voltage of planar p-n junctions and greatly reduce peak surface electric fields. A properly located moat etch or bevel is used to achieve what is effectively a positive bevel intersection angle between the junction and the surface. Qualitative arguments based on charge balance, exact computer solutions, and experimental results show that higher breakdown voltage and much lower surface fields can be achieved as some, but not all, of the deleterious effects of the junction curvature are eliminated. Optimum design and sensitivity to process variations are also considered.     

MOS型硅功率器件的耐压与终端处理

本文介绍了MOS型硅功率器件常见的平面结击穿电压的基本理论和提高击穿电压的基本方法以及终端处理技术发展中所面临的课题。     

A substrate etch geometry for near ideal breakdown voltage in p-n junction devices

A new junction-termination geometry is proposed which can be achieved by a simple etch. This etch effectively lowers peak surface fields in both plane and planar p-n junction devices without increasing peak bulk electric fields. This insures an ideal, or near-ideal, avalanche breakdown voltage. The further advantages of the proposed technique lie in a relative insensitivity to etch depth, a minimal loss in device area, and compatibility with planar technology. Theoretical and experimental results are given to illustrate the substrate-etch technique.     

用二维数值计算得到三维p-n结击穿特性的方法

本文基于大多数p-n结的结面形状在平行于表面的横剖面上常表现为一由光刻图形的圆角决定的圆弧这一特点,提出了一种把三维计算简化为二维计算的数值计算方法.用此方法对平面p-n结的击穿特性进行了分析,得到了平面p-n结击穿电压随图形圆角的曲率而变的曲线.本方法还可推广应用于对圆角区其他特性的研究.     

1200-V 5.2-mΩ·cm2 4H-SiC BJTs With a High Common-Emitter Current Gain

This letter presents fabrication of a power 4H-SiC bipolar junction transistor (BJT) with a high open-base breakdown voltage BV_CEO ap 1200 V, a low specific on-resistance R _{SP_ON} ap 5.2 mOmegamiddotcm², and a high common-emitter current gain beta ap 60. The high gain of the BJT is attributed to reduced surface recombination that has been obtained using passivation by thermal silicon dioxide grown in nitrous oxide (N₂O) ambient. Reference BJTs with passivation by conventional dry thermal oxidation show a clearly lower current gain and a more pronounced emitter-size effect. BJTs with junction termination by a guard-ring-assisted junction-termination extension (JTE) show about 400 V higher breakdown voltage compared with BJTs with a conventional JTE.     

Practical aspects of the depletion etch method in high-voltage devices

In an earlier paper a new junction-termination geometry was described which was able to give near-ideal avalanche breakdown voltage in both plane and planar p-n junctions. The difficulty of the DEM (depletion etch method) was to achieve a precise etch depth which failure to achieve led to reduced effectiveness. In this paper the range of avalanche breakdown voltage is related to the accuracy of the depletion etch in a quanitative and rather general way so thatDelta V, the decrease in breakdown voltage below the ideal is related toDelta Y, the deviation in etch depth from the ideal, for any p-n junction.     

Edge current induced failure of semiconductor PN junction during operation in the breakdown region of electrical characteristic

Typical blocking I-V characteristics are shown and analyzed for PN junctions exhibiting a breakdown region above 1000 V from commercial diodes and power MOSFETs. The leakage reverse current of PN junctions from commercial silicon devices available at this time has a flowing component at the semiconductor-passivant material interface around the junction edge.Part of the plotted experimental current-voltage characteristic fits to linear variation and deviation from this variation at higher applied voltage is attributed to non-controlled current flow in the interfacial layer, between the silicon and passivating material from the junction periphery. The thin interfacial layer including atomic layers both from the semiconductor and passivating dielectric material with fixed charges has imperfections resulted from the junction passivation process. For controlled-avalanche PN junctions no deviation from linear voltage dependence of the reverse current is possible until breakdown region practically at right knee appears. For other PN junctions deviation of the reverse current from linear variation results in a breakdown region with round knee and still with visible voltage dependence at current increase. Such soft breakdown region caused by the phenomena in the interfacial layer is exhibited at lower applied reverse voltage than the expected one for breakdown caused by charge carrier avalanche multiplication at the junction. Operation even for short in the soft breakdown region can lead to PN junction failure and for this reason, a maximum working permissible reverse voltage is specified in device data sheet with a value under the breakdown region. Junction failure consists in significantly lower reverse voltage than the initial one or even electrical short-circuit caused by a spot of material degradation in the interfacial layer from the junction periphery. Operation of the controlled-avalanche diode in the breakdown region is possible only for single pulse of short duration and at junction temperature not higher than 175 °C. Above 150-175 °C even for controlled-avalanche diodes deviation from linear variation of the reverse current has been observed and soft breakdown region can appear before the expected avalanche breakdown. Device failure after operation in the breakdown region, caused by spot of material degradation at the junction periphery has occurred in such conditions. For high voltage commercial power MOSFETs operation in the avalanche breakdown region is limited to 150 °C.     

Some new aspects of thermal instability of the current distribution in power transistors

An important characteristic of second breakdown in p-n junctions is the current constriction to a small region. This may be caused by a thermal feedback mechanism, as discussed by Scarlett and Shockley, and by Bergmann and Gerstner. A brief review of this theory is given, illustrated by experimental results of a simple model arrangement consisting of three thermally coupled transistors. The essential parameters influencing the thermal stability of the current distribution are device geometry, power density, and temperature dependence of current. It is widely known that second breakdown occurs at high voltages at a much lower power level than at low voltages. To allow a more detailed discussion of this effect in view of thermal stability, we determined experimentally the temperature coefficient of transistor current for various Si planar transistors as a function of current, voltage, and junction temperature. The experimental procedure is described and the results are discussed. The experimental values of the temperature coefficient range from 0.08 to 0.01 1/°C. The values for high currents are much lower than predicted by the theory of Ebers and Moll. It thus can easily be understood why, in the case of high current, and low voltage, the thermal stability of the current distribution is much better than in the case of low current and high voltage.     

高压IGBT线性变窄场限环终端设计

为使3300 V及以上电压等级绝缘栅双极型晶体管(IGBT)的工作结温达到150℃以上,设计了一种具有高结终端效率、结构简单且工艺可实现的线性变窄场限环(LNFLR)终端结构。采用TCAD软件对这种终端结构的击穿电压、电场分布和击穿电流等进行了仿真,调整环宽、环间距及线性变窄的公差值等结构参数以获得最优的电场分布,重点对比了高环掺杂浓度和低环掺杂浓度两种情况下LNFLR终端的阻断特性。仿真结果表明,低环掺杂浓度的LNFLR终端具有更高的击穿电压。进一步通过折中击穿电压和终端宽度,采用LNFLR终端的3300 V IGBT器件可以实现4500 V以上的终端耐压,而终端宽度只有700μm,相对于标准的场限环场板(FLRFP)终端缩小了50%。     

Optimization of interconnection-induced breakdown voltage injunction isolated IC's using biased polysilicon field plates

The detrimental effect of high-voltage interconnection on the blocking capability of a junction isolated (JI) structure in a typical high-voltage integrated circuit (HVIC) process is investigated. A significant increase in breakdown voltage is realized using a novel biased polysilicon field plate technique. Fabricated devices show a large improvement in breakdown over the equivalent junction termination extension (JTE) case for the same wire width. Increases of 30% were observed for a three field plate scheme and 50% for four field plates. Breakdown voltages of up to 700 V were realized for a 50-μm wide wire     

On multiplication and avalanche breakdown in exponentially retrograded silicon P-N junctions

An analysis of avalanche breakdown in exponentially retrograded p-n junctions results in simple criteria for avoiding breakdown in such structures. Breakdown voltages are shown to be extremely dependent on the surface concentration and grading constant of the retrograded region. The effect of background resistivity on breakdown is also analyzed. Unusual saturation effects in the multiplication voltage curves of retrograded p-n diodes are predicted theoretically. Experimental results point towards a confirmation of this theory.     

对拥有结终端保护的高压4H-SiC PIN二极管的研究

在对4H-SiC高压PIN二极管进行了理论分析的基础上,利用仿真软件ISE10.0对具有结终端保护的高压4H-SiC PIN二极管耐压特性进行了模拟仿真计算,并取得了很多有价值的计算结果。利用平面制造工艺,结合仿真提取的参数,试制了高压4H-SiC PIN二极管。实验测试结果表明,仿真计算的结果与实际样品测试的数据一致性较好,实测此器件击穿电压值已达到1 650V。     

Plasma-induced micro breakdown in small-area MOSFETs

We investigated the impact of latent plasma-induced damage (PID) on the reliability of nMOSFETs with small gate area and gate-oxide thickness of 3.2 nm. To this purpose, we stressed 1500 devices with different antenna areas by using a staircase-like stress voltage and by monitoring the gate leakage at the gate voltage V/sub G/=+2 V. The stress was always stopped because of an abrupt jump in the gate current. The statistics obtained for the breakdown current are characterized by two different oxide-breakdown modes. The first is the well-known hard breakdown (HB), while the second one, which we called micro breakdown (MB), can be modeled as a double trap-assisted tunneling (D-TAT) mechanism and is characterized by a very small leakage current (around 100 pA at the gate voltage V/sub G/=2 V). In devices with large antenna, i.e., more prone to be damaged by plasma processing, the number of microbroken oxides is larger and breakdown occurs at lower voltages than in reference devices (non plasma damaged). Conversely, the hard breakdown statistics shows only a weak dependence on the gate antenna ratio of plasma damaged devices. This has been explained by considering the intrinsic nature of latent plasma-induced oxide defects, linked to the different generation mechanisms involved in micro breakdown and hard breakdown phenomena.     

SiC devices: physics and numerical simulation

The important material parameters for 6H silicon carbide (6H-SiC) are extracted from the literature and implemented into the 2-D device simulation programs PISCES and BREAKDOWN and into the 1-D program OSSI Simulations of 6H-SiC p-n junctions show the possibility to operate corresponding devices at temperatures up to 1000 K thanks to their low reverse current densities. Comparison of a 6H-SiC 1200 V p-n^--n⁺ diode with a corresponding silicon (Si) diode shows the higher switching performance of the 6H-SiC diode, while the forward power loss is somewhat higher than in Si due to the higher built-in voltage of the 6H-SiC p-n junction. This disadvantage can be avoided by a 6H-SiC Schottky diode. The on-resistances of Si, 3C-SiC, and 6H-SiC vertical power MOSFET's are compared by analytical calculations. At room temperature, such SiC MOSFET's can operate up to blocking capabilities of 5000 V with an on-resistance below 0.1 Ωcm², while Si MOSFET's are limited to below 500 V. This is checked by calculating the characteristics of a 6H-SiC 1200 V MOSFET with PISCES. In the voltage region below 200 V, Si is superior due to its higher mobility and lower threshold voltage. Electric fields in the order of 4×10⁶ V/cm occur in the gate oxide of the mentioned 6H-SiC MOSFET as well as in a field plate oxide used to passivate its planar junction. To investigate the high frequency performance of SiC devices, a heterobipolartransistor with a 6H-SiC emitter is considered. Base and collector are assumed to be out of 3C-SiC. Frequencies up to 10 GHz with a very high output power are obtained on the basis of analytical considerations