圆柱突变结击穿电压及电场沿结边的分布

基于横向侧扩散与纵向体扩散结深构成椭圆形冶金结外形这一与工艺实际相符合的假设 ,通过圆柱对称解的归一化 ,提出了平面结击穿电场沿结边分布的解析解。理论结果阐述了不同结深及结边形状对边缘区击穿电压的影响规律 ,说明了表面击穿电压总是小于体内击穿电压的原因。     

Maximum surface and bulk electric fields at breakdown for planar and beveled devices

Techniques previously presented for predicting breakdown voltage on planar devices with and without a field ring and in negative beveled devices are greatly extended so that the peak bulk and surface electric fields at breakdown can now be predicted. In addition, new techniques are described which for the first time allow the peak bulk and surface electric fields to be predicted for all positive and double positive beveled devices. Using this paper it becomes possible to predict peak bulk and surface electric fields as well as breakdown voltage for all planar and beveled devices. This is accomplished by the use or normalization procedures which allow dependencies on the substrate doping, junction depth, surface concentration, junction curvature, and bevel angle to be reduced to a single dependence. It is shown that the positive bevel is most effective in reducing surface electric fields with the negative bevel, double positive bevel, and the field ring for planar devices in decreasing order of effectiveness.     

The planar junction etch for high voltage and low surface fields in planar devices

A modification of the moat etch type of surface contouring is described which can increase the avalanche breakdown voltage of planar p-n junctions and greatly reduce peak surface electric fields. A properly located moat etch or bevel is used to achieve what is effectively a positive bevel intersection angle between the junction and the surface. Qualitative arguments based on charge balance, exact computer solutions, and experimental results show that higher breakdown voltage and much lower surface fields can be achieved as some, but not all, of the deleterious effects of the junction curvature are eliminated. Optimum design and sensitivity to process variations are also considered.     

Calculation of avalanche breakdown voltage and depletion layer thickness in a P−N junction with a double error function doping profile

We have calculated the avalanche breakdown voltage and the extent of the depletion region for a pn-junction with a double error function doping profile which could be useful in the design of high voltage thyristors. The results are presented as a set of curves corresponding to various surface concentrations and depths of the two diffusions. The parameter range covered is as follows: surface concentrations: first diffusion 10¹⁸–10²⁰ cm^?3, and second diffusion 2 × 10¹⁵–10¹⁷ cm^?3; diffusion depths: first diffusion 60–100 μm, and second diffusion 40–160 μm; background doping density: 10¹³–10¹⁴ cm^?3.     

Improvement of breakdown voltage in SOI n-MOSFETs using thegate-recessed (GR) structure

A gate-recessed structure is introduced to SOI MOSFETs in order to increase the source-to-drain breakdown voltage. A significant increase in the breakdown voltage can be seen compared with that of a planar single source/drain SOI MOSFET without inducing the appreciable reduction of the current drivability. We have analyzed the origin of the breakdown voltage improvement by the substrate current measurements and 2-D device simulations, and shown that the breakdown voltage improvement is caused by the reductions in the impact ionization rate and the parasitic bipolar current gain     

Self-aligned shallow junction MJFET (metal junction FET) for higherturn-on and breakdown voltages

Simple self-aligned p⁺⁺-gate formation technology for a junction field-effect transistor (JFET) using elemental shallow Zn diffusion from patterned Au/Zn gate metal is reported. This diffusion technology makes it possible to control a very shallow p⁺⁺-layer less than 50 nm. The metal junction FET (MJFET) shows about 0.3 V higher gate turn-on voltage in forward bias and much larger reverse breakdown voltage than the conventional Al-gate MESFET with similar transconductances, typically 200 mS/mm for 1.5-μm gate length quasi-enhancement, and 90 mS/mm for 4-μm gate length deep depletion devices     

A study on IGBT junction temperature (Tj) online estimation using gate-emitter voltage (Vge) at turn-off

A novel method is presented for online estimation of the junction temperature (Tj) of semiconductor chips in IGBT modules, based on evaluating the gate-emitter voltage (Vge) during the IGBT switch off process. It is shown that the Miller plateau width (in the Vge waveform) depend linearly on the junction temperature of the IGBT chips. Hence, a method can be proposed for estimating the junction temperature even during converter operation – without the need of additional thermal sensors or complex Rth network models. A measurement circuit was implemented at gate level to measure the involved time duration and its functionality was demonstrated for different types of IGBT modules. A model has been proposed to extract Tj from Vge measurements. Finally, an IGBT module with semiconductor chips at two different temperatures has been measured using Vge method and this method was found to provide the average junction temperature of all the semiconductor chips.     

Characterizing electric fields in (111)B InGaAs quantum wells using electric field modulated photoluminescence and reflectance techniques

We have performed a series of electroreflectance, photoluminescence, and electric-field-modulated photoluminescence experiments to characterize the strain-induced electric fields in (111)B InGaAs/AlGaAs quantum well p-i-n diode structures. A 180° phase change in the lineshapes of electroreflectance spectra of these samples determines when the quantum well is biased to flatband. Using this bias and a depletion model for the diode, the polarization field in the quantum well can be determined. Contrary to expectations, this polarization field increases significantly with increasing temperature. In addition, at fixed temperature, the quantum well transition energies red-shift with increasing excitation intensity when excited by photons of energy higher than the lowest quantum well transition but lower than the AlGaAs diode's bandgap. When excited with photons of energy greater than the AlGaAs bandgap, the transition energy first red shifts then blue shifts with increasing excitation intensity.     

Properties of GaAs nanowhiskers grown on a GaAs(111)B surface using a combined technique

Arrays of GaAs whiskers on GaAs(111)B substrates were grown using a technique combining vacuum evaporation and molecular-beam epitaxy. The surface structural properties of the samples obtained were studied by scanning electron microscopy. It was found that the areal density of the whiskers amounted to (1–2)×10⁹ cm^?2. The typical dimensions of the whiskers were 30–150 nm (diameter) and 300–800 nm (length). It was shown that the whisker size can be controlled by changing the growth conditions and varying the thickness of the evaporated Au film.     

Submillimeter spectroscopy using a Froome harmonic generator (metal-plasma junction)

The rectifying properties of the cathode spot of a microscopic arc discharge (as first investigated by K. D. Froome) are used to generate high harmonics of a 37.5-kMc/s source. That these high harmonics can be used to do high resolution spectroscopy in the submillimeter range is demonstrated by a study of the pressure broadening of the J13 → 14 rotational transition of N2O at 0.85-mm wavelength.     

Improvement of GaAs MESFET performance using surface p-layer doping(SPD) technique

The development of a surface p-layer doping (SPD) technique to improve GaAs MESFET performance is presented. Very shallow p-type doping into the gate-drain and gate-source regions is used to improve the output conductance of the device. It is found that the threshold voltage is independent of the SPD dose. The transconductance degrades significantly as the p doping (Be, 10 keV) increases above 3×10 ¹²/cm². However, the output conductance and subthreshold current are improved with higher SPD dose. The gate-source reverse breakdown voltage is improved by about 90%, and the parasitic resistance increases by about 30% with an SPD of 5×10¹²/cm²     

Evaluation of the dielectric breakdown of reoxidized nitrided oxide (ONO) in flash memory devices using constant current-stressing technique

The dielectric breakdown time of reoxidized nitrided oxide (ONO) in flash memory devices has been evaluated using the constant current-stressing technique. The dielectric performance of ONO was severely impaired by the stressing effects of a current. A positive constant current of 5 μA stressing on a 280 Åthick ONO layer (via two polysilicon electrodes), covering an area of 50,000 μm² took only a mere 20 s to breakdown. The situation worsened when a negative current of 5 μA was stressed on it—the ONO layer almost instantaneously broke down. The electrical tolerance of the ONO interpoly dielectric is still mediocre upon stressing with a smaller current. With a 1 μA positive constant current-stressing test, the average breakdown time of the dielectric layer was about 50 s, but it broke down instantaneously again upon a 1 μA negative constant current-stressing test. The probable causes for the rapid degradation of ONO dielectric properties are the rough surface of bottom polysilicon layer, the trapped fluoride ions in the device, and the changes in the occupancy of the interfacial states. There can be the occurrence of current surging through the devices during their fabrication e.g. stack-etching. Hence, with the future scaling of memory devices, situations of higher current density surging through the devices will be realized. It will be beneficial to investigate how the ONO layer conducts upon current-stressing. The constant current-stressing technique is a simple and most straightforward method to address and simulate the current-stressing conditions.     

Design of voltage-mode PID controller using a single voltage differencing current conveyor (VDCC)

Analog Integrated Circuits and Signal Processing - This paper presents a voltage differencing current conveyor (VDCC) based voltage-mode (VM) proportional integral derivative (PID) controller for...     

Control and testing of a dynamic voltage restorer (DVR) at medium voltage level

The dynamic voltage restorer (DVR) has become popular as a cost effective solution for the protection of sensitive loads from voltage sags. Implementations of the DVR have been proposed at both a low voltage (LV) level, as well as a medium voltage (MV) level; and give an opportunity to protect high power sensitive loads from voltage sags. This paper reports practical test results obtained on a medium voltage (10 kV) level using a DVR at a distribution test facility in Kyndby, Denmark. The DVR was designed to protect a 400-kVA load from a 0.5-p.u. maximum voltage sag. The reported DVR verifies the use of a combined feed-forward and feed-back technique of the controller and it obtains both good transient and steady-state responses. The effect of the DVR on the system is experimentally investigated under both faulted and nonfaulted system states, for a variety of linear and nonlinear loads. Variable duration voltage sags were created using a controllable LV breaker fed by a 630 kVA distribution transformer placed upstream of the sensitive load. The fault currents in excess of 12 kA were designed and created to obtain the required voltage sags. It is concluded the DVR works well in all operating conditions.     

The transient response of a dipole antenna using a summationapproach in technique (SAT)

A novel summation approach in technique (SAT) improving on the usual computation by multiple reflections to find the transient response was presented in a previous paper. This technique leads to accurate answers consisting of relatively few terms. The transient response at large values of time can be found without need to know explicitly and laboriously add all multiple reflections for the whole preceding range of time involved in producing the response. In this paper, the transient response for a realistically modeled pulse generator exciting a dipole antenna modeled as a distributed parameter load is investigated using a generalization of the SAT. A detailed comparison between this technique and the standard superposition of multiple reflections is presented     

Calculation of tunneling currents in (Hg,Cd)Te photodiodes using a two-sided junction potential

It has been shown previously that tunneling current can become the dominant dark current and hence the performance-limiting factor in diodes formed in narrow bandgap semiconductors, such as Hg1_xCdxTe. In this paper, we calculate the tunneling current using a Kane approximation for the nonparabolic conduction band and a more realistic junction potential than has been used previously. The potential used here is characteristic of a linearly graded n-type region intersecting a uniformly doped p-type region and is a better approximation to the actual potential in a diode formed by ion implantation into a p-type substrate. We show that significant errors sometimes arise when the abrupt junction model is used to calculate tunneling current in these structures. The effect of changes in base carrier concentration and n-side donor gradient is shown forxbetween 0.196 and 0.400, which corresponds to a photodiode spectral cutoff in the important 3- to 14-µm region.     

Low voltage stress induced leakage current and time to breakdown in ultra-thin (1.2–2.3 nm) oxides

Ultra-thin gate-oxide reliability is an essential factor in CMOS technologies. The low voltage gate current in ultra-thin oxide of metal–oxide–semiconductor devices is very sensitive to electrical stresses. It can be used as a reliability monitor when the oxide thickness becomes too small for traditional electrical measurements. In this paper, the low voltage stress induced leakage current (LVSILC) for various oxide thicknesses ranging from 1.2 to 2.3 nm is investigated during constant voltage stress (CVS). From the LVSILC measurements, we shown that time to breakdown can be deduced as a function of the stress voltage. We also study the effect of elevated stress temperature on the time to breakdown. We show that temperature dependence of the time to breakdown is non-Arrhenius and decreases in a drastic way with a slope of 0.036 decade/°C.     

Low drive voltage (1.5 Vp.p.) and high power DFB-LD/modulatorintegrated light sources using bandgap energy controlled selective MOVPE

The authors have reduced modulator drive voltage in DFB-LD/modulator integrated light sources (DFB/MODs) taking fabrication tolerance into account. By enhancing the quantum confined Stark effect through well width increase and optimising the doping profile, DFB/MODS with >13 dB extinction ratio at 1.5 V and >4 mW (+6 dBm) output power at 100 mA were achieved while maintaining a reasonably large fabrication tolerance     

Direct measurement of surface wave velocity and time delay—Temperature variation using a pulse technique

An experimental pulse technique has been developed permitting rapid measurement of absolute surface wave velocity on single crystals to an accuracy of 1 percent or better. A further modification of the technique allows measurement of parts per million changes in surface wave time delay caused by changes in substrate temperature. The technique directly measures the vertical component of particle velocity at the receiver as a function of time and enables one to distinguish clearly between the various types of surface modes, e.g., Rayleigh wave, pseudosurface wave, etc. The method is applicable to any material.