CMOS存储器IDD频谱图形测试

通过对CMOS存储器IDD频谱图形测试过程的介绍,测试及试验数据证实CMOS存储器IDD频谱图形测试是可行的。     

一种CMOS微电子测试图形的设计

本文介绍一种CMOS集成电路微电子测试图形——E2-PED,它是针对CMOS EEPR-OM电路的研制而设计的,也可以用于一般的CMOS电路工艺:文章描述了E2-PED所含有的各种微电子测试结构以及设计布图,给出了这些结构的构成及其作用。     

模拟集成电路的测试与故障检测技术

本文综述了模拟集成电路的测试及故障检测等有关问题，首先介绍面向性能的测试方法，然后讨论故障模型和面向故障的测试方法，在介绍了模拟集成电路的可测性设计技术之后，讨论了利用电源监测进行故障检测的方法。     

MMIC微波S参数测试

阐述了单片微波集成电路测试系统的工作原理,测试方法和自动测试程序。     

一种廉价的计算器集成电路测试系统──微机测试系统

本文扼要地介绍了计算器集成电路的自身测试方法，并根据这种测试方法给出了微机测试计算器集成电路的系统结构。然后着重阐述了微机与计算器集成电路的硬件接口，它包括键盘接口、LCD段码接口、背极信号接口，以及计算器集成电路静态电参数的测试方法与接口线路。     

CMOS数字集成电路输入电流的测试

CMOS数字电路的输入电流是反映该器件工艺水平的主要参数之一，通过叙述并分析了影响其测试准确性的原因，应用ATS60e数字集成电路测试系统，可满足对其输入电流的测试要求。     

高温微电子学-Ⅱ:硅集成电路的高温特性研究

本文详细分析了硅集成电路的高温特性和高温失效模式,指出了CMOS集成电路的高温失效的主要模式是高温闭锁效应。解决这个问题的有效途径之一是研制介质隔离的CMOS IC,例如SOI CMOS集成电路。     

STS2106A数字集成电路测试系统的开发及应用

本文以一款CMOS专用数字集成电路为例，介绍STS2106A数字集成电路测试系统开发过程以及使用中的重点注意事项。     

应用虚拟仪器(VI)技术开发集成电电路闩锁测试系统

闩锁(latch-up)效应严重影响了CMOS集成电路的可靠性,如何对其进行快速有效地测试是很有必要的,本文主要介绍了代表了当今世界测试仪器技术发展方向的虚拟仪器技术(VI)及其在开发集成电路闩锁测试系统过程中的应用.     

浅谈CMOS集成电路的应用

CMOS集成电路因其高性能、低功耗的特点已经在集成电路设计中得到了极为广泛的应用。本文浅析了CMOS集成电路的性能特点,通过对其特点的分析,介绍了目前CMOS集成电路的应用方面,并指出了CMOS集成电路应用的注意事项,为集成电路的发展提供理论依据。     

基于FPGA的频率测试系统

传统ATE比较昂贵,功率大耗电多,造成IC的测试成本偏高,针对ATE的不足之处,设计制作FPGA模块的频率测试系统,包括FPGA测试系统的组成模块,测试原理和测试方法,以及与Handler的通信设计。该测试系统占用空间小,耗电少,测试成本低,达到了节能降耗,降低测试成本的目的。     

Performance of iterative decoding for superposition modulation-based cooperative transmission

In this paper, we propose a new superposition modulation-based cooperative scheme and investigate receivers with iterative detection and decoding (IDD), where we focus on an interference cancellation (IC) detector. For quasi-static fading environment, we analyze the bit-error-probability (BEP) of the proposed scheme and analytically show the optimal power allocation in the superposition modulation. It is demonstrated that the proposed scheme performs about 2-3.5 dB better than the system previously proposed in the literature and simulation results are shown to be very close to the analytical results. In addition, the receiver with IC detectors achieves the MAP detection performance in the scheme.     

基于安全火花试验装置的电感分断电弧电阻建模研究

研究电感分断放电电弧电阻模型是建立电感电路非爆炸本安性能评价的基础.运用IEC安全火花试验装置对电感分断电弧放电特性进行试验研究,深入分析电弧电阻随放电时间的变化规律,并采用非线性回归的方法得出分断电弧放电时间与电感和初始电流之间的函数关系式.考虑安全火花试验装置钨丝和镉盘电极结构特点,建立了一种极间电弧放电区域的物理模型,并推断出二维泊松方程的边界条件.基于此,利用分离变量法求解泊松方程,推导出电弧电阻的数学表达式,得出了电感分断电弧放电电压和电流的关系表达式.仿真分析及实验结果证明了理论分析及所提出电弧电阻数学模型的准确性和可行性.     

高速数字微波共面带线电磁互耦全波分析及模拟器

报道了采用电磁场全波分析方法模拟高速数字微波共面带线传输线电磁互耦特性。共面带线传输线电磁互耦模拟器具有很好的交互式界面，能用于高速集成电路共面带经传输线的电磁场全波分析。     

用GaAs MMIC实现2.1GHz的预失真线性化单片

介绍了一种预失真线性化单片电路,该电路单电源工作,采用预失真技术结合有源反馈的方法,完成了单片预失真线性化电路的研制.预失真线性化单片电路采用75 m m Ga As MMIC工艺研制,芯片面积约为4 mm2 .结果表明,2 .1GHz时此预失真单片电路可改善放大器的三阶互调分量9d B     

Assessment of digital integrated circuit electromagnetic emissionbased on radiated power evaluation

This paper deals with the assessment of digital integrated circuit (IC) electromagnetic emission (EME), and concentrates on the specific aspect of EME of long external wiring, driven by IC input-output pins. In particular, the contribution of single IC pins is investigated by analyzing the structure composed of an IC output driver connected via a microstrip line to a receiver. A transmission-line model is used, and an approach based on the concept of radiated power is applied to the characterization of single-pin IC EME in terms of external-wiring radiation effects. By the analysis of typical driver-wiring configurations, it is shown that the spectrum of the driver output current is the quantity of interest, and that the use of wiring with smaller characteristic impedance leads to larger radiated power. The use of a specific test setup (IEC 61967-4-150-Ω direct coupling method) for the experimental assessment of single pin IC emissions is also considered. Frequency-dependent setup effects are experimentally ascertained via a scattering parameter characterization, and definition of suitable circuit functions. An estimate of the degree of correlation between voltage measurements foreseen by the test procedure and the total power radiated by the loading network of an IC driver is derived     

IC Immunity Modeling Process Validation Using On-Chip Measurements

Developing integrated circuit (IC) immunity models and simulation flow has become one of the major concerns of ICs suppliers to predict whether a chip will pass susceptibility tests before fabrication and avoid redesign cost. This paper presents an IC immunity modeling process including the standard immunity test applied to a dedicated test chip. An on-chip voltage sensor is used to characterize the radio frequency interference propagation inside the chip and thus validate the immunity modeling process.     

An alternative method for transistor low frequency noise estimation by measuring phase noise of test oscillator

In this paper we suggest an alternative method for the analysis of low frequency noise of transistors based on measurements of phase noise of a test oscillator. This method is demonstrated by experimental results obtained with a simple test oscillator with HEMT, and central frequency of 13.769 GHz. The main contribution to phase noise of the test oscillator comes from up conversion of transistor LF noise. This idea and the method can be used for the selection of transistors for high frequency application or for design of test circuit in RF IC manufacture.     

S-parameter-measurement-based high-speed signal transientcharacterization of VLSI interconnects on SiO2-Si substrate

A new S-parameter-based signal transient characterization method for very large scale integrated (VLSI) interconnects is presented. The technique can provide very accurate signal integrity verification of an integrated circuit (IC) interconnect line since its S-parameters are composed of all the frequency-variant transmission line characteristics over a broad frequency band. In order to demonstrate the technique, test patterns are designed and fabricated by using a 0.35 μm complementary metal-oxide-semiconductor (CMOS) process. The time-domain signal transient characteristics for the test patterns are then examined by using the S-parameters over a 50 MHz to 20 GHz frequency range. The signal delay and the waveform distortion presented in the interconnect lines based on the proposed method are compared with the existing interconnect models. Using the experimental characterizations of the test patterns, it is shown that the silicon substrate effect and frequency-variant transmission line characteristics of IC interconnects can be very crucial