High-performance edge-triggered flip-flops using weak-branch differential latch

A new technique to build edge-triggered flip-flops based on the use of 'weak' transistors is presented. This technique can be applied to most CMOS differential latches with only some further design considerations. Despite the hardware costs, the resulting flip-flops are very suitable for high-performance and low-noise applications.     

新型半静态低功耗D触发器设计

本文从简化触发器内部锁存器结构以降低功耗的要求出发，提出了一种新型的半静态D触发器设计。PSPICE模拟表明，新设计逻辑功能正确。与以往一些设计相比，新设计在功耗和速度上获得显著改进。     

A new family of semidynamic and dynamic flip-flops with embeddedlogic for high-performance processors

In an attempt to reduce the pipeline overhead, a new family of edge-triggered flip-flops has been developed. The flip-flops belong to a class of semidynamic and dynamic circuits that can interface to both static and dynamic circuits. The main features of the basic design are short latency, small clock load, small area, and a single-phase clock scheme. Furthermore, the flip-flop family has the capability of easily incorporating logic functions with a small delay penalty. This feature greatly reduces the pipeline overhead, since each flip-flop can be viewed as a special logic gate that serves as a synchronization element as well     

Two D flip-flops based on bistable-gated-bipolar devices

Two novel static D flip-flops based on a novel bistable-gated bipolar device are proposed. Their logic functionality and improved speed in comparison to the conventional static D flip-flop are verified with SPICE simulation.     

Aging comparative analysis of high-performance FinFET and CMOS flip-flops

This paper presents a comparative performance analysis to investigate the impact of aging mechanisms on various flip-flops in CMOS and FinFET technologies. We consider Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) effects on the robustness of high performance flip-flops. To apply BTI and HCI aging mechanisms, we utilize long-term model to estimate ∆ V_th and employ the updated V_th in transistor model file. The simulation results on performance analysis indicate the high ranking of various flip-flops considering speed and power consumption in each CMOS and FinFET technologies, moreover, approve the superiority of static FinFET flip-flops over CMOS flip-flops. In addition, a comparative analysis considering temperature and V_DD variations over different FinFET flip-flop structures demonstrates the average percentages of T_DQmin and PDP degradation against aging mechanisms are significantly less than similar CMOS flip-flops.     

Design analysis and circuit enhancements for high-speed bipolar flip-flops

The design of high-speed current mode logic latches is discussed, using analytical expressions for delay. An open circuit time constant method is utilized throughout this paper, though similar results were obtained from a charge control analysis. Emphasis is placed on the variables that are under the control of the circuit designer, as opposed to the device designer. Circuit delay is calculated with respect to device area, current density, amplitude, and a keep-alive current. In particular, the keep-alive current gives the circuit designer control over the average transconductance of switching transistors, independent of their bias currents. The cost of the keep-alive current is the loss of output amplitude. The effects of transmission lines and peaking inductors are discussed in a qualitative manner. Latch designs were tested with static divide-by-two frequency dividers. Results of several dividers (both SiGe and InP) are shown and compared with the theory.     

Comments on “New dynamic flip-flops for high-speeddual-modulus prescaler”

For the original paper see ibid., vol. 33, no. 10, p. 1568-1571 (1998). In the aforementioned paper a fast true single-phase clocking (TSPC) ratioed D-flip-flop is proposed by C. Yang et al. It is claimed by the commenters that the proposed flip-flop violates the edge-triggering characteristic. However, it is shown that high clock frequency and the propagation delay of the transistor enable the flip-flop to operate normally in the dual-modulus prescaler     

Generation of cyclic sequences using D and T flip-flops

A general polynomial is derived for cyclic sequences generrated by circuits employing only D and T flip-flops. For specific combinations of the flip-flops, a simple method of expanding the polynomial using a mod-2 Pascal's triangle is given.     

Metastability behavior of CMOS ASIC flip-flops in theory and test

Basic flip-flop structures are compared with the main emphasis on CMOS ASIC implementations. Flip-flop properties are analyzed by means of simplified models, some structural approaches for optimized metastable behavior are discussed. A special integrated test circuit which facilitates accurate and reproducible measurements is presented. The circuit has been used for carrying out metastability measurements in a wide temperature and voltage range to predict circuit parameters for worst-case designs. Results from measurements and circuit simulation indicate that different criteria for optimizing flip-flop performance should be used for synchronizers and for those applications where the observation of timing constraints imposed on flip-flop input signals can be guaranteed. These results can help in determining the reliability of existing synchronizer and arbiter designs. By means of special synchronizer cells the reliability of asynchronous interfaces can be improved significantly, enabling the system design to gain speed and flexibility in communication between independently clocked submodules     

Comparative analysis of master-slave latches and flip-flops forhigh-performance and low-power systems

In this paper, we propose a set of rules for consistent estimation of the real performance and power features of the flip-flop and master-slave latch structures. A new simulation and optimization approach is presented, targeting both high-performance and power budget issues. The analysis approach reveals the sources of performance and power-consumption bottlenecks in different design styles. Certain misleading parameters have been properly modified and weighted to reflect the real properties of the compared structures. Furthermore, the results of the comparison of representative master-slave latches and flip-flops illustrate the advantages of our approach and the suitability of different design styles for high-performance and low-power applications     

一种高速低功耗BiCMOS脉冲式触发器的通用结构

BiCMOS电路兼具CMOS电路高集成度,低功耗的优点和双极型电路高速大驱动能力的优势,已成为目前国际学术界研究的热点之一。本文提出了一种基于BiCMOS工艺的新型脉冲式触发器的通用结构和设计方法,并设计了两种结构简单的BiCMOS脉冲式D型触发器。应用TSMC 180nm工艺,采用HSPICE模拟表明:所设计的BiCMOS脉冲式D型触发器不仅具有正确的逻辑功能,而且具有高速低功耗大驱动能力的优点,与已有文献提出的BiCMOS D型触发器相比,功耗和PDP均有大幅度降低。     

All-optical tree-based greedy router using optical logic gates and optical flip-flops

Due to ever-increasing throughput demands, the lookup in conventional IP routers based on longest prefix matching is becoming a bottleneck. Additionally, the scalability of current routing protocols is limited by the size of the routing tables. Geometric greedy routing is an alternative to IP routing which replaces longest prefix matching with a simple calculation employing only local information for packet forwarding. For the first time, in this paper we propose a novel and truly all-optical geometric greedy router based on optical logic gates and optical flip-flops. The circuit of the router is constructed through the interconnection of SOAs and directional couplers. The successful functionality of the proposed router is verified through simulation. The circuit enables high data rate throughput.     

一种新型微分平坦无极灯镇流器的研究

为了改善无极灯的效率和性能,设计一种基于微分平坦理论控制的无极灯镇流器。通过引入微分平坦理论,使用李雅普诺夫稳定性原理设计出控制策略,既可以保证系统的稳定性与可靠性,还可以提高系统的效率。该文分析了Boost升压变换器的微分平坦性,构造了李雅普诺夫能量函数及确定其控制规律,分析了控制策略的可行性与正确性。最后,基于DSP2812制作了一台100 W的实验样机,实验结果表明,基于微分平坦控制理论设计的控制系统具有稳定性好、调节能力快以及效率高等优点。     

The behaviour of flip-flops used as synchronizers and prediction of their failure rate

Deals with the behavior of flip-flops, used as input synchronizers, in particular when they operate in the metastable region. It is shown first, theoretically as well as experimentally, that the average rate of system failures, due to the occurrence of metastable states (MSSs), is independent of circuit noise. A formula which describes the probability of occurrence of a metastable state has been derived. To verify the theory, measurements have been made on a flip-flop made in n-channel MOS technology. Also a method is given for predicting the average number of system failures, for a given flip-flop, occurring over a year. This method is applied to predict this average failure rate for the designed synchronizer.     

IST-LASAGNE: towards all-optical label swapping employing optical logic gates and optical flip-flops

The Information Society Technologies-all-optical LAbel SwApping employing optical logic Gates in NEtwork nodes (IST-LASAGNE) project aims at designing and implementing the first, modular, scalable, and truly all-optical photonic router capable of operating at 40 Gb/s. The results of the first project year are presented in this paper, with emphasis on the implementation of network node functionalities employing optical logic gates and optical flip-flops, as well as the definition of the network architecture and migration scenarios.     

Split-level precharge differential logic: a new type of high-speedcharge-recycling differential logic

In this paper, a new charge-recycling differential logic named split-level precharge differential logic (SPDL) is presented. It employs a new push-pull type output driver which is simple and separated from the NMOS logic tree. Therefore, it can improve energy efficiency, driving capability, and reliability compared with the previous differential logic structures which use cross-coupled inverters as the output driver. To verify the reliability and the applicability of the proposed SPDL in VLSI systems, an 8-bit full adder is fabricated in a 0.6-μm CMOS technology. Experimental results show that the performance of the SPDL is about two times as good as that of the previous half-rail differential logic (HRDL) in terms of power-delay product. Moreover, the SPDL has stable operation under mismatch or parameter variation     

A new differential space-time block coding scheme

We present a new differential space-time block code (DSTBC). The scheme can be represented by a trellis and decoded using the Viterbi algorithm. It provides a differential coding gain of 1 dB due to redundancy introduced in the differential encoding and it is only 2 dB away from the corresponding coherent space-time block code (STBC).     

All-optical network subsystems using integrated SOA-based optical gates and flip-flops for label-swapped networks

In this letter, we demonstrate that all-optical network subsystems, offering intelligence in the optical layer, can be constructed by functional integration of integrated all-optical logic gates and flip-flops. In this context, we show 10-Gb/s all-optical 2-bit label address recognition by interconnecting two optical gates that perform xor operation on incoming optical labels. We also demonstrate 40-Gb/s all-optical wavelength-switching through an optically controlled wavelength converter, consisting of an integrated flip-flop prototype device driven by an integrated optical gate. The system-level advantages of these all-optical subsystems combined with their realization with compact integrated devices, suggest that they are strong candidates for future packet/label switched optical networks.