A high-throughput energy-efficient passive optical datacenter network

Datacenter applications impose heavy demands on bandwidth and also generate a variety of communication patterns (unicast, multicast, incast, and broadcast). Supporting such traffic demands leads to networks built with exorbitant facility costs and formidable power consumption if conventional design is followed. In this paper, we propose a novel high-throughput datacenter network that leverages passive optical technologies to efficiently support communications with mixed traffic patterns. Our network enables a dynamic traffic allocation that caters to diverse communication patterns at low power consumption. Specifically, our proposed network consists of two optical planes, each optimized for specific traffic patterns. We compare the proposed network with its optical and electronic counterparts and highlight its potential benefits in terms of facility costs and power consumption reductions. To avoid frame collisions, a high-efficiency distributed protocol is designed to dynamically distribute traffic between the two optical planes. Moreover, we formulate the scheduling process as a mixed integer programming problem and design three greedy heuristic algorithms. Finally, simulation results show that our proposed scheme outperforms the previous POXN architecture in terms of throughput and mean packet delay.     

平行光纤互联技术：高性能和低能耗的结合

This paper analyzes the physical potential,computing performance benefit and power consumption of optical interconnects. Compared with electrical interconnections, optical ones show undoubted advantages based on physical factor analysis. At the same time, since the recent developments drive us to think about whether these optical interconnect technologies with higher bandwidth but higher cost are worthy to be deployed, the computing performance comparison is performed. To meet the increasing demand of large-scale parallel or multi-processor computing tasks, an analytic method to evaluate parallel computing performance of interconnect systems is proposed in this paper. Both bandwidth-limit model and full-bandwidth model are under our investigation. Speedup and efficiency are selected to represent the parallel performance of an interconnect system. Deploying the proposed models, we depict the performance gap between the optical and electrically interconnected systems. Another investigation on power consumption of commercial products showed that if the parallel interconnections are deployed, the unit power consumption will be reduced. Therefore, from the analysis of computing influence and power dissipation, we found that parallel optical interconnect is valuable combination of high performance and low energy consumption. Considering the possible data center under construction, huge power could be saved if parallel optical interconnects technologies are used.     

RAPID: reconfigurable and scalable all-photonic interconnect for distributed shared memory multiprocessors

In this paper, we describe the design and analysis of a scalable architecture suitable for large-scale distributed shared memory (DSM) systems. The approach is based on an interconnect technology which combines optical components and a novel architecture design. In DSM systems, numerous shared memory transactions such as requests, responses and acknowledgment messages propagate simultaneously in the network. As the network size increases, network contention results in increasing the critical remote memory access latency, which significantly penalizes the performance of DSM systems. In our proposed architecture called reconfigurable and scalable all-photonic interconnect for distributed-shared memory (RAPID), we provide high connectivity by maximizing the channel availability for remote communication to reduce the critical remote latency. RAPID provides fast and efficient unicast, multicast and broadcast capabilities using a combination of aggressively designed wavelength division multiplexing (WDM), time division multiplexing (TDM), and space division multiplexing (SDM) techniques. RAPID is wavelength-routed, permitting the same limited set of wavelength to be reused among all processors. We evaluated RAPID based on network characteristics, power budget criteria, and by simulation using synthetic traffic workloads and compared it against other networks such as electrical ring, torus, mesh, and hypercube networks. We found that RAPID outperforms all networks and still provides good performance as the network is scaled to very large numbers.     

Proposed Low-Power High-Speed Microring Resonator-Based Switching Technique for Dynamically Reconfigurable Optical Interconnects

The dynamic bandwidth re-allocation (DBR) technique balances traffic by re-allocating bandwidth from under-utilized links to over-utilized links in a network. In this letter, we propose a nonblocking, fast, low-power, and integratable optical switch that enables DBR. The basic building blocks of the proposed switch are silicon-on-insulator-based microring resonators. Analytical and numerical studies show that the active switch design gives similar performance in throughput and latency, while reducing cost (number of lasers) and area significantly when compared to implementation of DBR with only passive components. There is a slight increase in power (~0.4% for worst-case traffic pattern) using the active switch implementation.     

An architecture for next-generation radio access networks

With fourth-generation wireless technologies envisioned to provide high bandwidth for content-rich multimedia applications, next-generation mobile communication systems are well poised to lead the technology march. Incumbent with the new technology is the challenge of providing flexible, reconfigurable architectures capable of catering to the dynamics of the network, while providing cost-effective solutions for service providers. In this article we focus on IP-based radio access network architectures for next-generation mobile systems. We provide an insight into wireless mesh-based connectivity for the RAN network elements - using short high-bandwidth links to interconnect the network entities in a multihop mesh network for backhauling traffic to the core. A generic self-similar fractal topology, using optical wireless transmission technology, is described. We study the performance of the architecture and conclude that mesh-based architectures are well suited to provide highly scalable, dynamic radio access networks with carrier-class features at significantly low system costs.     

Chip-to-chip optical interconnects: more bandwidth,more powerful

This paper aims to compare the electrical chip-to-chip interconnects and optical interconnect from the physical view and the computing performance view. Using transmission line theory, the constraints of transmission bandwidth is obtained. The calculation indicates that ideal maximum electrical capacity density is much lower than the experimental optical interconnected one. In this calculation, all the parameters come from International Technology Roadmap for Semiconductors (ITRS) and reports of world-class laboratories. Compared with bandwidth, application is a more important factor, which has great influence on the technology development direction and deployment in the real scenarios. Therefore, we take fast Fourier transform (FFT) computation as an example to study whether and how the optical interconnect technology has influences on the computing performance. One of most popular topology, mesh architecture is evaluated in this paper. The results illustrate the bandwidth increase will lift up the speedup and efficiency, especially for the clusters with many processors working cooperatively. From the above analysis, it is shown that the unique features of optical interconnects make it possible to provide more bandwidth, and then bring great advantage to computing performance.     

CDMA bus-based on-chip interconnect infrastructure

As technology scales toward deep submicron, the integration of complete system-on-chip (SoC) designs consisting of large number of Intellectual Property (IP) blocks (cores) on the same silicon die is becoming technically feasible. Until recently, the design-space exploration for SoCs has been mainly focused on the computational aspects of the problem. However, as the number of IP blocks on a single chip and their performance continue to increase, a shift from computation-based to communication-based designs becomes mandatory. As a result, the communication architecture plays a major role in the area, performance and energy consumption of the overall systems [Pasricha S, Dutt N. On-chip communication architectures: system on chip interconnect. Amsterdam: Elsevier Inc.; 2008, Kim J, Verbauwhede I, Chang MCF. Design of an interconnect architecture and signaling technology for parallelism in communication. IEEE Trans VLSI Syst 2007;15(8):881-94].This article presents a structure of a wrapper as a component of Code Division Multiple Access, CDMA, based shared bus architecture in a SoC. Two types of wrappers can be identified, master and slave. A master wrapper is located between the arbiter and CDMA coded physical interconnect, while a slave connects the CDMA coded bus with memory/peripheral module. In the proposal, only bus lines that carry address and data signals are CDMA coded. We implemented a pair of master-slave wrapper described in VHDL and confirmed its functionality using testbenches. Also we synthesized wrappers using a Xilinx Spartan and Virtex devices to determine resource requirements in respect to a number of equivalent gates, communication bandwidth, latency and power consumption. Specifically we involved a Design_Quality, DQ, metric for wrapper performance evaluation. A pair of master-slave wrapper seems to occupy appropriate space, in average 2000 equivalent gates, considering CPU cost of about 30,000 gates, what is less than 8% of hardware overhead per CPU. We also present experimental results which show that benefits of involving CDMA coding relates both to decreasing a number of bus lines and accomplishing simultaneous multiple master-slave connections at relatively low-power consumption and high communication bandwidth. Convenient range indices R_W and R_R to determine data transfer rate for Write and Read operations in multiprocessor bus systems that use TDMA and CDMA data transfer techniques. The obtained results show that increased data transfer latencies involved by CDMA data transfer are compensated by simultaneous master-slave transfers.     

Predictions of CMOS compatible on-chip optical interconnect

Interconnect has become a primary bottleneck in the integrated circuit design process. As CMOS technology is scaled, the design requirements of delay, power, bandwidth, and noise due to the on-chip interconnects have become more stringent. New design challenges are continuously emerging, such as delay uncertainty induced by process and environmental variations. It has become increasingly difficult for conventional copper interconnect to satisfy these design requirements. On-chip optical interconnect has been considered as a potential substitute for electrical interconnect. In this paper, predictions of the performance of CMOS compatible optical devices are made based on current state-of-the-art optical technologies. Electrical and optical interconnects are compared for various design criteria based on these predictions. The critical dimensions beyond which optical interconnect becomes advantageous over electrical interconnect are shown to be approximately one-tenth of the chip edge length at the 22 nm technology node.     

Design of a hybrid switching architecture for avionic WDM platforms

A novel hybrid switching architecture using optical circuit switching for intra-subnet communication and fiber channel（FC）for inter-subnet communication is proposed.The proposed scheme utilizes small-size arrayed waveguide grating routers（AWGRs）and legacy FC switches to construct the large-scale avionic network,thus has the potential of the lower latency,the satisfactory network bandwidth and the lower power consumption.The simulation results verify that the proposed architecture outperforms FC switched architecture in terms of real time performance and power consumption.     

Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication

The need for efficient interconnect architectures beyond the conventional time-division multiplexing (TDM) protocol-based interconnects has been brought on by the continued increase of required communication bandwidth and concurrency of small-scale digital systems. To improve the overall system performance without increasing communication resources and complexity, this paper presents a cost-effective interconnect architecture, communication protocol, and signaling technology that exploits parallelism in board-level communication, resulting in shorter latency and higher concurrency on a shared bus or link: the proposed source synchronous CDMA interconnect (SSCDMA-I) enables dual concurrent transactions on a single wire line as well as flexible input/output (I/O) reconfiguration. The SSCDMA-I utilizes 2-bit orthogonal CDMA coding and a variation of source synchronous clocking for multilevel superposition; a single 3-level SSCDMA-I line operates as if it consists of dual virtual time-multiplexed interconnects, which exploits communication parallelism with a reduced number of pins, wires, and complexity. The unique multiple access capability of the SSCDMA-I improves real-time communication between multiple semiconductor intellectual property (IP) blocks on a shared link or bus by reducing the bus contention interference from simultaneous traffic requests and by taking advantage of shorter request latency. The prototype transceiver chip is implemented in 0.18-m CMOS and the 10-cm test PC board system achieves an aggregate data rate of 2.5 Gb/s/pin between four off-chip (2Tx-to-2Rx) I/Os.     

Monolithic integration of diffractive lenses with LED-arrays forboard-to-board free space optical interconnect

Since optical interconnections can severely reduce problems associated with electrical interconnect technology (including bandwidth limitations, electromagnetic cross talk, signal delay and EMI aspects), the development of suitable electrooptic components is of crucial importance for implementation of optical interconnects in future computer systems. This paper addresses the design, modeling, fabrication as well as experimental assessment of LED-arrays, with diffractive lenses etched into the rear side of the LED-substrate. The suitability of such optical sources for board-to-board optical interconnections will be demonstrated     

Five-port silicon optical router based on Mach-Zehnder optical switches for photonic networks-on-chip

With the continuous development of integrated circuits, the performance of the processor has been improved steadily. To integrate more cores in one processor is an effective way to improve the performance of the processor, while it is impossible to further improve the property of the processor by only increasing the clock frequency. For a processor with integrated multiple cores, its performance is determined not only by the number of cores, but also by communication efficiency between them. With more processor cores integrated on a chip, larger bandwidths are required to establish the communication among them. The traditional electrical interconnect has gradually become a bottleneck for improving the performance of multiple-core processors due to its limited bandwidth, high power consumption, and long latency. The optical interconnect is considered as a potential way to solve this issue. The optical router is the key device for realizing the optical interconnect. Its basic function is to achieve the data routing and switching between the local node and the multi-node. In this paper we present a five-port optical router for Mesh photonics network-on-chip. A five-port optical router composed of eight thermally tuned silicon Mach-Zehnder optical switches is demonstrated. The experimental spectral responses indicate that the optical signal-to-noise ratios of the optical router are over 13 dB in the wavelength range of 1525-1565 nm for all of its 20 optical links. Each optical link can manipulate 50 wavelength channels with the channel spacing of 100 GHz and the data rate of 32 Gbps for each wavelength channel in the same wavelength range. The lowest energy efficiency of the optical router is 43.4 fJ/bit.     

Adaptive bandwidth mechanism using dual rate OLT for energy efficient WDM–TDM passive optical network

This paper reviews various energy efficient approaches in existence and proposes a Hybrid WDM–TDM PON architecture that allows the adaptive bandwidth allocation mechanism to reduce central office power consumption with acceptable performance. Our proposed architecture allows sending two signals, one broadband and other narrowband to each optical networking unit so an appropriate signal can be utilized according to the traffic demand. In case of very low traffic, only narrowband signal is used and a significant amount of energy consumption and OPEX is reduced. By using \(2\times \hbox {N}\) power splitter and interleaver, proposed architecture provides broadcasting at both broadband and narrowband signal depending on the required link rate. This further reduces energy consumption and OPEX by avoiding the transmission of same signal from multiple sources. Offered data rates to the optical distribution networks (ODNs) may also be varied by doubling the wavelength spacing of remote node AWG so that two contiguous wavelengths can be transmitted at each port or ODN. This provides the geographical dynamic bandwidth allocation. Proposed architecture also support simultaneous transmission of both broadband and narrowband signals to the ODN to provide bandwidth scalability and network extensibility for supporting future access network in terms of new users and data rates. As two signals are reaching to any ODN, resiliency against OLT TRx and line card failure is also achieved. The performance of the proposed design is verified by simulation results in terms of bit error rate and receiver sensitivity to demonstrate its feasibility for the next-generation optical access network.     

可重构阵列处理器光电混合互连原型系统实现

高效视频编码(HEVC)标准在提升编码性能的同时,对系统带宽提出了更高的要求。传统电互连方式存在带宽小和时延大的问题,而光互连的高带宽和低功耗为片上资源数据通信提出了新的解决方案。然而由于工艺水平的限制,集成光器件无法在现场可编程门阵列(FPGA)芯片内部实现。采用片外光器件模拟片上光互连系统可以达到原型验证的目的。文章基于BEE4开发平台在单片上采用电互连方式进行数据通信,在Xilinx V6系列芯片间通过接入4通道小型可插拔+(QSFP+)光模块搭建光通信链路,构建光通信网络,实现了光电混合互连网络原型系统。以分辨率176×144的标准测试序列akiyoqcif176×144.yuv为例进行测试,实验结果表明,以光链路替代片间电通信能够正确实现,且板间传输时间仅为电互连的一半,综合频率为51.327 MHz。     

Power minimization and technology comparisons for digitalfree-space optoelectronic interconnections

This paper investigates the design optimization of digital free-space optoelectronic interconnections with a specific goal of minimizing the power dissipation of the overall link, and maximizing the interconnect density. To this end, we discuss a method of minimizing the total power dissipation of an interconnect link at a given bit rate. We examine the impact on the link performance of two competing transmitter technologies, vertical cavity surface emitting lasers (VCSELs) and multiple quantum-well (MQW) modulators and their associated driver-receiver circuits including complementary metal-oxide-semiconductor (CMOS) and bipolar transmitter driver circuits, and p-n junction photodetectors with multistage transimpedance receiver circuits. We use the operating bit-rate and on-chip power dissipation as the main performance measures. Presently, at high bit rates (>800 Mb/s), optimized links based on VCSELs and MQW modulators are comparable in terms of power dissipation. At low bit rates, the VCSEL threshold power dominates. In systems with high bit rates and/or high fan-out, a high slope efficiency is more important for a VCSEL than a low threshold current. The transmitter driver circuit is an important component in a link design, and it dissipates about the same amount of power as that of the transmitter itself. Scaling the CMOS technology from 0.5 μm down to 0.1 μm brings a 50% improvement in the maximum operating bit rate, which is around 4 Gb/s with 0.1 μm CMOS driver and receiver circuits. Transmitter driver circuits implemented with bipolar technology support a much higher operating bandwidth than CMOS technology; they dissipate, however, about twice the electrical power. An aggregate bandwidth in excess of 1 Tb/s-cm² can be achieved in an optimized free-space optical interconnect system using either VCSELs or MQW modulators as its transmitters     

Optical I/O Technology for Tera-Scale Computing

This paper describes both a near term and a long term optical interconnect solution, the first based on a packaging architecture and the second based on a monolithic photonic CMOS architecture. The packaging-based optical I/O architecture implemented with 90 nm CMOS transceiver circuits, 1 × 12 VCSEL/detector arrays and polymer waveguides achieves 10 Gb/s/channel at 11 pJ/b. A simple TX pre-emphasis technique enables a potential 18 Gb/s at 9.6 pJ/b link efficiency. Analysis predicts this architecture to reach less than 1 pJ/b at the 16 nm CMOS technology node. A photonic CMOS process enables higher bandwidth and lower energy-per-bit for chip-to-chip optical I/O through integration of electro-optical polymer based modulators, silicon nitride waveguides and polycrystalline germanium (Ge) detectors into a CMOS logic process. Experimental results for the photonic CMOS ring resonator modulators and Ge detectors demonstrate performance above 20 Gb/s and analysis predicts that photonic CMOS will eventually enable energy efficiency better than 0.3 pJ/b with 16 nm CMOS. Optical interconnect technologies such as these using multi-lane communication or wavelength division multiplexing have the potential to achieve TB/s interconnect and enable platforms suitable for the tera-scale computing era.     

A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects

Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution to address the increasing chip-to-chip I/O bandwidth demands. This paper describes a dense, high-speed, and low-power CMOS optical interconnect transceiver architecture. Vertical-cavity surface-emitting laser (VCSEL) data rate is extended for a given average current and corresponding reliability level with a four-tap current summing FIR transmitter. A low-voltage integrating and double-sampling optical receiver front-end provides adequate sensitivity in a power efficient manner by avoiding linear high-gain elements common in conventional transimpedance-amplifier (TIA) receivers. Clock recovery is performed with a dual-loop architecture which employs baud-rate phase detection and feedback interpolation to achieve reduced power consumption, while high-precision phase spacing is ensured at both the transmitter and receiver through adjustable delay clock buffers. A prototype chip fabricated in 1 V 90 nm CMOS achieves 16 Gb/s operation while consuming 129 mW and occupying 0.105 mm².     

100 channel optical FDM technology and its applications to opticalFDM channel-based networks

Optical frequency division multiplexing (optical FDM) technology, which allows the use of an extremely broad lightwave bandwidth (10-200 THz and over) and can realize transport systems that could replace the current digital (time division multiplexing based) transport networks, is described. The future outlook for communication networks based on optical FDM technology is assessed. Based on the technical results obtained from a 100-channel optical FDM experiment, of an optical FDM channel concept is proposed and a viable architecture for optical FDM-channel-based networks is developed     

带有前置EDFA卫星相干激光通信终端的信噪比分析

卫星激光通信链路是一项实现卫星大规模星座组网的关键技术。相干激光链路灵敏度高、抗背景干扰、速率升级空间大,在星间激光链路中应用广泛。文章建立了带有前置掺铒光纤放大器(EDFA)的卫星相干激光通信终端的信噪比分析模型,仿真分析了EDFA功率增益、EDFA噪声系数、本振光功率、信号光功率、光放后端光带宽、基带前端电带宽对终端输出信噪比的影响以及各种输出噪声功率占比的情况,得到了带有前置EDFA卫星相干激光通信终端的信噪比参数特性。