热氮化SiO_2膜性能的试验研究

本文报导对热氮化SiO_2膜的研究结果.热氮化SiO_2膜的腐蚀特性、抗氧化特性的研究表明膜的化学结构与SiO_2不同.采用AES表面分析技术观察了膜中化学成份,从而证实了膜中的氮含量取决于氮化前的SiO_2膜厚和氮化时的条件,热氮化SiO_2膜的电学特性、抗辐射性能明显优于SiO_2膜.     

快速热氮化超薄SiO_2膜特性的研究

本文主要研究了超薄快速热氮化(Rapid Thermal Nitridation)SiO_2膜在高电场下的电特性和抗辐照特性,采用AES和XPS等技术分析了RTN SiO_2膜的成份和结构。与同厚SiO_2膜相比,RTN SiO_2膜具有许多明显的优点,在同样条件下,当电场强度E≈1.5×10~7V/cm时,击穿时间t_(bd)比SiO_2的约高两个量级;在经过剂量高达10~7rad的Co~(60)辐照后,SiO_2膜的界面态密度及漏电流均增大1—2个量级,而RTN SiO_2膜的变化非常小。     

PECVD SiO_2薄膜应力特性的研究

本文分析了等离子增强化学汽相淀积(PECVD)SiO_2膜的淀积过程,用激光束偏转法测量衬底形变弯曲技术研究了SiO_2膜的应力特性,讨论了SiO_2膜的应力与膜厚、折射率、测量温度及退火温度的关系,最后分析了SiO_2膜本征应力的产生机制。     

用射频溅射控制SiO_2的性质

用溅射法制得的SiO_2膜优点很多,但存在离子污染问题,其中正电荷将使SiO_2膜退化。本文介绍将氟离子溅射到SiO_2膜中以抵消正电荷的有效解决方法。实验方法采用MRC SEM—8620型溅射仪,功率1.5千瓦,可进行溅射腐蚀及射频偏置溅射等操作。实验时,将靶子与衬底夹具之间的距离调节到5cm,靶子采用MRC公司生产的IC级SiO_2,直径6英寸,厚3/16英寸。     

离子辅助淀积SiO_2和TiO_2膜的特性

用同Ebert研制成的类似的氧离子源研究了SiO_2和TiO_2膜的反应淀积。这离子源通过直流气体放电产生负氧离子,然后用石墨出孔把锥形负离子束引向衬底。此源在400V放电电压下产生1.26mA的离子流。淀积所用原料是由电阻加热舟蒸发的SiO和TiO。测得TiO_2膜的光学常数表明,提高离子流就降低了膜的吸收常数,提高了膜的折射率。借助红外衰减全反射率测量研究SiO_2膜的化学配比、潮气含量及悬挂键。这些测量指出,离子流提高时,SiO_2膜的化学配比接近SiO_2。     

PECVD SiO_2-InP MIS结构研究

本文报导用正硅酸乙酯等离子增强化学汽相淀积(PECVD)技术在InP上淀积SiO_2膜的方法,用C—V,DLTS,AES,XPS等手段测量分析了PECVD SiO_2-InP MIS结构的电学性质和界面化学结构,研究了淀积前InP表面的不同处理对界面特性的影响。     

SiO_2薄膜低击穿机理的研究

用扫描内光电发射法结合液晶显示法与自愈击穿法研究了SiO_2薄膜低击穿的起因,得到液晶显示的SiO_2膜中的缺陷是膜层低击穿的原因,而膜中可动正离子在缺陷处的堆积则引起击穿电压进一步降低的结论.     

MoNb/SiO_2界面的AES分析

用电子束蒸发MoNb的方法,制备了MoNb/SiO_2接触界面。用俄歇电子能谱(AES)测定该界面热处理前后各元素组分随深度的分布。从AES分析中发现:随着热处理温度的上升,MoNb/SiO_2界面中Mo,O渐渐出现再分布峰,形成Mo,O的富集区;Nb的富集区始终为平坦分布,并没有出现Nb的再分布峰。界面宽度由低温的1.5nm变到600℃的15nm;同时还发现600℃时界面呈现电阻性。这一异常现象是由于Mo在SiO_2界面中热稳定性差所导致的。     

SiO_2/NiO复合纳米颗粒的制备及表征

提出了共溶胶双水解的方法来制备SiO_2基复合纳米材料,并用氧化镍作为复合对象来制备SiO_2/NiO复合纳米颗粒。利用X射线衍射仪(XRD)、扫描电子显微镜(SEM)、能量色散谱(EDS)和透射电子显微镜(TEM)等方法对复合纳米颗粒的形貌和结构进行了表征。测试结果表明:该方法成功制备出了SiO_2/NiO复合纳米颗粒。该复合纳米颗粒是由SiO_2与NiO两种物质构成的,其中SiO_2小球是非晶结构的,粒径为200～300 nm;NiO纳米颗粒是多晶结构的,直径在20 nm左右。每个SiO_2小球上复合的NiO纳米颗粒数目并不均一,但是复合纳米颗粒分散性比较好,几乎没有团聚现象产生。最后,对这种制备方法的合成机理进行了初步的解释。     

通过磷硅玻璃—SiO_2膜的钠离子漂移

由热氧化在 SiO_2层上形成的磷硅玻璃膜能显著提高硅平面结型器件和场效应晶体管的表面稳定性,若无磷硅玻璃膜,由于 SiO_2层中易动的钠离子的漂移和积累会引起硅表面电位很大的变化。这是因为最初在 SiO_2中存在的移动性的碱离子在磷硅玻璃膜的形成中被磷硅玻璃捕获,其后在玻璃中也有被捕获的倾向,有关磷硅玻璃的作用过去已作了报导。本文对磷硅玻璃的组成和钠离子浓度二者在 MOS 结构中作了系统的改变。进而测量了     

在SiO2中掺A1对Au／纳米（SiO2／Si／SiO2）／p—Si结构电致发光的影响

利用射频磁控溅射方法,制成纳米SiO2层厚度一定而纳米Si层厚度不同的纳米（SiO2/Si/SiO2）/p-Si结构和纳米（SiO2:A1/Si/SiO2:A1)/p-Si结构,用磁控溅射制备纳米SiO2:A1时所用的SiO2/A1复合靶中的A1的面积百分比为1%。上述两种结构中Si层厚度均为1-3nm,间隔为0.2nm。为了对比研究,还制备了Si层厚度为零的样品。这两种结构在900℃氮气下退火30min,正面蒸半透明Au膜,背面蒸A1作欧姆接触后,都在正向偏置下观察到电致发光（EL）。在一定的正向偏置下,EL强度和峰位以及电流都随Si层厚度的增加而同步振荡,位相相同。但掺A1结构的发光强度普遍比不掺A1结构强。另外,这两种结构的EL具体振荡特性有明显不同,对这两种结构的电致发光的物理机制和SiO2中掺A1的作用进行了分析和讨论。     

Hot-carrier injections in SiO2

We review the hot-carrier injection phenomena in gate-oxide and the related degradation in silicon MOSFETs. We discuss the basic degradation mechanisms and the nature of the created defects by carrier injections through the gate-oxide. Emphasis is put on the discussion of dynamic hot-carrier injections in MOSFETs and on the stress induced leakage currents in very thin (< 5 nm) gate-oxide.     

具有SiO2/SiNX/SiO2 复合绝缘层的有机薄膜晶体管

We have investigated a SiO_2/SiN_x/SiO_2 composite insulation layer structured gate dielectric for an organic thin film transistor(OTFT) with the purpose of improving the performance of the SiO_2 gate insulator. The SiO_2/SiN_x/SiO_2 composite insulation layer was prepared by magnetron sputtering.Compared with the same thickness of a SiO_2 insulation layer device,the SiO_2/SiN_x/SiO_2 composite insulation layer is an effective method of fabricating OTFT with improved electric characteristics and decrease...     

Comparison of electrical stress-induced charge carrier generation/trapping and related degradation of SiO2 and HfO2/SiO2 gate dielectric stacks

We compare charge carrier generation/trapping related degradation in control oxide (SiO₂) and HfO₂/SiO₂ stack of an identical equivalent-oxide-thickness (EOT) during constant gate voltage stress of n-type metal-oxide-semiconductor (nMOS) capacitors. Irrespective of these two dielectrics, the kinetics of generation of both surface states and oxide-trapped positive charges are found to be similar. Our analysis shows that the positive oxide charge buildup during CVS is due to trapping of protons by the strained SiOSi bonds in either of the devices. We demonstrate that compared to SiO₂ devices, HfO₂ devices with an equal EOT better perform in CMOS logic applications. On the other hand, our results indicate that the control oxide is better in charge trapping memory devices. Furthermore, the lifetime of the control oxide devices is observed longer than that of HfO₂ devices at a given operating voltage.     

The doped Si/SiO2 interface

A study is reported of the influence of dopant atoms on the SiSiO₂ interface states of thermally oxidized silicon. It was found that acceptor or donor atoms induce interface states and oxide charges. The effect is largest in the case of acceptor dopants and is independent of the doping process. The influence of the dopant atoms on oxide charge is probably related to the different segregation coefficients of acceptors and donors.     

Time-dependent-dielectric-breakdown characteristics of Hf-doped Ta2O5/SiO2 stack

The Time-Dependent-Dielectric Breakdown (TDDB) characteristics of MOS capacitors with Hf-doped Ta₂O₅ films (8 nm) have been analyzed. The devices were investigated by applying a constant voltage stress at gate injection, at room and elevated temperatures. Stress voltage and temperature dependences of hard breakdown of undoped and Hf-doped Ta₂O₅ were compared. The doped Ta₂O₅ exhibits improved TDDB characteristics in regard to the pure one. The maximum voltage projected for a 10 years lifetime at room temperature is −2.4 V. The presence of Hf into the matrix of Ta₂O₅ modifies the dielectric breakdown mechanism making it more adequate to the percolation model. The peculiarities of Weibull distribution of dielectric breakdown are discussed in terms of effect of three factors: nature of pre-existing traps and trapping phenomena; stress-induced new traps generation; interface layer degradation.     

Flat-field spectrograph in SiO2/Si

The operation of a flat-field spectrograph in silica glass on silicon (SiO₂/Si) as a demultiplexer with 4-nm channel spacing in the 1.5-μm waveguide length region is demonstrated. The concept allows fabrication tolerances to be compensated simultaneously with the adjustment of fan-out. Fiber-to-fiber insertion loss of 10.1 dB and crosstalk attenuation >15 dB have been achieved     

Thermally stimulated current in SiO2

Thermally stimulated current (TSC) techniques provide information about oxide-trap charge densities and energy distributions in MOS (metal-oxide-semiconductor) capacitors exposed to ionizing radiation or high-field stress that is difficult or impossible to obtain via standard capacitance–voltage or current–voltage techniques. The precision and reproducibility of measurements through repeated irradiation/TSC cycles on a single capacitor is demonstrated with a radiation-hardened oxide, and small sample-to-sample variations are observed. A small increase in E′_δ center density may occur in some non-radiation-hardened oxides during repeated irradiation/TSC measurement cycles. The importance of choosing an appropriate bias to obtain accurate measurements of trapped charge densities and energy distributions is emphasized. A 10 nm deposited oxide with no subsequent annealing above 400°C shows a different trapped-hole energy distribution than thermally grown oxides, but a similar distribution to thermal oxides is found for deposited oxides annealed at higher temperatures. Charge neutralization during switched-bias irradiation is found to occur both because of hole-electron annihilation and increased electron trapping in the near-interfacial SiO₂. Limitations in applying TSC to oxides thinner than 5 nm are discussed.     

Accelerated testing of SiO2 reliability

This paper compares several popular accelerated test methods for projecting SiO₂ lifetime distribution or failure rate: constant-voltage and constant-current time-to-breakdown and charge-to-breakdown tests, ramp-voltage breakdown test, and ramp-current charge to-breakdown test. Charge trapping affects the electric field acceleration parameter for time-to-breakdown and the value of breakdown voltage. Practical considerations favor ramp breakdown testing for gate oxide defect characterization. The effective thinning model is used for defect characterization and the ramp-voltage breakdown test is shown to be superior to the ramp-current Q_BD test for extraction of the defect distribution. Measurement issues are also discussed     

Pre-breakdown in thin SiO2 films

The on-off fluctuations of the tunnel current in 5.6 nm SiO₂ films before dielectric breakdown are analyzed in detail. For this purpose, a low noise measurement system has been realized which allows detection of pre-breakdown phenomena and interruption of the stress before catastrophic failure occurs. A spectral analysis of these fluctuations is presented along with preliminary results of the experiments made possible, for the first time, by the new measurement system