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当前,集成电路的生产趋向不仅单位面积的集成度一再提高,器件封装更向空间发展.主要的存储器生产厂都将采用多芯片封装(MCP)形式作为未来存储器件封装的重点发展方向之一.本文着重阐述针对越来越大的多芯片封装存储器大规模量产测试需要,作为占据测试领域领先地位的爱德万测试ADVANTEST所提供的,涵盖从设计端到最终成品测试整个产品链的业界最尖端的完整解决方案. 相似文献
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惠瑞捷(Verigy)推出了全新的HSM3G高速存储器测试解决方案,进一步拓展了面向DDR3世代主流存储器Ic和更高级存储器件测试能力的V93000HSM平台。 相似文献
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存储器制造商一直在寻找一种既能满足其生产和功能需求又能提供比一代器件寿命更长、投资价值更高的节约型ATE解决方案。针对上述需求,惠瑞捷(Verigy)公司推出了HSM3G高速存储器测试解决方案,进一步拓展了面向DDR3世代主流存储器芯片和更高级存储器件测试能力的V93000 HSM平台。 相似文献
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HSM3G高速存储器测试解决方案进一步拓展了面向DDR3主流存储器IC和更高级存储器件测试的V93000HSM平台。
V93000 HSM3G独特的优势在于其未来的可升级性,速度和功能将来都可以升级,其可编程的、快速的每引脚APG能力得到了数据总线倒置(DBI)和循环冗余校验码(CRC)数据的支持, 相似文献
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《红外技术》2017,(11):1066-1070
微通道板(简称MCP)是决定像增强器信噪比的关重件,MCP的噪声因子是对MCP噪声特性进行评价研究的主要参数。通过对不同材料、不同腐蚀工艺、不同烧氢工艺制备的MCP以及不同工作条件下MCP的噪声因子进行测试分析,研究不同制备工艺、不同工作条件下MCP的噪声特性,最终得出了最优噪声性能的MCP制备工艺和工作条件,结果表明采用B材料,采用混合类腐蚀液腐蚀工艺,尽可能长的烧氢时间,可获得较低噪声因子的MCP,同时适当增加入射电子能量和微通道板工作电压以改善通道板噪声特性,提高像管成像质量,这些研究成果为进一步降低MCP噪声因子提供了理论和工艺指导。 相似文献
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周震一 《电子工业专用设备》2008,37(5):54-56
近年来IC工业的快速发展对于自动测试设备(ATE)在架构、成本等方面提出了挑战。面对需求,ADVANTEST提出了开放架构测试平台的标准----OPENSTAR以及基于此标准的T2000SoC测试系统,其中T2000GSMF是最新发布的低成本的ATE解决方案。 相似文献
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Breeta SenGupta Dimitar Nikolov Urban Ingelsson Erik Larsson 《Journal of Electronic Testing》2017,33(1):7-23
This paper addresses reduction of test cost for core-based non-stacked integrated circuits (ICs) and stacked integrated circuits (SICs) by test planning, under power constraint. Test planning involves co-optimization of cost associated with test time and test hardware. Test architecture is considered compliant with IEEE 1149.1 standard. A cost model is presented for calculating the cost of any test plan for a given non-stacked IC and a SIC. An algorithm is proposed for minimizing the cost. Experiments are performed with several ITC’02 benchmark circuits to compare the efficiency of the proposed power constrained test planning algorithm against near optimal results obtained with Simulated Annealing. Results validate test cost obtained by the proposed algorithm are very close to those obtained with Simulated Annealing, at significantly lower computation time. 相似文献
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CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing 总被引:2,自引:0,他引:2
As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CAS-BUS that solves some of the new problems the test industry has to deal with. This TAM is scalable, flexible and dynamically reconfigurable. The CAS-BUS architecture is compatible with the IEEE P1500 standard proposal in its current state of development, and is controlled by Boundary Scan features.This basic CAS-BUS architecture has been extended with two independent variants. The first extension has been designed in order to manage SoC made up with both wrapped cores and non wrapped cores with Boundray Scan features. The second deals with a test pin expansion method in order to solve the I/O bandwidth problem. The proposed solution is based on a new compression/decompression mechanism which provides significant results in case of non correlated test patterns processing. This solution avoids TAM performance degradation.These test architectures are based on the CAS-BUS TAM and allow trade-offs to optimize both test time and area overhead. A tool-box environment is provided, in order to automatically generate the needed component to build the chosen SoC test architecture. 相似文献
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本文提出一种三维片上系统(3D SoC)的测试策略,针对硅通孔(TSV,Through Silicon Vias)互连技术的3D SoC绑定中和绑定后的测试进行优化,由于测试时间和用于测试的TSV数目都会对最终的测试成本产生很大的影响,本文的优化策略在有效降低测试时间的同时,还可以控制测试用的TSV数目,从而降低了测试成本.实验结果表明,本文的测试优化策略与同类仅考虑降低测试时间的策略相比,可以进一步降低约20%的测试成本. 相似文献
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边界扫描测试技术的原理及其应用 总被引:3,自引:1,他引:2
边界扫描技术是一种应用于数字集成电路器件的标准化可测试性设计方法,他提供了对电路板上元件的功能、互连及相互间影响进行测试的一种新方案,极大地方便了系统电路的测试。自从1990年2月JTAG与TEEE标准化委员会合作提出了“标准测试访问通道与边界扫描结构”的IEEE1149.1—1990标准以后,边界扫描技术得到了迅速发展和应用。利用这种技术,不仅能测试集成电路芯片输入/输出管脚的状态,而且能够测试芯片内部工作情况以及直至引线级的断路和短路故障。对芯片管脚的测试可以提供100%的故障覆盖率,且能实现高精度的故障定位。同时,大大减少了产品的测试时间,缩短了产品的设计和开发周期。边界扫描技术克服了传统针床测试技术的缺点,而且测试费用也相对较低。这在可靠性要求高、排除故障要求时间短的场合非常适用。特别是在武器装备的系统内置测试和维护测试中具有很好的应用前景。本文介绍了边界扫描技术的含义、原理、结构,讨论了边界扫描技术的具体应用。 相似文献
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As the system‐on‐chip (SoC) design becomes more complex, the test costs are increasing. One of the main obstacles of a test cost reduction is the limited number of test channels of the ATE while the number of pins in the design increases. To overcome this problem, a new test architecture using a channel sharing compliant with IEEE Standard 1149.1 and 1500 is proposed. It can significantly reduce the pin count for testing a SoC design. The test input data is transmitted using a test access mechanism composed of only input pins. A single test data output pin is used to measure the sink values. The experimental results show that the proposed architecture not only increases the number of sites to be tested simultaneously, but also reduces the test time. In addition, the yield loss owing to the proven contact problems can be reduced. Using the new architecture, it is possible to achieve a large test time and cost reduction for complex SoC designs with negligible design and test overheads. 相似文献
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随着目前国际集成电路封装测试产业不断向中国转移,更多国际知名公司均希望在中国找到低成本、高品质的解决方案。集成电路测试作为品质把关的重要一环,其成本在整个集成电路产业链中占有较高比重。据统计,目前有很多集成电路的测试成本已高达整个集成电路生产成本的45%以上,因此,测试成本的有效降低能够明显减少集成电路制造成本。昂贵的集成电路测试设备是导致IC量产测试成本偏高的主要因素,需要负责IC量产测试的工程技术人员不断地探索和钻研如何最有效地使用这些测试设备。本文详细地阐述了如何使用乒乓测试模式充分利用设备资源,从而有效降低IC的测试成本。 相似文献
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On IEEE P1500's Standard for Embedded Core Test 总被引:4,自引:0,他引:4
Erik Jan Marinissen Rohit Kapur Maurice Lousberg Teresa McLaurin Mike Ricchetti Yervant Zorian 《Journal of Electronic Testing》2002,18(4-5):365-383
The increased usage of embedded pre-designed reusable cores necessitates a core-based test strategy, in which cores are tested as separate entities. IEEE P1500 Standard for Embedded Core Test (SECT) is a standard-under-development that aims at improving ease of reuse and facilitating interoperability with respect to the test of core-based system chips, especially if they contain cores from different sources. This paper briefly describes IEEE P1500, and illustrates through a simplified example its scalable wrapper architecture, its test information transfer model described in a standardized Core Test Language, and its two compliance levels. The standard is still under development, and this paper only reflects the view of six active participants of the standardization committee on its current status. 相似文献
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对MCU进行测试时,如何高效生成测试向量是测试的难点.文章以8位MCU STC12C5410AD为例,详细地介绍了通过使用仿真环境,以C语言编写功能测试程序,完成芯片寄存器控制和主要逻辑单元运算,然后使用集成电路测试系统直接生成测试向量的解决方案.使用此解决方案,可根据测试要求,在较短时间内开发出MCU测试程序,节约测试开发成本. 相似文献